CAT93C4621 [CATALYST]

Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer; 监控电路与Microwire串行E2PROM CMOS ，精密复位控制器和看门狗定时器


型号：	CAT93C4621
厂家：	CATALYST SEMICONDUCTOR
描述：	Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer 监控电路与Microwire串行E2PROM CMOS ，精密复位控制器和看门狗定时器监控控制器可编程只读存储器
文件：	总10页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Advanced Information

CAT93CXXXX (1K-16K)

Supervisory Circuits with Microwire Serial CMOS E PROM, Precision Reset Controller and Watchdog Timer

FEATURES

■ Active High or Low Reset Outputs

—Precision Power Supply Voltage Monitoring

—5V, 3.3V and 3V options

■ Watchdog Timer

■ Programmable Reset Threshold

■ Built-in Inadvertent Write Protection

■ Hardware and Software Write Protection

■ Power-Up Inadvertant Write Protection

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

—V_CCLock Out

■ High Speed Operation: 3MHz

■ Low Power CMOS Technology

■ x 16 or x 8 Selectable Serial Memory

■ Self-Timed Write Cycle with Auto-Clear

■ Sequential Read

■ Commercial, Industrial, and Automotive

Temperature Ranges

■ 2.7-6.0 Volt Operation

■ 16 Byte Page Mode

■ Fast Nonvolatile Write Cycle: 3ms Max

DESCRIPTION

duringbrownoutandpowerup/downconditions. During

system failure the watchdog timer feature protects the

microcontroller with a reset signal. Catalyst's advanced

CMOS technology substantially reduces device power

requirements. The 93CXXXX isavailable in 8-pin DIP, 8-

pin TSSOP or 8-pin SOIC packages. It is designed to

endure 1,000,000 program/erase cycles and has a data

retention of 100 years.

The CAT93CXXXX is a single chip solution to three

popular functions of EEPROM memory, precision reset

controller and watchdog timer. The serial EEPROM

memoryofthe93CXXXXcanbeconfiguredeitherby16-

bits or by 8-bits. Each register can be written (or read)

by using the DI (or DO pin).

The reset function of the 93CXXXX protects the system

PIN CONFIGURATION

BLOCK DIAGRAM

93CX63X

93CX61X

93CX62X

GND

RESET

RESET(RESET) SK

RESET(RESET)

WDI

ORG

GND

RESET

GND

ADDRESS

DECODER

ORG

MEMORY ARRAY

PIN FUNCTIONS

Pin Name

Function

Chip Select

Reset I/O

DATA

RESET/RESET

OUTPUT

BUFFER

Clock Input

MODE DECODE

LOGIC

Serial Data Input

Serial Data Output

CLOCK

GENERATOR

V_CC

GND

ORG

+2.7 to 6.0V Power Supply

Ground

RESET Controller

High

Precision

Memory Organization

WATCHDOG

Vcc Monitor

Note: When the ORG pin is connected to VCC, the X16 organiza

tion is selected. When it is connected to ground, the X8 pin

is selected. If the ORG pin is left unconnected, then an

internal pullup device will select the X16 organization.

WDI RESET/RESET

Characteristics subject to change without notice

9-85

Advanced Information

CAT93CXXXX

ABSOLUTE MAXIMUM RATINGS*

COMMENT

Temperature Under Bias....................–55°C to +125°C

Storage Temperature........................ –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation

of the device at these or any other conditions outside of

those listed in the operational sections of this specifica-

tion is not implied. Exposure to any absolute maximum

rating for extended periods may affect device perfor-

mance and reliability.

Voltage on Any Pin with

(1)

Respect to Ground

..............–2.0V to +V

+ 2.0V

V_CCwith Respect to Ground..................–2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)1.0W.................................1.0W

Lead Soldering Temperature (10 secs)...............300°C

Output Short Circuit Current⁽²⁾..........................100mA

D.C. OPERATING CHARACTERISTICS

= +2.7V to +6.0V, unless otherwise specified.

Limits

Typ.

Symbol

Parameter

Min.

Max.

Units

Test Conditions

I_CC1

Power Supply Current

(Write)

f_SK= 1MHz

V_CC= 5.0V

I_CC2

I_SB1

I_SB2

Power Supply Current

(Read)

µA

f_SK= 1MHz

V_CC= 5.0V

Power Supply Current

(Standby) (x8 Mode)

CS = 0V

ORG=GND

Power Supply Current

(Standby) (x16Mode)

CS=0V

ORG=Float or V_CC

I_LI

Input Leakage Current

µA

V_IN= 0V to V_CC

I_LO

Output Leakage Current

(Including ORG pin)

V_OUT= 0V to V_CC

CS = 0V

V_IL1

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-0.1

0.8

V_CC+1

0.4

4.5V≤V_CC<5.5V

V_IH1

V_OL1

V_OH1

2.4

I_OL= 2.1mA

I_OH= -400µA

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

Stock No. 21084-01 2/98

9-86

Advanced Information

CAT93CXXXX

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min.

Max. Units

Cycles/Byte

Reference Test Method

(1)

N_END

Endurance

1,000,000

100

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(1)

T_DR

Data Retention

ESD Susceptibility

Latch-up

Years

Volts

(1)

V_ZAP

2000

(1)(3)

I_LTH

100

A.C. CHARACTERISTICS

=2.7V to 6.0V unless otherwise specified.

Output Load is 1 TTL Gate and 100pF

Limits

V_CC

4.5V-5.5V

V_CC

2.7V -6V

Test

SYMBOL PARAMETER

Min. Max.

Min. Max. UNITS Conditions

t_CSS

t_CSH

t_DIS

CS Setup Time

250

µs

CS Hold Time

DI Setup Time

250

0.5

500

t_DIH

t_PD1

t_PD0

DI Hold Time

Output Delay to 1

0.1

100

Output Delay to 0

C_L= 100pF

(1)

t_HZ

Output Delay to High-Z

Program/Erase Pulse Width

Minimum CS Low Time

Minimum SK High Time

Minimum SK Low Time

Output Delay to Status Valid

Maximum Clock Frequency

t_EW

t_CSMIN

t_SKHI

t_SKLOW

t_SV

0.5

0.1

SK_MAX

1000

3000 KHZ

(1)(2)

Power-Up Timing

Symbol

t_PUR

Parameter

Max.

Units

Power-up to Read Operation

Power-up to Write Operation

t_PUW

CAPACITANCE T = 25°C, f = 1.0 MHz, V

= 5V

Symbol

Test

Max.

Units

Conditions

V_I/O= 0V

V_IN= 0V

(1)

C_I/O

Input/Output Capacitance

Input Capacitance

(1)

C_IN

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

Stock No. 21084-01 2/98

9-87

Advanced Information

CAT93CXXXX

INSTRUCTION SET

Instruction Device

Type

Start Opcode

Bit

Address

Data

x8 x16

Comments

x16

READ

93C46XX

93C56XX⁽¹⁾

93C66XX

93C57XX

93C86XX

A6–A0

A8–A0

A7-A0

A5-A0

A7-A0

A6-A0

A9-A0

Read Address AN–A0

A10-A0

ERASE 93C46XX

93C56XX⁽¹⁾

93C66XX

A6–A0

A8–A0

A7-A0

A5-A0

A7-A0

A6-A0

A9-A0

Clear Address AN–A0

Write Address AN–A0

Write Enable

93C57XX

93C86XX

A10-A0

WRITE 93C46XX

93C56XX⁽¹⁾

93C66XX

A6–A0

A8–A0

A7-A0

A5-A0

A7-A0

A6-A0

A9-A0

D7-D0 D15-D0

93C57XX

93C86XX

A10-A0

EWEN 93C46XX

93C56XX

11XXXXX

11XXXXXXX

11XXXXXX

11XXXX

11XXXXXX

11XXXXX

93C66XX

93C57XX

93C86XX

11XXXXXXXXX 11XXXXXXXX

EWDS 93C46XX

93C56XX

00XXXXX

00XXXXXXX

00XXXXXX

00XXXX

00XXXXXX

00XXXXX

Write Disable

93C66XX

93C57XX

93C86XX

00XXXXXXXXX 00XXXXXXXX

ERAL

93C46XX

93C56XX

93C66XX

93C57XX

93C86XX

10XXXXX

10XXXXXXX

10XXXXXX

10XXXX

10XXXXXX

10XXXXX

Clear All Addresses

Write All Addresses

10XXXXXXXXX 10XXXXXXXX

WRAL

93C46XX

93C56XX

93C66XX

93C57XX

93C86XX

01XXXXX

01XXXXXXX

01XXXXXX

01XXXX

01XXXXXX

01XXXXX

D7-D0 D15-D0

01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0

Note:

(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and

ERASE commands.

Stock No. 21084-01 2/98

9-88

Advanced Information

CAT93CXXXX

RESET CIRCUIT CHARACTERISTICS

Symbol

t_GLITCH

V_RT

Parameter

Min.

Max. Units

Glitch Reject Pulse Width

Reset Threshold Hystersis

Reset Output Low Voltage (I_OLRS=1mA)

Reset Output High Voltage

100

V_OLRS

V_OHRS

0.4

Vcc-0.75

4.50

Reset Threshold (Vcc=5V)

(93CXXXX-45)

4.75

Reset Threshold (Vcc=5V)

(93CXXXX-42)

4.25

3.00

4.50

3.15

Reset Threshold (Vcc=3.3V)

(93CXXXX-30)

V_TH

Reset Threshold (Vcc=3.3V)

(93CXXXX-28)

2.85

2.55

3.00

2.70

Reset Threshold (Vcc=3V)

(93CXXXX-25)

PURST

Power-Up Reset Timeout

V_THto RESET Output Delay

RESET Output Valid

130

270

µs

RPD

V_RVALID

Figure 1. RESET Output Timing

t_GLITCH

V_TH

RVALID

V_CC

t_RPD

t_PURST

RESET

t_RPD

RESET

Stock No. 21084-01 2/98

9-89

Advanced Information

CAT93CXXXX

DEVICE OPERATION

Reset Controller Description

the existing reset threshold voltage to one of the other

four reset threshold voltages. Once the reset threshold

voltage is selected it will not change even after cycling

the power, unless the user uses the programmer to

change the reset threshold voltage. However, the

programming function is available only through external

program manufacturers. Please call Catalyst for a list of

programmer manufacturers which support this function.

The CAT93CXXXX provides a precision RESET con-

troller that ensures correct system operation during

brown-out and power-up/down conditions. It is config-

ured with open drain RESET outputs. During power-

up, the RESET outputs remain active until V_CC

reaches the V_THthreshold and will continue driving the

outputs for approximately 200ms (t_PURST) after reach-

ing V_TH.After the t_PURSTtimeout interval, the device

will cease to drive reset outputs. At this point the reset

outputs will be pulled up or down by their respective pull

up/pull down devices. During power-down, the RESET

outputs will begin driving active when V_CCfalls below

V_TH.The RESET outputs will be valid so long as V_CCis

>1.0V (V_RVALID).

Memory Functional Description

TheCAT93CXXXXisa1024/2048/4096/16,384-bitnon-

volatile memory intended for use with industry standard

microprocessors. The CAT93CXXXX can be organized

aseitherregistersof16bitsor8bits. Whenorganizedas

X16, seven 9-bit instructions for 93C46XX; seven 10-bit

instructions for 93C57XX; seven 11-bit instructions for

93C56XX and 93C66XX; seven 13-bit instructions for

93C86XX; control the reading, writing and erase opera-

tions of the device. When organized as X8, seven 10-bit

instructions for 93C46XX; seven 11-bit instructions for

93C57; seven 12-bit instructions for 93C56 and 93C66:

seven 14-bit instructions for 93C86; control the reading,

writing and erase operations of the device. The

CAT93CXXXX operates on a single power supply and

will generate on chip, the high voltage required during

any write operation.

TheRESETpinsareI/Os;therefore, theCAT93CXXXX

can act as a signal conditioning circuit for an externally

applied reset. The inputs are level triggered; that is, the

RESETinputinthe93CXXXXwillinitiatearesettimeout

after detecting a high and the RESET input in the

93CXXXX will initiate a reset timeout after detecting a

low.

Watchdog Timer

The Watchdog Timer provides an independent protec-

tion for microcontrollers. During a system failure, the

CAT93CXXXX will respond with a reset signal after a

time-out interval of 1.6 seconds for lack of activity.

Instructions, addresses, and write data are clocked into

the DI pin on the rising edge of the clock (SK). The DO

pin is normally in a high impedance state except when

reading data from the device, or when checking the

ready/busy status after a write operation.

As long as the reset signal is asserted, the Watchdog

Timer will not count and will stay cleared.

Hardware Data Protection

The ready/busy status can be determined after the start

ofawriteoperationbyselectingthedevice(CShigh)and

polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that

the device is ready for the next instruction. If necessary,

the DO pin may be placed back into a high impedance

state during chip select by shifting a dummy “1” into the

DIpin. TheDOpinwillenterthehighimpedancestateon

the falling edge of the clock (SK). Placing the DO pin into

the high impedance state is recommended in applica-

tions where the DI pin and the DO pin are to be tied

together to form a common DI/O pin.

The 93CXXXX is designed with a V_CClock out data

protection feature to provide a high degree of data

integrity.

TheV_CCsenseprovideswriteprotectionwhenV_CCfalls

below the reset threshold value. The V_CClock out

inhibits writes to the serial EEPROM whenever V_CC

falls below (power down) or until V_CCreaches the reset

threshold (power up).

Reset Threshold Voltage

From the factory the 93CXXXX is offered in five differ-

ent variations of reset threshold voltages. They are

4.50-4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and

2.55-2.70V. To provide added flexibility to design

engineers using this product, the 93CXXXX is de-

signed with an additional feature of programming the

reset threshold voltage. This allows the user to change

The format for all instructions sent to the device is a

logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit

(93C46XX)//7-bit (93C57XX)/ 8-bit (93C56XX or

93C66XX)/10-bit (93C86XX) (an additional bit when

organized X8) and for write operations a 16-bit data field

(8-bit for X8 organizations).

Stock No. 21084-01 2/98

9-90

Advanced Information

Read

CAT93CXXXX

Write

After receiving a WRITE command, address and the

data, the CS (Chip Select) pin must be deselected for a

minimum of t_CSMIN. The falling edge of CS will start the

self clocking clear and data store cycle of the memory

location specified in the instruction. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93CXXXX can be determined by selecting the de-

vice and polling the DO pin. Since this device features

Auto-Clear before write, it is NOT necessary to erase a

memory location before it is written into.

Upon receiving a READ command and an address

(clockedintotheDIpin),theDOpinoftheCAT93CXXXX

will come out of the high impedance state and, after

sending an initial dummy zero bit, will begin shifting out

the data addressed (MSB first). The output data bits will

toggle on the rising edge of the SK clock and are stable

after the specified time delay (t_PD0or t_PD1

)

For the 93CXXXX, after the initial data word has been

shifted out and CS remains asserted with the SK clock

continuing to toggle, the device will automatically incre-

menttothenextaddressandshiftoutthenextdataword

in a sequential READ mode. As long as CS is continu-

ously asserted and SK continues to toggle, the device

will keep incrementing to the next address automatically

until it reaches to the end of the address space, then

loops back to address 0. In the sequential READ mode,

only the initial data word is preceeded by a dummy zero

bit. All subsequent data words will follow without a

dummy zero bit.

Page Write

The 93CXXXX writes up to 16 bytes (8 words for x16

format) of data in a single write cycle, using the page

write operation. The page write operation is initiated in

the same manner as the byte (word for x16 format) write

operation. However, instead of terminating after the

initial byte (word for x16 format) is transmitted, the host

Figure 2. Sychronous Data Timing

SKLOW

SKHI

CSH

DIS

DIH

VALID

CSS

DIS

PD0, PD1

CSMIN

DATA VALID

Figure 3. Read Instruction Timing

Don't Care

N–1

HIGH-Z

Dummy 0

Address + 1 Address + 2 Address + n

15 . . .

7 . . .

Stock No. 21084-01 2/98

9-91

Advanced Information

CAT93CXXXX

Erase

can then continue to clock in 8-bit (16-bit for x16 format)

data to be written to the next higher address. Internally,

the address pointer is incremented after each group of

eight clocks (16 clocks for x16 format). If the host

transmits more than 16 bytes (8 words for x16 format)

the address counter ‘wraps around’ and previously

transmitted data will be overwritten.

Upon receiving an ERASE command and address, the

CS (Chip Select) pin must be deasserted for a minimum

oft_CSMIN.ThefallingedgeofCSwillstarttheselfclocking

clear cycle of the selected memory location. The clock-

ing of the SK pin is not necessary after the device has

enteredtheselfclockingmode.Theready/busystatusof

the CAT93CXXXX can be determined by selecting the

deviceandpollingtheDOpin. Oncecleared, thecontent

of a cleared location returns to a logical “1” state.

After receiving a WRITE command, address and the

data, the CS (Chip Select) pin must be deselected for a

minimum of t_CSMIN. The falling edge of CS will start the

self clocking clear and data store cycle of the memory

location specified in the instruction. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93CXXXX can be determined by selecting the de-

vice and polling the DO pin. Since this device features

Auto-Clear before write, it is NOT necessary to erase a

memory location before it is written into.

Figure 4. Write Instruction Timing

STANDBY

STATUS

VERIFY

N-1

BUSY

HIGH-Z

READY

HIGH-Z

Figure 5. Erase Instruction Timing

STANDBY

STATUS VERIFY

N-1

HIGH-Z

BUSY

READY

HIGH-Z

Stock No. 21084-01 2/98

9-92

Advanced Information

CAT93CXXXX

Erase/Write Enable and Disable

entered the self clocking mode. The ready/busy status

of the CAT93CXXXX can be determined by selecting

the device and polling the DO pin. Once cleared, the

contents of all memory bits return to a logical “1” state.

The CAT93CXXXX powers up in the write disable state.

Any writing after power-up or after an EWDS (write

disable) instruction must first be preceded by the EWEN

(write enable) instruction. Once the write instruction is

enabled, it will remain enabled until power to the device

is removed, or the EWDS instruction is sent. The EWDS

instruction can be used to disable all CAT93CXXXX

write and clear instructions, and will prevent any acci-

dental writing or clearing of the device. Data can be read

normally from the device regardless of the write enable/

disable status.

Write All

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

t_CSMIN. The falling edge of CS will start the self clocking

data write to all memory locations in the device. The

clocking of the SK pin is not necessary after the device

hasenteredtheselfclockingmode.Theready/busystatus

oftheCAT93CXXXXcanbedeterminedbyselectingthe

device and polling the DO pin. It is not necessary for all

memory locations to be cleared before the WRAL com-

mand is executed.

Erase All

Upon receiving an ERAL command, the CS (Chip Se-

lect) pin must be deselected for a minimum of t_CSMIN

The falling edge of CS will start the self clocking clear

cycle of all memory locations in the device. The clocking

of the SK pin is not necessary after the device has

Figure 6. EWEN/EWDS Instruction Timing

STANDBY

* ENABLE=11

DISABLE=00

Figure 7. ERAL Instruction Timing

STATUS VERIFY

STANDBY

HIGH-Z

BUSY

READY

HIGH-Z

Stock No. 21084-01 2/98

9-93

Advanced Information

CAT93CXXXX

Figure 8. WRAL Instruction Timing

STATUS VERIFY

STANDBY

BUSY

READY

HIGH-Z

Ordering Information

Prefix

Device #

Suffix

-25

TE13

CAT

93C46

Optional

Company ID

Product

Temperature Range

Tape & Reel

Number

Variation

Blank = Commercial (0˚ - 70˚C)

I = Industrial (-40˚ - 85˚C)

TE13: 2000/Reel

93C46: 1K

93C56: 2K

93C57: 2K

93C66: 4K

11 RESET on Pin 7, No WDT

12 RESET on Pin 7, No WDT

13 RESET on Pin 7, WDT on CS

14 RESET on Pin 7, WDT on CS

21 x16 Mode, RESET on Pin 7

22 x16 Mode, RESET on Pin 7

23 x8 Mode, RESET on Pin 7

24 x8 Mode, RESET on Pin 7

31 x16 Mode, No WDT

A = Automotive (-40˚ - 105˚C)*

93C86: 16K

Package

P = PDIP

ResetThreshold

Voltage

S = SOIC (JEDEC)

J = SOIC (JEDEC)

K = SOIC (EIAJ)

U = TSSOP

45: 4.5-4.75V

42: 4.25-4.5V

30: 3.0-3.15V

28: 2.85-3.0V

25: 2.55-2.7V

32 x8 Mode, No WDT

33 x16 Mode, WDT on CS

34 x8 Mode, WDT on CS

* -40˚ to +125˚C is available upon request

Note:

(1) The device used in the above example is a 93C4611SI-25TE13 (1K EEPROM, Reset on pin 7 & No WDT, SOIC, Industrial Temperature,

2.55V to 2.7 V Reset threshold voltage, Tape & Reel).

Stock No. 21084-01 2/98

9-94

CAT93C4621 [CATALYST]

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