CAT93C46WE-1.8REVL [CATALYST]
EEPROM, 64X16, Serial, CMOS, PDSO8, GREEN, SOIC-8;
| 型号： | CAT93C46WE-1.8REVL |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 64X16, Serial, CMOS, PDSO8, GREEN, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：583K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT93C46 (Die Rev. L)
1K-Bit Microwire Serial EEPROM
TM
FEATURES
ꢀ High speed operation: 1MHz
ꢀ Power-up inadvertant write protection
ꢀ 1,000,000 Program/erase cycles
ꢀ 100 year data retention
ꢀ Low power CMOS technology
ꢀ 1.8 to 6.0 volt operation
ꢀ Selectable x8 or x16 memory organization
ꢀ Self-timed write cycle with auto-clear
ꢀ Hardware and software write protection
ꢀ Commercial, industrial and automotive
temperature ranges
ꢀ “Green” package option available
DESCRIPTION
Catalyst’s advanced CMOS EEPROM floating gate
technology. Thedeviceisdesignedtoendure1,000,000
program/erase cycles and has a data retention of 100
years. The device is available in 8-pin DIP, 8-pin SOIC,
8-pin TSSOP and 8-pad TDFN packages.
The CAT93C46 is a 1K-bit Serial EEPROM memory
device which is configured as either registers of 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the
DI (or DO) pin. The CAT93C46 is manufactured using
PIN CONFIGURATION
FUNCTIONAL SYMBOL
VCC
SOIC Package (J,W)
DIP Package (P, L)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
ORG
GND
DO
NC
CC
ORG
CS
DI
NC
V
CC
CS
ORG
GND
DO
DO
SK
DI
SK
NC
SOIC Package (S,V)
SOIC Package (K,X)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
CS
SK
DI
V
CC
NC
ORG
GND
CC
GND
NC
ORG
GND
PIN FUNCTIONS
DO
DO
Pin Name
Function
Chip Select
Clock Input
CS
TSSOP Package (U,Y)
SK
1
2
3
4
8
7
6
5
CS
SK
DI
V
CC
DI
Serial Data Input
Serial Data Output
+1.8 to 6.0V Power Supply
Ground
NC
DO
VCC
GND
ORG
NC
ORG
GND
DO
TDFN Package (RD4, ZD4)
Memory Organization
No Connection
V
CC
NC
1
2
3
4
8
7
6
5
CS
SK
DI
Note: When the ORG pin is connected to VCC, the x16 organiza-
tion is selected. When it is connected to ground, the x8 pin is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
ORG
GND
DO
Bottom View
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1086, Rev. L
CAT93C46
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on any Pin with
Respect to Ground(1) ............. -2.0V to +VCC +2.0V
V
CC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC1
Power Supply Current
(Write)
fSK = 1MHz
VCC = 5.0V
3
mA
ICC2
ISB1
ISB2
Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
500
10
µA
µA
µA
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
0
10
ILI
Input Leakage Current
VIN = 0V to VCC
1
1
µA
µA
ILO
Output Leakage Current
(Including ORG pin)
VOUT = 0V to VCC
,
CS = 0V
VIL1
VIH1
VIL2
VIH2
VOL1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
4.5V ≤ VCC < 5.5V
4.5V ≤ VCC < 5.5V
1.8V ≤ VCC < 4.5V
1.8V ≤ VCC < 4.5V
-0.1
0.8
VCC + 1
VCC x 0.2
VCC+1
0.4
V
V
V
V
V
2
0
VCC x 0.7
4.5V ≤ VCC < 5.5V
IOL = 2.1mA
VOH1
VOL2
Output High Voltage
Output Low Voltage
4.5V ≤ VCC < 5.5V
IOH = -400µA
2.4
V
V
1.8V ≤ VCC < 4.5V
0.2
IOL = 1mA
VOH2
Output High Voltage
1.8V ≤ VCC < 4.5V
IOH = -100µA
VCC - 0.2
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1086, Rev. L
2
CAT93C46
PIN CAPACITANCE
Symbol
Test
Conditions
VOUT=0V
VIN=0V
Min
Typ
Max
Units
pF
(1)
COUT
Output Capacitance (DO)
5
5
(1)
CIN
Input Capacitance (CS, SK, DI, ORG)
pF
INSTRUCTION SET
Address
Data
Instruction Start Bit Opcode
x8
x16
x8
x16
Comments
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6-A0
A6-A0
A5-A0
A5-A0
A5-A0
Read Address AN– A0
Clear Address AN– A0
A6-A0
D7-D0
D15-D0 Write Address AN– A0
Write Enable
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
Write Disable
Clear All Addresses
WRAL
D7-D0
D15-D0 Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC
=
VCC
=
VCC
=
1.8V-6V
2.5V-6V
4.5V-5.5V
Test
Symbol Parameter
Conditions
Min Max Min
Max Min
Max
Units
ns
tCSS
tCSH
tDIS
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
200
0
100
0
50
0
ns
400
400
200
200
100
100
ns
tDIH
tPD1
tPD0
ns
Output Delay to 1
Output Delay to 0
1
1
0.5
0.5
200
10
0.25
0.25
100
10
µs
CL = 100pF
(3)
µs
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
10
ns
tEW
ms
µs
tCSMIN
tSKHI
tSKLOW
tSV
1
1
1
0.5
0.5
0.5
0.25
0.25
0.25
µs
µs
1
0.5
0.25
µs
SKMAX
DC
250
DC
500
DC
1000
kHz
Doc. No. 1086, Rev. L
3
CAT93C46
(1)(2)
POWER-UP TIMING
Symbol
tPUR
Parameter
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
NOTE:
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
PUR
PUW
CC
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
DEVICE OPERATION
The CAT93C46 is a 1024-bit nonvolatile memory in-
tended for use with industry standard microprocessors.
The CAT93C46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructionscontrolthereading,writinganderaseopera-
tions of the device. When organized as X8, seven 10-bit
instructions control the reading, writing and erase
operations of the device. The CAT93C46 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
The format for all instructions sent to the device is a
logical"1"startbit, a2-bit(or4-bit)opcode, 6-bitaddress
(an additional bit when organized X8) and for write
operationsa16-bitdatafield(8-bitforX8organizations).
Read
Upon receiving a READ command and an address
(clockedintotheDIpin),theDOpinoftheCAT93C46will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed(MSBfirst). Theoutputdatabitswilltoggleon
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DIpin. TheDOpinwillenterthehighimpedancestateon
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
Doc. No. 1086, Rev. L
4
CAT93C46
Figure 1. Sychronous Data Timing
t
t
t
SKLOW
SKHI
CSH
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
DIS
PD0, PD1
CSMIN
DO
DATA VALID
Figure 2. Read Instruction Timing
SK
t
CSMIN
CS
STANDBY
A
A
A
0
N
N—1
DI
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
D
D
D
0
N
N—1
1
Figure 3. Write Instruction Timing
SK
t
CSMIN
STANDBY
STATUS
VERIFY
CS
A
A
A
0
D
D
N
N-1
N
0
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
Doc. No. 1086, Rev. L
5
CAT93C46
Erase All
Erase
UponreceivinganERALcommand,theCS(ChipSelect)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking
clearcycleoftheselectedmemorylocation.Theclocking
of the SK pin is not necessary after the device has
enteredtheselfclockingmode.Theready/busystatusof
the CAT93C46 can be determined by selecting the
deviceandpollingtheDOpin. Oncecleared, thecontent
of a cleared location returns to a logical “1” state.
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C46 can be determined by selecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
TheCAT93C46powersupinthewritedisablestate. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable)instruction.Oncethewriteinstructionisenabled,
itwillremainenableduntilpowertothedeviceisremoved,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C46 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Figure 4. Erase Instruction Timing
SK
STANDBY
STATUS VERIFY
CS
t
CS
A
A
0
A
N
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
Doc. No. 1086, Rev. L
6
CAT93C46
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CSMIN
D
D
DI
0
0
1
0
1
N
0
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1086, Rev. L
7
CAT93C46
ORDERING INFORMATION
Prefix
Device #
Suffix
S
-1.8
Rev L(2)
CAT
93C46
TE13
I
Optional
Company ID
Product
Number
Temperature Range
Tape & Reel
Blank = Commercial (0°C - 70°C)
I = Industrial (-40°C - 85°C)
A = Automotive (-40°C - 105°C)
E = Extended (-40°C to + 125°C)
Die Revision
Operating Voltage
Package
Blank (V =2.5 to 6.0V)
cc
P = PDIP
1.8 (V =1.8 to 6.0V)
S = SOIC (JEDEC)
J = SOIC (JEDEC)
K = SOIC (EIAJ)
U= TSSOP
cc
RD4 = TDFN (3x3mm)
ZD4 = TDFN (3x3mm, Lead free, Halogen free)
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
W= SOIC, JEDEC (Lead free, Halogen free)
X = SOIC, EIAJ (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWL.) For additional
information, please contact your Catalyst sales office.
Doc. No. 1086, Rev. L
8
REVISION HISTORY
Date
Revision Comments
05/14/04
L
New Data Sheet Created From CAT93C46/56/57/66/86. Parts
CAT93C56, CAT93C56, CAT93C57, CAT93C66, CAT93C76 and
CAT93C86 have been separtated into single data sheets
Add Die Revision ID Letter
Update Features
Update Description
Update Pin Condition
Add Functional Diagram
Update Pin Function
Update D.C. Operating Characteristics
Update Pin Capacitance
Update Instruction Set
Update Device Operation
Update Ordering Information
Update Revision History
Update Rev Number
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1086
Revison:
L
Issue date:
5/14/04
www.catalyst-semiconductor.com
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