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CAT93C56SI-TE13 [CATALYST]

1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM; 1K / 2K / 2K / 4K / 16K位Microwire串行E2PROM
CAT93C56SI-TE13
型号： CAT93C56SI-TE13
厂家： CATALYST SEMICONDUCTOR    CATALYST SEMICONDUCTOR
描述：

1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
1K / 2K / 2K / 4K / 16K位Microwire串行E2PROM

存储 内存集成电路 光电二极管 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟
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中文：  中文翻译
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CAT93C46/56/57/66/86  
1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM  
FEATURES  
■ High Speed Operation:  
■ Power-Up Inadvertant Write Protection  
■ 1,000,000 Program/Erase Cycles  
■ 100 Year Data Retention  
– 93C46/56/57/66: 1MHz  
– 93C86: 3MHz  
■ Low Power CMOS Technology  
■ Commercial, Industrial and Automotive  
■ 1.8 to 6.0 Volt Operation  
Temperature Ranges  
■ Selectable x8 or x16 Memory Organization  
■ Self-Timed Write Cycle with Auto-Clear  
■ Hardware and Software Write Protection  
■ Sequential Read (except 93C46)  
■ Program Enable (PE) Pin (93C86 only)  
DESCRIPTION  
CMOS E2PROM floating gate technology. The devices  
aredesignedtoendure1,000,000program/erasecycles  
and have a data retention of 100 years. The devices are  
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP  
packages.  
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit  
Serial E2PROM memory devices which are configured  
as either registers of 16 bits (ORG pin at VCC) or 8 bits  
(ORGpinatGND). Eachregistercanbewritten(orread)  
serially by using the DI (or DO) pin. The CAT93C46/56/  
57/66/86 are manufactured using Catalyst’s advanced  
PIN CONFIGURATION  
TSSOP Package (U)  
SOIC Package (J)  
SOIC Package (S)  
DIP Package (P)  
SOIC Package (K)  
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
CC  
NC (PE*)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS  
SK  
DI  
V
ORG  
GND  
DO  
CS  
SK  
DI  
V
CS  
SK  
DI  
V
CC  
NC (PE*)  
CC  
CC  
NC (PE*)  
V
NC (PE*)  
ORG  
NC (PE*)  
ORG  
CC  
ORG  
ORG  
CS  
DO  
DO  
GND  
SK  
DI  
DO  
GND  
DO  
GND  
GND  
*Only For 93C86  
93C46/56/57/66/86  
F01  
PIN FUNCTIONS  
BLOCK DIAGRAM  
Pin Name  
CS  
Function  
V
GND  
CC  
Chip Select  
SK  
Clock Input  
ADDRESS  
DECODER  
DI  
Serial Data Input  
Serial Data Output  
MEMORY ARRAY  
ORGANIZATION  
ORG  
DO  
VCC  
GND  
ORG  
NC  
+1.8 to 6.0V Power Supply  
Ground  
DATA  
REGISTER  
OUTPUT  
BUFFER  
Memory Organization  
No Connection  
DI  
MODE DECODE  
LOGIC  
CS  
PE*  
PE*  
Program Enable  
Note: When the ORG pin is connected to VCC, the X16 organiza  
tion is selected. When it is connected to ground, the X8 pin  
is selected. If the ORG pin is left unconnected, then an  
internal pullup device will select the X16 organization.  
CLOCK  
GENERATOR  
DO  
SK  
93C46/56/57/66/86 F02  
© 1998 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 25056-00 2/98 M-1  
1
93C46/56/57/66/86  
ABSOLUTE MAXIMUM RATINGS*  
*COMMENT  
Temperature Under Bias ................. –55°C to +125°C  
Storage Temperature....................... –65°C to +150°C  
Stresses above those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device.  
These are stress ratings only, and functional operation of  
the device at these or any other conditions outside of those  
listed in the operational sections of this specification is not  
implied. Exposure to any absolute maximum rating for  
extended periods may affect device performance and  
reliability.  
Voltage on any Pin with  
Respect to Ground(1) ............ –2.0V to +VCC +2.0V  
V
CC with Respect to Ground ............... –2.0V to +7.0V  
Package Power Dissipation  
Capability (Ta = 25°C)................................... 1.0W  
Lead Soldering Temperature (10 secs) ............ 300°C  
Output Short Circuit Current(2) ........................ 100 mA  
RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Min.  
1,000,000  
100  
Max.  
Units  
Cycles/Byte  
Years  
Reference Test Method  
MIL-STD-883, Test Method 1033  
MIL-STD-883, Test Method 1008  
MIL-STD-883, Test Method 3015  
JEDEC Standard 17  
(3)  
NEND  
(3)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-Up  
(3)  
VZAP  
2000  
Volts  
(3)(4)  
ILTH  
100  
mA  
D.C. OPERATING CHARACTERISTICS  
= +1.8V to +6.0V, unless otherwise specified.  
V
CC  
Limits  
Typ.  
Symbol  
Parameter  
Min.  
Max.  
Units  
Test Conditions  
ICC1  
Power Supply Current  
(Operating Write)  
3
mA  
fSK = 1MHz  
VCC = 5.0V  
ICC2  
ISB1  
Power Supply Current  
(Operating Read)  
500  
10  
0
µA  
µA  
µA  
fSK = 1MHz  
VCC = 5.0V  
Power Supply Current  
(Standby) (x8 Mode)  
CS = 0V  
ORG=GND  
(5)  
ISB2  
Power Supply Current  
(Standby) (x16Mode)  
CS=0V  
ORG=Float or VCC  
ILI  
Input Leakage Current  
1
1
µA  
µA  
VIN = 0V to VCC  
ILO  
Output Leakage Current  
(Including ORG pin)  
VOUT = 0V to VCC  
CS = 0V  
,
VIL1  
Input Low Voltage  
Input High Voltage  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
-0.1  
0.8  
VCC+1  
VCCX0.2  
VCC+1  
0.4  
4.5V≤VCC<5.5V  
1.8V≤VCC<2.7V  
4.5V≤VCC<5.5V  
V
V
V
V
V
V
VIH1  
VIL2  
2
0
VIH2  
VOL1  
VOH1  
VCCX0.7  
2.4  
IOL = 2.1mA  
IOH = -400µA  
VOL2  
VOH2  
Output Low Voltage  
Output High Voltage  
0.2  
1.8V≤VCC<2.7V  
VCC-0.2  
IOL = 1mA  
IOH = -100µA  
V
Note:  
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) This parameter is tested initially and after a design or process change that affects the parameter.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.  
CC  
(5) Standby Current (ISB )=0µA (<900nA) for 93C46/56/57/66, (ISB )=2µA for 93C86.  
2
2
Doc. No. 25056-00 2/98 M-1  
2
93C46/56/57/66/86  
PIN CAPACITANCE  
Symbol  
Test  
Max.  
Units  
pF  
Conditions  
(3)  
COUT  
OUTPUT CAPACITANCE (DO)  
5
5
VOUT=OV  
VIN=OV  
(3)  
CIN  
INPUT CAPACITANCE (CS, SK, DI, ORG)  
pF  
INSTRUCTION SET  
(2)  
Instruction Device Start Opcode  
Address  
Data  
x8 x16  
Comments  
PE  
Type  
Bit  
x8  
x16  
READ  
ERASE  
WRITE  
EWEN  
EWDS  
ERAL  
93C46  
93C56(1)  
93C66  
93C57  
93C86  
1
1
1
1
1
10  
10  
10  
10  
10  
A6-A0  
A8-A0  
A8-A0  
A7-A0  
A10-A0  
A5-A0  
A7-A0  
A7-A0  
A6-A0  
A9-A0  
Read Address AN–A0  
X
93C46  
93C56(1)  
93C66  
93C57  
93C86  
1
1
1
1
1
11  
11  
11  
11  
11  
A6-A0  
A8-A0  
A8-A0  
A7-A0  
A10-A0  
A5-A0  
A7-A0  
A7-A0  
A6-A0  
A9-A0  
Clear Address AN–A0  
I
93C46  
93C56(1)  
93C66  
93C57  
93C86  
1
1
1
1
1
01  
01  
01  
01  
01  
A6-A0  
A8-A0  
A8-A0  
A7-A0  
A10-A0  
A5-A0  
A7-A0  
A7-A0  
A6-A0  
A9-A0  
D7-D0 D15-D0 Write Address AN–A0  
D7-D0 D15-D0  
D7-D0 D15-D0  
D7-D0 D15-D0  
D7-D0 D15-D0  
I
X
X
I
93C46  
93C56  
93C66  
93C57  
93C86  
1
1
1
1
1
00  
00  
00  
00  
00  
11XXXXX  
11XXXXXXX  
11XXXXXXX  
11XXXXXX  
11XXXX  
11XXXXXX  
11XXXXXX  
11XXXXX  
Write Enable  
Write Disable  
11XXXXXXXXX 11XXXXXXXX  
93C46  
93C56  
93C66  
93C57  
93C86  
1
1
1
1
1
00  
00  
00  
00  
00  
00XXXXX  
00XXXXXXX  
00XXXXXXX  
00XXXXXX  
00XXXX  
00XXXXXX  
00XXXXXX  
00XXXXX  
00XXXXXXXXX 00XXXXXXXX  
93C46  
93C56  
93C66  
93C57  
93C86  
1
1
1
1
1
00  
00  
00  
00  
00  
10XXXXX  
10XXXXXXX  
10XXXXXXX  
10XXXXXX  
10XXXX  
10XXXXXX  
10XXXXXX  
10XXXXX  
Clear All Addresses  
10XXXXXXXXX 10XXXXXXXX  
WRAL  
93C46  
93C56  
93C66  
93C57  
93C86  
1
1
1
1
1
00  
00  
00  
00  
00  
01XXXXX  
01XXXXXXX  
01XXXXXXX  
01XXXXXX  
01XXXX  
01XXXXXX  
01XXXXXX  
01XXXXX  
D7-D0 D15-D0  
D7-D0 D15-D0  
D7-D0 D15-D0  
D7-D0 D15-D0  
Write All Addresses  
01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0  
I
Note:  
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE  
and ERASE commands.  
(2) Applicable only to 93C86  
(3) This parameter is tested initially and after a design or process change that affects the parameter.  
Doc. No. 25056-00 2/98 M-1  
3
93C46/56/57/66/86  
A.C. CHARACTERISTICS (93C46/56/57/66)  
Limits  
VCC  
2.5V-6V  
VCC  
1.8V-6V*  
=
=
VCC  
4.5V-5.5V  
=
Test  
SYMBOL PARAMETER  
Min.  
200  
0
Max.  
Min.  
Max.  
Min.  
50  
Max. UNITS Conditions  
ns  
tCSS  
tCSH  
tDIS  
CS Setup Time  
100  
0
CS Hold Time  
0
ns  
ns  
ns  
µs  
µs  
ns  
ms  
µs  
µs  
µs  
µs  
DI Setup Time  
400  
400  
200  
200  
100  
100  
tDIH  
tPD1  
tPD0  
DI Hold Time  
Output Delay to 1  
1
1
0.5  
0.5  
200  
10  
0.25  
0.25  
100  
10  
Output Delay to 0  
CL = 100pF  
(1)  
tHZ  
Output Delay to High-Z  
Program/Erase Pulse Width  
Minimum CS Low Time  
Minimum SK High Time  
Minimum SK Low Time  
Output Delay to Status Valid  
Maximum Clock Frequency  
400  
10  
tEW  
tCSMIN  
tSKHI  
tSKLOW  
tSV  
1
1
1
0.5  
0.5  
0.5  
0.25  
0.25  
0.25  
1
0.5  
0.25  
SKMAX  
DC  
250  
DC  
500  
DC  
1000 KHZ  
* Preliminary data for 93C56/57/66  
A.C. CHARACTERISTICS (93C86)  
Limits  
VCC  
2.5V-6V  
VCC  
1.8V-6V*  
=
=
VCC  
4.5V-5.5V  
=
Test  
SYMBOL PARAMETER  
Min.  
200  
0
Max.  
Min.  
Max.  
Min.  
50  
0
Max. UNITS Conditions  
ns  
tCSS  
tCSH  
tDIS  
CS Setup Time  
150  
0
CS Hold Time  
ns  
ns  
ns  
µs  
µs  
ns  
ms  
µs  
µs  
µs  
µs  
DI Setup Time  
400  
400  
250  
250  
50  
50  
tDIH  
tPD1  
tPD0  
DI Hold Time  
Output Delay to 1  
1
1
0.5  
0.5  
200  
5
0.1  
0.1  
100  
5
Output Delay to 0  
CL = 100pF  
(1)  
tHZ  
Output Delay to High-Z  
Program/Erase Pulse Width  
Minimum CS Low Time  
Minimum SK High Time  
Minimum SK Low Time  
Output Delay to Status Valid  
Maximum Clock Frequency  
400  
5
tEW  
tCSMIN  
tSKHI  
tSKLOW  
tSV  
1
1
1
0.5  
0.5  
0.5  
0.1  
0.1  
0.1  
1
0.5  
0.1  
SKMAX  
DC  
250  
DC  
1000  
DC  
3000 KHZ  
NOTE:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
Doc. No. 25056-00 2/98 M-1  
4
93C46/56/57/66/86  
DEVICE OPERATION  
the DI pin on the rising edge of the clock (SK). The DO  
pin is normally in a high impedance state except when  
reading data from the device, or when checking the  
ready/busy status after a write operation.  
The CAT93C46/56(57)66/86 is a 1024/2048/4096/  
16,384-bit nonvolatile memory intended for use with  
industrystandardmicroprocessors. TheCAT93C46/56/  
57/66/86 can be organized as either registers of 16 bits  
or 8 bits. When organized as X16, seven 9-bit instruc-  
tions for 93C46; seven 10-bit instructions for 93C57;  
seven 11-bit instructions for 93C56 and 93C66; seven  
13-bitinstructionsfor93C86;controlthereading, writing  
and erase operations of the device. When organized as  
X8, seven 10-bit instructions for 93C46; seven 11-bit  
instructions for 93C57; seven 12-bit instructions for  
93C56 and 93C66: seven 14-bit instructions for 93C86;  
control the reading, writing and erase operations of the  
device.TheCAT93C46/56/57/66/86operatesonasingle  
power supply and will generate on chip, the high voltage  
required during any write operation.  
The ready/busy status can be determined after the start  
ofawriteoperationbyselectingthedevice(CShigh)and  
polling the DO pin; DO low indicates that the write  
operation is not completed, while DO high indicates that  
the device is ready for the next instruction. If necessary,  
the DO pin may be placed back into a high impedance  
state during chip select by shifting a dummy “1” into the  
DIpin. TheDOpinwillenterthehighimpedancestateon  
the falling edge of the clock (SK). Placing the DO pin into  
the high impedance state is recommended in applica-  
tions where the DI pin and the DO pin are to be tied  
together to form a common DI/O pin.  
Instructions, addresses, and write data are clocked into  
Figure 1. Sychronous Data Timing  
t
t
t
SKLOW  
SKHI  
CSH  
SK  
t
t
DIS  
DIH  
VALID  
VALID  
DI  
t
CSS  
CS  
t
t
t
t
DIS  
PD0, PD1  
CSMIN  
DO  
DATA VALID  
93C46/56/57/66/86 F03  
Figure 2a. Read Instruction Timing (93C46)  
SK  
t
CS  
CS  
STANDBY  
A
A
A
0
N
N–1  
DI  
1
1
0
t
HZ  
t
HIGH-Z  
HIGH-Z  
PD0  
DO  
0
D
D
D
D
0
N
N–1  
1
93C46/56/57/66/86 F04  
Doc. No. 25056-00 2/98 M-1  
5
93C46/56/57/66/86  
The format for all instructions sent to the device is a  
logical"1"startbit,a2-bit(or4-bit)opcode,6-bit(93C46)/  
/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)  
(an additional bit when organized X8) and for write  
operationsa16-bitdatafield(8-bitforX8organizations).  
increment to the next address and shift out the next data  
word in a sequential READ mode. As long as CS is  
continuously asserted and SK continues to toggle, the  
device will keep incrementing to the next address auto-  
maticallyuntilitreachestotheendoftheaddressspace,  
then loops back to address 0. In the sequential READ  
mode, only the initial data word is preceeded by a  
dummy zero bit. All subsequent data words will follow  
without a dummy zero bit.  
Note: This note is applicable only to 93C86. The Write,  
Erase, Write all and Erase all instructions require PE=1.  
If PE is left floating, 93C86 is in Program Enabled mode.  
ForWriteEnableandWriteDisableinstructionPE=don’t  
care.  
Write  
Read  
After receiving a WRITE command, address and the  
data, the CS (Chip Select) pin must be deselected for a  
minimum of tCSMIN. The falling edge of CS will start the  
self clocking clear and data store cycle of the memory  
location specified in the instruction. The clocking of the  
SK pin is not necessary after the device has entered the  
self clocking mode. The ready/busy status of the  
CAT93C46/56/57/66/86canbedeterminedbyselecting  
the device and polling the DO pin. Since this device  
features Auto-Clear before write, it is NOT necessary to  
erase a memory location before it is written into.  
Upon receiving a READ command and an address  
(clocked into the DI pin), the DO pin of the CAT93C46/  
56/57/66/86 will come out of the high impedance state  
and, after sending an initial dummy zero bit, will begin  
shifting out the data addressed (MSB first). The output  
databitswilltoggleontherisingedgeoftheSKclockand  
are stable after the specified time delay (tPD0 or tPD1  
)
For the 93C56/57/66/86, after the initial data word has  
been shifted out and CS remains asserted with the SK  
clock continuing to toggle, the device will automatically  
Figure 2b. Read Instruction Timing (93C56/57/66/86)  
SK  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS  
DI  
Don't Care  
A
A
A
0
N
N–1  
1
1
0
HIGH-Z  
DO  
Dummy 0  
D
D
Address + 1 Address + 2 Address + n  
15 . . .  
0
or  
D
D
D
D
D
15 . . .  
0
15 . . .  
or  
D
0
15 . . .  
D
D
0
or  
or  
7 . . .  
D
D
D
D
7 . . .  
7 . . .  
0
7 . . .  
0
Figure 3. Write Instruction Timing  
SK  
t
CS  
STANDBY  
STATUS  
VERIFY  
CS  
A
A
A
0
D
N
D
0
N
N-1  
DI  
1
0
1
t
t
SV  
HZ  
BUSY  
HIGH-Z  
DO  
READY  
HIGH-Z  
t
EW  
93C46/56/57/66/86 F05  
Doc. No. 25056-00 2/98 M-1  
6
93C46/56/57/66/86  
Erase All  
Upon receiving an ERAL command, the CS (Chip Se-  
Erase  
Upon receiving an ERASE command and address, the  
CS (Chip Select) pin must be deasserted for a minimum  
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking  
clear cycle of the selected memory location. The clock-  
ing of the SK pin is not necessary after the device has  
enteredtheselfclockingmode.Theready/busystatusof  
the CAT93C46/56/57/66/86 can be determined by se-  
lecting the device and polling the DO pin. Once cleared,  
the content of a cleared location returns to a logical “1”  
state.  
lect) pin must be deselected for a minimum of tCSMIN  
.
The falling edge of CS will start the self clocking clear  
cycle of all memory locations in the device. The clocking  
of the SK pin is not necessary after the device has  
enteredtheselfclockingmode.Theready/busystatusof  
the CAT93C46/56/57/66/86 can be determined by se-  
lecting the device and polling the DO pin. Once cleared,  
the contents of all memory bits return to a logical “1”  
state.  
Write All  
Erase/Write Enable and Disable  
Upon receiving a WRAL command and data, the CS  
(Chip Select) pin must be deselected for a minimum of  
The CAT93C46/56/57/66/86 powers up in the write  
disable state. Any writing after power-up or after an  
EWDS (write disable) instruction must first be preceded  
by the EWEN (write enable) instruction. Once the write  
instruction is enabled, it will remain enabled until power  
to the device is removed, or the EWDS instruction is  
sent. The EWDS instruction can be used to disable all  
CAT93C46/56/57/66/86 write and clear instructions,  
and will prevent any accidental writing or clearing of the  
device. Data can be read normally from the device  
regardless of the write enable/disable status.  
tCSMIN. The falling edge of CS will start the self clocking  
data write to all memory locations in the device. The  
clocking of the SK pin is not necessary after the device  
has entered the self clocking mode. The ready/busy  
statusoftheCAT93C46/56/57/66/86canbedetermined  
by selecting the device and polling the DO pin. It is not  
necessary for all memory locations to be cleared before  
the WRAL command is executed.  
Figure 4. Erase Instruction Timing  
SK  
CS  
STANDBY  
STATUS VERIFY  
t
CS  
A
N
A
0
A
N-1  
DI  
1
1
1
t
t
SV  
HZ  
HIGH-Z  
DO  
BUSY  
EW  
READY  
HIGH-Z  
t
93C46/56/57/66/86 F06  
Doc. No. 25056-00 2/98 M-1  
7
93C46/56/57/66/86  
Figure 5. EWEN/EWDS Instruction Timing  
SK  
CS  
STANDBY  
DI  
0
1
0
*
* ENABLE=11  
DISABLE=00  
93C46/56/57/66/86 F07  
Figure 6. ERAL Instruction Timing  
SK  
CS  
STATUS VERIFY  
STANDBY  
t
CS  
DI  
1
0
0
1
0
t
t
SV  
HZ  
HIGH-Z  
HIGH-Z  
DO  
BUSY  
READY  
t
EW  
93C46/56/57/66/86 F08  
Figure 7. WRAL Instruction Timing  
SK  
CS  
STATUS VERIFY  
STANDBY  
t
CS  
D
D
DI  
1
0
0
0
1
N
0
t
t
SV  
HZ  
DO  
BUSY  
READY  
HIGH-Z  
t
EW  
93C46/56/57/66/86 F09  
Doc. No. 25056-00 2/98 M-1  
8
93C46/56/57/66/86  
ORDERING INFORMATION  
Prefix  
Device #  
Suffix  
S
-1.8  
CAT  
93C46  
TE13  
I
Optional  
Company ID  
Product  
Temperature Range  
Tape & Reel  
TE13: 2000/Reel  
Number  
Blank = Commercial (0˚ - 70˚C)  
I = Industrial (-40˚ - 85˚C)  
A = Automotive (-40˚ - 105˚C)*  
93C46: 1K  
93C56: 2K  
93C57: 2K  
93C66: 4K  
93C86: 16K  
Operating Voltage  
Blank (Vcc=2.5 to 6.0V)  
1.8 (Vcc=1.8 to 6.0V)  
Package  
P = PDIP  
S = SOIC (JEDEC)  
J = SOIC (JEDEC)  
K = SOIC (EIAJ)  
U = TSSOP  
* -40˚ to +125˚C is available upon request  
93C46/56/57/66/86 F10  
Notes:  
(1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,  
Tape & Reel)  
Doc. No. 25056-00 2/98 M-1  
9

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