CAT93C66XI-GT2 [CATALYST]
4-Kb Microwire Serial CMOS EEPROM; 4 KB Microwire串行EEPROM CMOS
| 型号： | CAT93C66XI-GT2 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 4-Kb Microwire Serial CMOS EEPROM |
| 文件： | 总17页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT93C66
4-Kb Microwire Serial CMOS EEPROM
FEATURES
DESCRIPTION
The CAT93C66 is a 4-Kb CMOS Serial EEPROM
device which is organized as either 256 registers of 16
bits (ORG pin at VCC) or 512 registers of 8 bits (ORG
pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C66
features sequential read and self-timed internal write
with auto-clear. On-chip Power-On Reset circuitry
protects the internal logic against powering up in the
wrong state.
High speed operation: 2MHz
1.8V to 5.5V supply voltage range
Selectable x8 or x16 memory organization
Sequential read
Software write protection
Power-up inadvertant write protection
Low power CMOS technology
1,000,000 Program/erase cycles
100 year data retention
Industrial temperature ranges
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
For Ordering Information details, see page 15.
8-pad TDFN packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (V, X)
TSSOP (Y)
VCC
TDFN (VP2, ZD4)*
SOIC (W)
ORG
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
CAT93C66
CS
SK
DI
DO
NC
ORG
GND
DO
DI
* TDFN 3x3mm (ZD4) package is available only for Die Rev E
(not recommended for new designs)
GND
PIN FUNCTION
Pin Name
CS
Function
Chip Select
SK
Clock Input
DI
Serial Data Input
Serial Data Output
Power Supply
Ground
DO
VCC
GND
ORG
NC
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization
Memory Organization
No Connection
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1089 Rev. P
CAT93C66
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
°C
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65 to +150
-0.5 to +6.5
V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter
NEND(4) Endurance
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS (NEW PRODUCT, DIE REV. G)
CC = +1.8V to +5.5V, TA=-40°C to +85°C unless otherwise specified.
V
Symbol Parameter
ICC1 Power Supply Current (Write)
ICC2
Test Conditions
Min
Max
1
Units
mA
fSK = 1MHz, VCC = 5.0V
fSK = 1MHz, VCC = 5.0V
Power Supply Current (Read)
500
µA
Power Supply Current
(Standby) (x8 Mode)
VIN = GND or VCC, CS = GND
ORG = GND
ISB1
ISB2
2
1
µA
µA
Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC, CS = GND
ORG = Float or VCC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VOUT = GND to VCC, CS = GND
4.5V ≤ VCC < 5.5V
1
1
µA
µA
V
ILO
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
-0.1
0.8
Input High Voltage
Input Low Voltage
4.5V ≤ VCC < 5.5V
2
0
VCC + 1
VCC x 0.2
VCC + 1
0.4
V
1.8V ≤ VCC < 4.5V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
1.8V ≤ VCC < 4.5V
VCC x 0.7
V
4.5V ≤ VCC < 5.5V, IOL = 2.1mA
4.5V ≤ VCC < 5.5V, IOH = -400µA
1.8V ≤ VCC < 4.5V, IOL = 1mA
1.8V ≤ VCC < 4.5V, IOH = -100µA
V
2.4
V
0.2
V
VCC - 0.2
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, VCC = 5V, 25°C
Doc. No. 1089 Rev. P
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
D.C. OPERATING CHARACTERISTICS (MATURE PRODUCT, DIE REV. E – Not Recommended for New
Designs)
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
3
Units
mA
ICC1
ICC2
Power Supply Current (Write)
Power Supply Current (Read)
fSK = 1MHz, VCC = 5.0V
fSK = 1MHz, VCC = 5.0V
500
µA
Power Supply Current
(Standby) (x8 Mode)
VIN = GND or VCC, CS = GND
ORG = GND
ISB1
ISB2
10
10
µA
µA
Power Supply Current
(Standby) (x16 Mode)
VIN = GND or VCC, CS = GND
ORG = Float or VCC
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND to VCC
VOUT = GND to VCC, CS = GND
4.5V ≤ VCC < 5.5V
1
1
µA
µA
V
ILO
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
-0.1
0.8
Input High Voltage
Input Low Voltage
4.5V ≤ VCC < 5.5V
2
0
VCC + 1
VCC x 0.2
VCC + 1
0.4
V
1.8V ≤ VCC < 4.5V
V
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
1.8V ≤ VCC < 4.5V
VCC x 0.7
V
4.5V ≤ VCC < 5.5V, IOL = 2.1mA
4.5V ≤ VCC < 5.5V, IOH = -400µA
1.8V ≤ VCC < 4.5V, IOL = 1mA
1.8V ≤ VCC < 4.5V, IOH = -100µA
V
2.4
V
0.2
V
VCC - 0.2
V
PIN CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 5V
Symbol Test
Conditions
VOUT = 0V
VIN = 0V
Min
Typ
Max
5
Units
pF
(1)
COUT
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
(1)
CIN
5
pF
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1089 Rev. P
CAT93C66
A.C. CHARACTERISTICS(1) (NEW PRODUCT, DIE REV. G)
VCC = +1.8V to +5.5V, TA = -40°C to +85°C, unless otherwise specified.
Limits
Symbol Parameter
Units
ns
Min
50
Max
tCSS
tCSH
tDIS
CS Setup Time
CS Hold Time
0
ns
DI Setup Time
100
100
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
0.25
0.25
100
5
µs
Output Delay to 0
µs
(2)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
tEW
tCSMIN
tSKHI
ms
µs
0.25
0.25
0.25
µs
tSKLOW
tSV
µs
0.25
µs
SKMAX
DC
2000
kHz
A.C. CHARACTERISTICS (1) (MATURE PRODUCT, DIE REV E – Not Recommended for New Design)
Limits
Symbol Parameter
Units
VCC = 1.8V - 5.5V
VCC = 2.5V - 5.5V
VCC = 4.5V - 5.5V
Min
200
0
Max
Min
100
0
Max
Min
50
Max
tCSS
tCSH
tDIS
CS Setup Time
ns
ns
CS Hold Time
0
DI Setup Time
400
400
200
200
100
100
ns
tDIH
tPD1
tPD0
DI Hold Time
ns
Output Delay to 1
1
1
0.5
0.5
200
10
0.25
0.25
100
10
µs
µs
ns
Output Delay to 0
(2)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
10
tEW
tCSMIN
tSKHI
ms
µs
µs
µs
µs
kHz
1
1
1
0.5
0.5
0.5
0.25
0.25
0.25
tSKLOW
tSV
1
0.5
0.25
SKMAX
DC
250
DC
500
DC
1000
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
Doc. No. 1089 Rev. P
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
POWER-UP TIMING(1) (2)
Symbol
tPUR
Parameter
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
50 ns
≤
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C66 is a 4096-bit nonvolatile memory
intended for use with industry standard micropro–
cessors. The CAT93C66 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 11-bit instructions control the reading, writing and
erase operations of the device. When organized as X8,
seven 12-bit instructions control the reading, writing and
erase operations of the device. The CAT93C66 operates
on a single power supply and will generate on chip, the
high voltage required during any write operation.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
The format for all instructions sent to the device is a
logical “1” start bit, a 2-bit (or 4-bit) opcode, 8-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The instruction format is shown in
Instruction Set table.
INSTRUCTION SET
Address
Start
Data
Instruction
Bit
Opcode
Comments
x8
x16
x8
x16
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A8-A0
A8-A0
A8-A0
A7-A0
A7-A0
A7-A0
Read Address AN – A0
Clear Address AN – A0
D7-D0 D15-D0 Write Address AN – A0
Write Enable
11XXXXXXX 11XXXXXX
00XXXXXXX 00XXXXXX
10XXXXXXX 10XXXXXX
Write Disable
Clear All Addresses
WRAL
01XXXXXXX 01XXXXXX D7-D0 D15-D0 Write All Addresses
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1089 Rev. P
CAT93C66
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 2.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C66
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1).
Erase/Write Enable and Disable
The CAT93C66 powers up in the write disable state. Any
writing after power-up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C66 write and erase instructions, and will prevent
any accidental writing or clearing of the device. Data can
be read normally from the device regardless of the write
enable/disable status. The EWEN and EWDS
instructions timing is shown in Figure 3.
For the CAT93C66, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will auto-
matically increment to the next address and shift out
the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues
to toggle, the device will keep incrementing to the next
address automatically until it reaches to the end of the
address space, then loops back to address 0. In the
Figure 1. Sychronous Data Timing
t
t
t
CSH
SKLOW
SKHI
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
CSMIN
DIS
PD0, PD1
DO
DATA VALID
Figure 2. READ Instruction Timing
SK
CS
Don't Care
A
A
A
0
N
N–1
DI
1
1
0
tPD0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
D
0
or
or
or
7 . . .
D
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Doc. No. 1089 Rev. P
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
Write
Erase
After receiving a WRITE command (Figure 4), address
and the data, the CS (Chip Select) pin must be
deselected for a minimum of tCSMIN. The falling edge of
CS will start the self clocking clear and data store cycle
of the memory location specified in the instruction. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C66 can be determined by
selecting the device and polling the DO pin. Since this
device features Auto-Clear before write, it is NOT
necessary to erase a memory location before it is
written into.
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of tCSMIN (Figure 5). The falling edge of CS
will start the self clocking clear cycle of the selected
memory location. The clocking of the SK pin is not
necessary after the device has entered the self
clocking mode. The ready/ busy status of the
CAT93C66 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
Figure 3. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. Write Instruction Timing
SK
t
CSMIN
STANDBY
STATUS
VERIFY
CS
A
N
A
N-1
A
0
D
N
D
0
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
Figure 5. Erase Instruction Timing
SK
STANDBY
STATUS VERIFY
CS
t
CS
A
A
0
A
N
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 1089 Rev. P
CAT93C66
Erase All
Write All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C66 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to
a logical “1” state.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 7). The falling edge of CS will start the
self clocking data write to all memory locations in the
device. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C66 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
t
HZ
SV
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CSMIN
D
D
0
DI
1
0
0
0
1
N
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1089 Rev. P
8
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
PACKAGE OUTLINES
8-LEAD 300MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
4.57
A
A1
A2
b
0.38
3.05
0.36
1.14
0.21
9.02
7.62
6.09
3.81
0.56
1.77
0.35
10.16
8.25
7.11
0.46
0.26
b2
c
D
E
7.87
6.35
E1
e
2.54 BSC
eB
L
7.87
2.92
9.65
3.81
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS001
(3) Dimensioning and tolerancing per ANSI Y14.5M-1982.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 1089 Rev. P
CAT93C66
8-LEAD 150 MIL SOIC (V, W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012.
Doc. No. 1089 Rev. P
10
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
8-LEAD 208 MIL SOIC (X)
E
b
D
c
A
θ1
e
A1
L
SYMBOL
MIN
0.05
NOM
MAX
A1
A
0.25
2.03
0.48
0.25
5.33
8.26
5.38
b
0.36
0.19
5.13
7.75
5.13
c
D
E
E1
e
1.27 BSC
L
0.51
0.76
θ
1
0°
8°
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with EIAJ specification EDR-7320.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 1089 Rev. P
CAT93C66
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
q1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
0.90
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Standard MO-153
Doc. No. 1089 Rev. P
12
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
D
A1
D2
A2
A3
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.02
E2
0.55
0.20 REF
0.25
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
PIN 1 ID
D
2.00
D2
E
1.40
3.00
E2
e
1.30
L
0.50 TYP
0.30
L
0.20
0.40
b
e
3 x e
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MO-229.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 1089 Rev. P
CAT93C66
8-PAD TDFN 3X3 PACKAGE (ZD4)
3
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MO-229.
Doc. No. 1089 Rev. P
14
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C66
ORDERING INFORMATION
CAT93C66, DIE REV. G (NEW PRODUCT)*
Prefix
Device # Suffix
CAT
93C66
V
I
-G
T3
Package
L: PDIP
V: SOIC, JEDEC
W: SOIC, JEDEC
X: SOIC, EIAJ(4)
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Company ID
Product Number
93C66
Tape & Reel
T: Tape & Reel
2: 2000 units/Reel(4)
3: 3000 units/Reel
VP2: TDFN (2x3mm)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT93C66VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C66XI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
* For CAT93C66, Die Rev. G (all packages) availability, please contact factory.
CAT93C66, DIE REV. E, MATURE PRODUCT (Not Recommended for New Design)
Prefix
Device # Suffix
93C66
CAT
V
I
-1.8
-G T3
Rev E(4)
Temperature Range
I = Industrial (-40ºC to 85ºC)
A = Automotive (-40ºC to 105ºC)
E = Extended (-40ºC to 125ºC)
Die Revision
93C66: E
Company ID
Product Number
93C66
Tape & Reel
Package
L: PDIP
V: SOIC, JEDEC
W: SOIC, JEDEC
X: SOIC, EIAJ(5)
Y: TSSOP
Operating Voltage
Blank: VCC = 2.5V to 5.5V
1.8: VCC = 1.8V to 5.5V
T: Tape & Reel
2: 2000 units/Reel(5)
3: 3000 units/Reel
Lead Finish
Blank: Matte-Tin
G: NiPdAu
ZD4: TDFN (3x3mm)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu.
(3) The device used in the above example is a CAT93C66VI-1.8-GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt
Operating Voltage, NiPdAu finish, Tape & Reel.)
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE.) For additional informa-
tion, please contact your Catalyst sales office.
(5) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C66XI-T2.
(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. 1089 Rev. P
CAT93C66
REVISION HISTORY
Date
Rev. Comments
05/14/04
L
New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56,
CAT93C57, CAT93C66, CAT93C76 and CAT93C86 have been separated into single
data sheets
Add Die Revision ID Letter
Update Features
Update Description
Update Pin Condition
Add Functional Diagram
Update Pin Function
Update D.C. Operating Characteristics
Update Pin Capacitance
Update Instruction Set
Update Device Operation
Update Ordering Information
Update Revision History
Update Rev Number
10/13/06
11/17/06
M
N
Update Features
Update Pin Configuration / Packages
Update Functional Symbol
Update Pin Functions
Update D.C. Operating Characteristics (VCC Range)
Add Package Drawings
Update Example of Ordering Information
Remove "Die Rev E" from the title
Update Pin Configuration / Packages
Update Absolute Maximum Rating
Update Reliability Characteristics
Update D.C. Operating Characteristics
Added A.C. Characteristics for Die Rev G
Rearrange / Format Text and Figures
Added Example of Ordering Information for Die Rev G
Update separate DC Characteristics for Die Rev. G and Die Rev. E.
Updated Example of Ordering Information
12/07/06
04/03/07
O
P
Update note on page 1
Update D.C. Operating Characteristics (New Product, Die Rev. G)
Update Ordering Information – CAT93C66, Die Rev. G (New Product)
Doc. No. 1089 Rev. P
16
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: 1089
Revision:
P
Issue date:
04/03/07
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