CAT93C76RD4E-REVA [CATALYST]
EEPROM, 512X16, Serial, CMOS, 3 X 3 MM, TDFN-8;
| 型号： | CAT93C76RD4E-REVA |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 512X16, Serial, CMOS, 3 X 3 MM, TDFN-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 内存集成电路 |
| 文件： | 总10页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT93C76 (Rev. A)
8K-Bit Microwire Serial EEPROM
TM
FEATURES
ꢀ High speed operation: 3MHz @ VCC ≥ 2.5V
ꢀ Low power CMOS technology
ꢀ Power-up inadvertant write protection
ꢀ 1,000,000 Program/erase cycles
ꢀ 100 year data retention
ꢀ 1.8 to 5.5 volt operation
ꢀ Selectable x8 or x16 memory organization
ꢀ Self-timed write cycle with auto-clear
ꢀ Software write protection
ꢀ Industrial and extended temperature ranges
ꢀ Sequential read
ꢀ “Green” package option available
DESCRIPTION
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. The device is
designed to endure 1,000,000 program/erase cycles
and has a data retention of 100 years. The device is
available in 8-pin DIP, SOIC, TSSOP and 8-pad TDFN
packages.
The CAT93C76 is an 8K-bit Serial EEPROM memory
device which is configured as either registers of 16 bits
(ORG pin at VCC or Not Connected) or 8 bits (ORG pin
at GND). Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT93C76 is
PIN CONFIGURATION
FUNCTIONAL SYMBOL
VCC
SOIC Package (S, V)
DIP Package (P, L)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
CC
NC
CS
SK
DI
V
CC
NC
ORG
GND
ORG
ORG
GND
DI
CS
DO
DO
DO
SK
TSSOP Package (U,Y)
1
2
3
4
8
7
6
5
CS
SK
DI
GND
V
CC
NC
PIN FUNCTIONS
ORG
GND
DO
Pin Name
CS
Function
Chip Select
TDFN Package (RD4, ZD4)
SK
Serial Clock Input
Serial Data Input
Serial Data Output
+1.8 to 5.5V Power Supply
Ground
1
2
3
4
8
7
6
5
CS
V
CC
DI
SK
DI
NC
DO
ORG
DO
GND
VCC
GND
ORG
NC
Top View
Memory Organization
No Connection
Note: When the ORG pin is connected to VCC, x16 organization is
selected. When it is connected to ground, x8 organization is selected.
If the ORG pin is left unconnected, then an internal
pull-up device will select x16 organization.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1090, Rev. A
CAT93C76
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses exceeding those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other conditions
outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device
performance and reliability.
Voltage on any Pin with
Respect to Ground(1) ............. -2.0V to +VCC +2.0V
V
CC with Respect to Ground ................ -2.0V to +7.0V
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified.
V
CC
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC1
Power Supply Current
(Write)
fSK = 1MHz
VCC = 5.0V
1
3
mA
ICC2
ISB1
ISB2
Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
300
2
500
10
µA
µA
µA
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
0(5)
10
ILI
ILO
Input Leakage Current
Output Leakage Current
ORG Pin Leakage Current
Input Low Voltage
VIN = 0V to VCC
VOUT = 0V to VCC, CS = 0V
ORG = GND or ORG = VCC
4.5V ≤ VCC ≤ 5.5V
0(5)
0(5)
1
10
10
µA
µA
µA
V
ILORG
VIL1
VIH1
VIL2
VIH2
VOL1
10
-0.1
0.8
Input High Voltage
4.5V ≤ VCC ≤ 5.5V
2
0
VCC + 1
VCC x 0.2
VCC+1
0.4
V
Input Low Voltage
1.8V ≤ VCC < 4.5V
V
Input High Voltage
1.8V ≤ VCC < 4.5V
VCC x 0.7
V
Output Low Voltage
4.5V ≤ VCC ≤ 5.5V
V
IOL = 2.1mA
VOH1
VOL2
Output High Voltage
Output Low Voltage
4.5V ≤ VCC ≤ 5.5V
IOH = -400µA
2.4
V
V
1.8V ≤ VCC < 4.5V
IOL = 100µA
0.1
VOH2
Output High Voltage
1.8V ≤ VCC < 4.5V
IOH = -100µA
VCC - 0.2
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second.
(3) These parameters are tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1V to V +1V.
CC
(5) 0 µA is defined as less than 900 nA.
Doc. No. 1090, Rev. A
2
CAT93C76
PIN CAPACITANCE
Symbol
Test
Conditions
VOUT=0V
VIN=0V
Min
Typ
Max
Units
pF
(1)
COUT
Output Capacitance (DO)
5
5
(1)
CIN
Input Capacitance (CS, SK, DI, ORG)
pF
(2)
INSTRUCTION SET
Address
Data
Instruction Start Bit Opcode
x8
x16
x8
x16
Comments
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A10-A0
A10-A0
A10-A0
A9-A0
A9-A0
A9-A0
Read Address AN– A0
Clear Address AN– A0
D7-D0 D15-D0 Write Address AN– A0
Write Enable
11XXXXXXXXX 11XXXXXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXXXXXX 10XXXXXXXX
01XXXXXXXXX 01XXXXXXXX
Write Disable
Clear All Addresses
WRAL
D7-D0 D15-D0 Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC
=
VCC
=
1.8V-2.5V
2.5V-5.5V
Test
Symbol Parameter
Conditions
Min
100
0
Max
Min
Max
Units
ns
tCSS
tCSH
tDIS
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
50
0
ns
100
100
50
50
ns
tDIH
tPD1
tPD0
ns
Output Delay to 1
Output Delay to 0
250
250
150
5
150
150
100
5
ns
CL = 100pF
(3)
ns
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
ns
tEW
tCSMIN
tSKHI
ms
ns
200
250
250
150
150
150
ns
tSKLOW Minimum SK Low Time
tSV Output Delay to Status Valid
SKMAX Maximum Clock Frequency
ns
250
100
ns
DC
1000
DC
3000
kHz
NOTE:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or
“0” for READ, WRITE and ERASE commands.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
Doc. No. 1090, Rev. A
3
CAT93C76
(1)(2)
POWER-UP TIMING
Symbol
tPUR
Parameter
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
NOTE:
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
PUR
PUW
CC
DEVICE OPERATION
Read
The CAT93C76 is a 8192-bit nonvolatile memory
intendedforusewithindustrystandardmicroprocessors.
The CAT93C76 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 13-bit
instructions control the read, write and erase operations
of the device. When organized as X8, seven 14-bit
instructions control the read, write and erase
operations of the device. The CAT93C76 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Upon receiving a READ command and an address
(clockedintotheDIpin),theDOpinoftheCAT93C76will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed(MSBfirst). Theoutputdatabitswilltoggleon
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAT93C76, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DIpin. TheDOpinwillenterthehighimpedancestateon
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applica-
tions where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device
and polling the DO pin. Since this device features Auto-
Clear before write, it is NOT necessary to erase a
memory location before it is written into.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The most significant bit of the address is
“don’t care” but it must be present.
Doc. No. 1090, Rev. A
4
CAT93C76
Figure 1. Sychronous Data Timing
t
t
t
SKLOW
SKHI
CSH
SK
t
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
DIS
PD0, PD1
CSMIN
DO
DATA VALID
Figure 2. Read Instruction Timing
SK
CS
Don't Care
A
A
A
0
N
N–1
DI
1
1
0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
D
0
or
or
D
or
7 . . .
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Figure 3. Write Instruction Timing
SK
t
CSMIN
STATUS
STANDBY
CS
VERIFY
A
A
A
0
D
D
0
N
N-1
N
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
Doc. No. 1090, Rev. A
5
CAT93C76
Write All
Erase
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C76 can be determined by selecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking
clearcycleoftheselectedmemorylocation.Theclocking
of the SK pin is not necessary after the device has
enteredtheselfclockingmode.Theready/busystatusof
the CAT93C76 can be determined by selecting the
deviceandpollingtheDOpin. Oncecleared, thecontent
of a cleared location returns to a logical “1” state.
Erase/Write Enable and Disable
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edgeoftheclock(SK)inordertostarttheself-timedhigh
voltage cycle. This is important because if CS is brought
low before or after this specific frame window, the
addressed location will not be programmed or erased.
TheCAT93C76powersupinthewritedisablestate. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable)instruction.Oncethewriteinstructionisenabled,
itwillremainenableduntilpowertothedeviceisremoved,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C76 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Power-On Reset (POR)
The CAT93C76 incorporates Power-On Reset (POR)
circuitrywhichprotectsthedeviceagainstmalfunctioning
while VCC is lower than the recommended operating
voltage.
Erase All
The device will power up into a read-only state and will
power-down into a reset state when VCC crosses the
POR level of ~1.3 V.
UponreceivinganERALcommand,theCS(ChipSelect)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Figure 4. Erase Instruction Timing
SK
STANDBY
STATUS VERIFY
CS
t
CS
A
A
0
A
N
N-1
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
Doc. No. 1090, Rev. A
6
CAT93C76
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CSMIN
D
D
DI
1
0
0
0
1
N
0
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1090, Rev. A
7
CAT93C76
ORDERING INFORMATION
Prefix
Device #
Suffix
S
Rev A(2)
CAT
93C76
TE13
I
Optional
Company ID
Product
Number
Temperature Range
I = Industrial (-40°C to +85°C)
E = Extended (-40°C to +125°C)
Tape & Reel
Die Revision
Package
P = PDIP
S = SOIC (JEDEC)
U= TSSOP
RD4 = TDFN (3x3mm)
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
ZD4 = TDFN (3x3mm, Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 93C76SI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA.) For additional
information, please contact your Catalyst sales office.
Doc. No. 1090, Rev. A
8
CAT93C76
REVISION HISTORY
Date
Revision Comments
08/11/04
A
Initial Issue
Doc. No. 1090, Rev. A
9
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1090
Revison:
A
Issue date:
08/11/04
www.catalyst-semiconductor.com
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明