CAT93C86PE [CATALYST]

EEPROM, 1KX16, Serial, CMOS, PDIP8, PLASTIC, DIP-8;


型号：	CAT93C86PE
厂家：	CATALYST SEMICONDUCTOR
描述：	EEPROM, 1KX16, Serial, CMOS, PDIP8, PLASTIC, DIP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总10页 (文件大小：80K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT93C46/56/57/66/86

1K/2K/2K/4K/16K-Bit Microwire Serial EEPROM

FEATURES

ꢀ High speed operation:

ꢀ Power-up inadvertant write protection

ꢀ 1,000,000 Program/erase cycles

ꢀ 100 year data retention

– 93C46/56/57/66: 1MHz

– 93C86: 3MHz

ꢀ Low power CMOS technology

ꢀ Commercial, industrial and automotive

ꢀ 1.8 to 6.0 volt operation

temperature ranges

ꢀ Selectable x8 or x16 memory organization

ꢀ Self-timed write cycle with auto-clear

ꢀ Hardware and software write protection

ꢀ Sequential read (except CAT93C46)

ꢀꢀꢀProgram enable (PE) pin (CAT93C86 only)

ꢀꢀꢀ“Green” package option available

DESCRIPTION

CMOS EEPROM floating gate technology. The devices

aredesignedtoendure1,000,000program/erasecycles

and have a data retention of 100 years. The devices are

available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and 8-

pad TDFN packages.

The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit

Serial EEPROM memory devices which are configured

as either registers of 16 bits (ORG pin at V_CC) or 8 bits

(ORGpinatGND). Eachregistercanbewritten(orread)

serially by using the DI (or DO) pin. The CAT93C46/56/

57/66/86 are manufactured using Catalyst’s advanced

PIN CONFIGURATION

TSSOP Package (U,Y)

SOIC Package (J,W) SOIC Package (S,V)

DIP Package (P, L)

SOIC Package (K,X)

ORG

GND

NC (PE*)

ORG

NC (PE*)

ORG

GND

*Only For 93C86

** TSSOP (U/Y) package only available for 93C46/56/57/66

TDFN Package (RD4, ZD4)

PIN FUNCTIONS

BLOCK DIAGRAM

GND

Pin Name

Function

Chip Select

Clock Input

CAT93C46

CAT93C56

CAT93C66

ORG

GND

ADDRESS

DECODER

MEMORY ARRAY

ORGANIZATION

Serial Data Input

Serial Data Output

+1.8 to 6.0V Power Supply

Ground

ORG

Bottom View

V_CC

GND

ORG

DATA

Memory Organization

No Connection

OUTPUT

BUFFER

MODE DECODE

LOGIC

PE*

Program Enable

PE*

Note: When the ORG pin is connected to VCC,

the x16 organization is selected. When it is

connected to ground, the x8 pin is selected. If

the ORG pin is left unconnected, then an internal

pullup device will select the x16 organization.

CLOCK

GENERATOR

Characteristics subject to change without notice.

Doc. No. 1023, Rev. J

93C46/56/57/66/86

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias .................. -55°C to +125°C

Storage Temperature........................ -65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Voltage on any Pin with

Respect to Ground⁽¹⁾............. -2.0V to +V_CC+2.0V

_CCwith Respect to Ground ................ -2.0V to +7.0V

Package Power Dissipation

Capability (T_A= 25°C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Reference Test Method

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

Min

1,000,000

100

Typ

Max

Units

Cycles/Byte

Years

(3)

N_END

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-Up

(3)

V_ZAP

2000

Volts

(3)(4)

I_LTH

100

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

I_CC1

Power Supply Current

(Operating Write)

f_SK= 1MHz

V_CC= 5.0V

I_CC2

I_SB1

Power Supply Current

(Operating Read)

f_SK= 1MHz

V_CC= 5.0V

500

µA

Power Supply Current

(Standby) (x8 Mode)

CS = 0V

ORG=GND

(5)

I_SB2

Power Supply Current

(Standby) (x16Mode)

CS=0V

ORG=Float or V_CC

I_LI

Input Leakage Current

V_IN= 0V to V_CC

µA

I_LO

Output Leakage Current

(Including ORG pin)

V_OUT= 0V to V_CC

CS = 0V

V_IL1

V_IH1

V_IL2

V_IH2

V_OL1

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

4.5V ≤ V_CC< 5.5V

1.8V ≤ V_CC< 4.5V

4.8V ≤ V_CC< 4.5V

-0.1

0.8

V_CC+ 1

V_CCx 0.2

V_CC+1

0.4

V_CCx 0.7

4.5V ≤ V_CC< 5.5V

I_OL= 2.1mA

V_OH1

V_OL2

Output High Voltage

Output Low Voltage

4.5V ≤ V_CC< 5.5V

I_OH= -400µA

2.4

1.8V ≤ V_CC< 4.5V

0.2

I_OL= 1mA

V_OH2

Output High Voltage

1.8V ≤ V_CC< 4.5V

I_OH= -100µA

V_CC- 0.2

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

(5) Standby Current (ISB )=0µA (<900nA) for 93C46/56/57/66, (ISB )=2µA for 93C86.

Doc. No. 1023, Rev. J

93C46/56/57/66/86

PIN CAPACITANCE

Symbol

Test

Conditions

V_OUT=0V

V_IN=0V

Min

Typ

Max

Units

(3)

C_OUT

Output Capacitance (DO)

(3)

C_IN

Input Capacitance (CS, SK, DI, ORG)

INSTRUCTION SET

(2)

Instruction Device Start Opcode

Address

Data

x8 x16

Comments

Type

Bit

x16

READ

ERASE

WRITE

EWEN

EWDS

ERAL

93C46

93C56⁽¹⁾

93C66

93C57

93C86

A6-A0

A8-A0

A7-A0

A10-A0

A5-A0

A7-A0

A6-A0

A9-A0

Read Address AN–A0

93C46

93C56⁽¹⁾

93C66

93C57

93C86

A6-A0

A8-A0

A7-A0

A10-A0

A5-A0

A7-A0

A6-A0

A9-A0

Clear Address AN–A0

93C46

93C56⁽¹⁾

93C66

93C57

93C86

A6-A0

A8-A0

A7-A0

A10-A0

A5-A0

A7-A0

A6-A0

A9-A0

D7-D0 D15-D0 Write Address AN–A0

D7-D0 D15-D0

93C46

93C56

93C66

93C57

93C86

11XXXXX

11XXXXXXX

11XXXXXX

11XXXX

11XXXXXX

11XXXXX

Write Enable

Write Disable

11XXXXXXXXX 11XXXXXXXX

93C46

93C56

93C66

93C57

93C86

00XXXXX

00XXXXXXX

00XXXXXX

00XXXX

00XXXXXX

00XXXXX

00XXXXXXXXX 00XXXXXXXX

93C46

93C56

93C66

93C57

93C86

10XXXXX

10XXXXXXX

10XXXXXX

10XXXX

10XXXXXX

10XXXXX

Clear All Addresses

10XXXXXXXXX 10XXXXXXXX

WRAL

93C46

93C56

93C66

93C57

93C86

01XXXXX

01XXXXXXX

01XXXXXX

01XXXX

01XXXXXX

01XXXXX

D7-D0 D15-D0

Write All Addresses

01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0

Note:

(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE

and ERASE commands.

(2) Applicable only to 93C86

(3) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 1023, Rev. J

93C46/56/57/66/86

A.C. CHARACTERISTICS (93C46/56/57/66)

Limits

V_CC

2.5V-6V

V_CC

1.8V-6V

V_CC

4.5V-5.5V

Test

SYMBOL PARAMETER

Conditions

Min Max Min

Max Min

Max

Units

t_CSS

t_CSH

t_DIS

CS Setup Time

200

100

CS Hold Time

DI Setup Time

400

200

100

t_DIH

t_PD1

t_PD0

DI Hold Time

Output Delay to 1

0.5

200

0.25

100

µs

C_L= 100pF

(3)

Output Delay to 0

µs

(1)

t_HZ

Output Delay to High-Z

Program/Erase Pulse Width

Minimum CS Low Time

Minimum SK High Time

Minimum SK Low Time

Output Delay to Status Valid

Maximum Clock Frequency

400

t_EW

µs

t_CSMIN

t_SKHI

t_SKLOW

t_SV

0.5

0.25

µs

0.5

0.25

µs

SK_MAX

250

500

1000

kHz

A.C. CHARACTERISTICS (93C86)

Limits

V_CC

1.8V-6V

V_CC

2.5V-6V

Min

V_CC

4.5V-5.5V

Test

SYMBOL PARAMETER

Conditions

Min Max

Max Min Max Units

t_CSS

t_CSH

t_DIS

CS Setup Time

200

100

µs

CS Hold Time

DI Setup Time

200

100

t_DIH

t_PD1

t_PD0

DI Hold Time

Output Delay to 1

0.5

200

0.15

100

C_L= 100pF

(3)

Output Delay to 0

(1)

t_HZ

Output Delay to High-Z

Program/Erase Pulse Width

Minimum CS Low Time

Minimum SK High Time

Minimum SK Low Time

Output Delay to Status Valid

Maximum Clock Frequency

400

t_EW

t_CSMIN

t_SKHI

t_SKLOW

t_SV

0.5

0.15

0.5

0.1

SK_MAX

500

1000 DC 3000 kHz

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Doc. No. 1023, Rev. J

93C46/56/57/66/86

(1)(2)

POWER-UP TIMING

SYMBOL

PARAMETER

Max

Units

t_PUR

Power-up to Read Operation

Power-up to Write Operation

t_PUW

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

(3) The input levels and timing reference points are shown in “AC Test Conditions” table.

A.C. TEST CONDITIONS

Input Rise and Fall Times

Input Pulse Voltages

≤ 50ns

0.4V to 2.4V

4.5V ≤ V_CC≤ 5.5V

1.8V ≤ V_CC≤ 4.5V

Timing Reference Voltages

Input Pulse Voltages

0.8V, 2.0V

0.2V_CCto 0.7V_CC

0.5V_CC

Timing Reference Voltages

Doc. No. 1023, Rev. J

93C46/56/57/66/86

DEVICE OPERATION

the DI pin on the rising edge of the clock (SK). The DO

pin is normally in a high impedance state except when

reading data from the device, or when checking the

ready/busy status after a write operation.

The CAT93C46/56(57)66/86 is a 1024/2048/4096/

16,384-bit nonvolatile memory intended for use with

industrystandardmicroprocessors. TheCAT93C46/56/

57/66/86 can be organized as either registers of 16 bits

or 8 bits. When organized as X16, seven 9-bit instruc-

tions for 93C46; seven 10-bit instructions for 93C57;

seven 11-bit instructions for 93C56 and 93C66; seven

13-bitinstructionsfor93C86;controlthereading, writing

and erase operations of the device. When organized as

X8, seven 10-bit instructions for 93C46; seven 11-bit

instructions for 93C57; seven 12-bit instructions for

93C56 and 93C66: seven 14-bit instructions for 93C86;

control the reading, writing and erase operations of the

device.TheCAT93C46/56/57/66/86operatesonasingle

power supply and will generate on chip, the high voltage

required during any write operation.

The ready/busy status can be determined after the start

ofawriteoperationbyselectingthedevice(CShigh)and

polling the DO pin; DO low indicates that the write

operation is not completed, while DO high indicates that

the device is ready for the next instruction. If necessary,

the DO pin may be placed back into a high impedance

state during chip select by shifting a dummy “1” into the

DIpin. TheDOpinwillenterthehighimpedancestateon

the falling edge of the clock (SK). Placing the DO pin into

the high impedance state is recommended in applica-

tions where the DI pin and the DO pin are to be tied

together to form a common DI/O pin.

Instructions, addresses, and write data are clocked into

Figure 1. Sychronous Data Timing

CSH

SKLOW

SKHI

DIS

DIH

VALID

CSS

CSMIN

DIS

PD0, PD1

DATA VALID

93C46/56/57/66/86 F03

Figure 2a. Read Instruction Timing (93C46)

CSMIN

STANDBY

N—1

HIGH-Z

PD0

N—1

93C46/56/57/66/86 F04

Doc. No. 1023, Rev. J

93C46/56/57/66/86

The format for all instructions sent to the device is a

logical"1"startbit,a2-bit(or4-bit)opcode,6-bit(93C46)/

/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)

(an additional bit when organized X8) and for write

operationsa16-bitdatafield(8-bitforX8organizations).

increment to the next address and shift out the next data

word in a sequential READ mode. As long as CS is

continuously asserted and SK continues to toggle, the

device will keep incrementing to the next address

automatically until it reaches to the end of the address

space, then loops back to address 0. In the sequential

READ mode, only the initial data word is preceeded by

a dummy zero bit. All subsequent data words will follow

without a dummy zero bit.

Note: This note is applicable only to 93C86. The Write,

Erase, Write all and Erase all instructions require PE=1.

If PE is left floating, 93C86 is in Program Enabled mode.

ForWriteEnableandWriteDisableinstructionPE=don’t

care.

Write

Read

After receiving a WRITE command, address and the

data, the CS (Chip Select) pin must be deselected for a

minimum of t_CSMIN. The falling edge of CS will start the

self clocking clear and data store cycle of the memory

location specified in the instruction. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93C46/56/57/66/86canbedeterminedbyselecting

the device and polling the DO pin. Since this device

features Auto-Clear before write, it is NOT necessary to

erase a memory location before it is written into.

Upon receiving a READ command and an address

(clocked into the DI pin), the DO pin of the CAT93C46/

56/57/66/86 will come out of the high impedance state

and, after sending an initial dummy zero bit, will begin

shifting out the data addressed (MSB first). The output

databitswilltoggleontherisingedgeoftheSKclockand

are stable after the specified time delay (t_PD0or t_PD1).

For the CAT93C56/57/66/86, after the initial data word

has been shifted out and CS remains asserted with the

SKclockcontinuingtotoggle,thedevicewillautomatically

Figure 2b. Read Instruction Timing (93C56/57/66/86)

Don't Care

N–1

HIGH-Z

Dummy 0

Address + 1 Address + 2 Address + n

15 . . .

7 . . .

Figure 3. Write Instruction Timing

CSMIN

STANDBY

STATUS

VERIFY

N-1

BUSY

HIGH-Z

READY

HIGH-Z

93C46/56/57/66/86 F05

Doc. No. 1023, Rev. J

93C46/56/57/66/86

Erase All

Erase

UponreceivinganERALcommand,theCS(ChipSelect)

pin must be deselected for a minimum of t_CSMIN. The

falling edge of CS will start the self clocking clear cycle

of all memory locations in the device. The clocking of the

SK pin is not necessary after the device has entered the

self clocking mode. The ready/busy status of the

CAT93C46/56/57/66/86canbedeterminedbyselecting

the device and polling the DO pin. Once cleared, the

contents of all memory bits return to a logical “1” state.

Upon receiving an ERASE command and address, the

CS (Chip Select) pin must be deasserted for a minimum

oft_CSMIN.ThefallingedgeofCSwillstarttheselfclocking

clearcycleoftheselectedmemorylocation.Theclocking

of the SK pin is not necessary after the device has

enteredtheselfclockingmode.Theready/busystatusof

the CAT93C46/56/57/66/86 can be determined by

selecting the device and polling the DO pin. Once

cleared, the content of a cleared location returns to a

logical “1” state.

Write All

Erase/Write Enable and Disable

Upon receiving a WRAL command and data, the CS

(Chip Select) pin must be deselected for a minimum of

The CAT93C46/56/57/66/86 powers up in the write

disable state. Any writing after power-up or after an

EWDS (write disable) instruction must first be preceded

by the EWEN (write enable) instruction. Once the write

instruction is enabled, it will remain enabled until power

to the device is removed, or the EWDS instruction is

sent. The EWDS instruction can be used to disable all

CAT93C46/56/57/66/86 write and clear instructions,

and will prevent any accidental writing or clearing of the

device. Data can be read normally from the device

regardless of the write enable/disable status.

t_CSMIN. The falling edge of CS will start the self clocking

data write to all memory locations in the device. The

clocking of the SK pin is not necessary after the device

hasenteredtheselfclockingmode. (Note1.) Theready/

busy status of the CAT93C46/56/57/66/86 can be

determined by selecting the device and polling the DO

pin. It is not necessary for all memory locations to be

cleared before the WRAL command is executed.

Figure 4. Erase Instruction Timing

STANDBY

STATUS VERIFY

N-1

HIGH-Z

BUSY

READY

HIGH-Z

93C46/56/57/66/86 F06

Doc. No. 1023, Rev. J

93C46/56/57/66/86

Figure 5. EWEN/EWDS Instruction Timing

STANDBY

* ENABLE=11

DISABLE=00

93C46/56/57/66/86 F07

Figure 6. ERAL Instruction Timing

STATUS VERIFY

STANDBY

HIGH-Z

BUSY

READY

93C46/56/57/66/86 F08

Figure 7. WRAL Instruction Timing

STATUS VERIFY

STANDBY

CSMIN

BUSY

READY

HIGH-Z

93C46/56/57/66/86 F09

Doc. No. 1023, Rev. J

93C46/56/57/66/86

ORDERING INFORMATION

Prefix

Device #

Suffix

-1.8

CAT

93C46

TE13

Optional

Company ID

Product

Temperature Range

Tape & Reel

Number

Blank = Commercial (0° - 70°C)

I = Industrial (-40° - 85°C)

A = Automotive (-40° - 105°C)

E = Extended (-40°C to + 125°C)

TE13: 2000/Reel

93C46: 1K

93C56: 2K

93C57: 2K

93C66: 4K

93C86: 16K

Operating Voltage

Blank (V_cc=2.5 to 6.0V)

1.8 (V_cc=1.8 to 6.0V)

Package

P = PDIP

S = SOIC (JEDEC)

J = SOIC (JEDEC)

K = SOIC (EIAJ)

U= TSSOP*

RD4 = TDFN (3x3mm)

ZD4 = TDFN (3x3mm, Lead free, Halogen free)

L = PDIP (Lead free, Halogen free)

V = SOIC, JEDEC (Lead free, Halogen free)

W= SOIC, JEDEC (Lead free, Halogen free)

X = SOIC, EIAJ (Lead free, Halogen free)

Y = TSSOP (Lead free, Halogen free)*

*CAT93C46/56/57/66 only

Notes:

(1) The device used in the above example is a 93C46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,

Tape & Reel)

(2) TSSOP (U/Y) package only available for 93C46/56/57/66

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AE²™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

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PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

www.catalyst-semiconductor.com

Doc. No. 1023, Rev. J

Publication #: 1023

Revison:

Issue date:

Type:

6/23/03

Final

CAT93C86PE [CATALYST]

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