CAT93HC46VE-TE13REVH [CATALYST]
EEPROM, 64X16, Serial, CMOS, PDSO8, SOIC-8;
| 型号： | CAT93HC46VE-TE13REVH |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 64X16, Serial, CMOS, PDSO8, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总9页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT93HC46
1-kb High Speed Microwire Serial EEPROM
TM
FEATURES
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ High speed operation: 4 MHz @ 5.0 V
■ 1.8 to 5.5 volt operation
■ Selectable x8 or x16 word organization
■ Sequential Read
■ Industrial and extended temperature ranges
■ 8-Lead PDIP, SOIC, MSOP and TSSOP
■ Software write protection
packages
■ Power-up inadvertent write protection
DESCRIPTION
technology. Thedeviceisdesignedtoendure1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, SOIC,
MSOP or TSSOP packages.
The CAT93HC46 is a 1-kb Serial EEPROM memory
device which is configured as registers of either 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
PIN CONFIGURATION
FUNCTIONAL SYMBOL
V
CC
SOIC Package (J, W)
DIP Package (P, L)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
ORG
GND
DO
NC
CC
ORG
NC
V
CC
CS
ORG
GND
DO
DI
DO
SK
DI
CAT93HC46
SK
MSOP Package (R, Z)
SOIC Package (S, V)
CS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
CS
SK
DI
V
CC
CC
NC
ORG
GND
NC
ORG
GND
V
SS
DO
DO
PIN FUNCTIONS
TSSOP Package (U, Y)
Pin Name
CS
Function
1
2
3
4
8
7
6
5
CS
V
CC
SK
DI
NC
Chip Select
ORG
GND
SK
Clock Input
DO
DI
Serial Data Input
DO
Serial Data Output
1.8 to 5.5 V Power Supply
Ground
VCC
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
GND
ORG
NC
Memory Organization
No Connection
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1008,Rev. H
1
CAT93HC46
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Pin with Respect to Ground(1) .... -2.0 V to VCC + 2.0 V
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
V
CC with Respect to Ground ................ -2.0 V to 7.0 V
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
Industrial Temperature Range (-40°C to 85°C)
Limits
Typ
Symbol
ICC1
Parameter
Min
Max
2
Units
mA
µA
Test Conditions
Power Supply Current (Write)
Power Supply Current (Read)
Standby Supply Current (x8)
Standby Supply Current (x16)
Input Leakage Current
Output Leakage Current
Input Low Voltage
fSK = 4 MHz, VCC = 5.0 V
fSK = 4 MHz, VCC = 5.0 V
CS = GND, ORG=GND
ICC2
200
10
ISB1
µA
(5)
ISB2
0
10
µA
CS = GND, ORG = Float or VCC
VIN = 0 V to VCC, CS = GND
VOUT = 0 V to VCC, CS = GND
4.5 V ≤ VCC < 5.5 V
ILI
1
µA
ILO
1
µA
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
-0.1
0.8
VCC + 1
Input High Voltage
2
0
4.5 V ≤ VCC < 5.5 V
Input Low Voltage
VCC x 0.2
VCC + 1
0.4
1.8 V ≤ VCC < 4.5 V
Input High Voltage
VCC x 0.7
1.8V ≤ VCC < 4.5 V
Output Low Voltage
4.5 V ≤ VCC < 5.5 V, IOL = 2.1 mA
4.5 V ≤ VCC < 5.5 V, IOH = -400 µA
1.8 V ≤ VCC < 4.5 V, IOL = 1 mA
1.8 V ≤ VCC < 4.5 V, IOH = -100 µA
Output High Voltage
2.4
V
Output Low Voltage
0.2
Output High Voltage
VCC - 0.2
Note:
(1) The minimum DC input voltage is -0.5 V. During transitions, inputs may undershoot to -2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1 V to V + 1 V.
CC
(5) Standby Current (ISB ) = 0 µA (<900 nA).
2
Doc. No. 1008, Rev. H
2
CAT93HC46
(1)(2)
POWER-UP TIMING
Symbol
tPUR
Parameter
Min
Typ
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
A.C. CHARACTERISTICS
Industrial Temperature Range (-40°C to 85°C)
1.8 V - 5.5 V
2.5 V - 5.5 V
4.5 V - 5.5 V
Test
Symbol
SKMAX
tCSS
Parameter
Min
DC
240
0
Max
1
Min
DC
120
0
Max
2
Min
DC
60
0
Max
4
Units
Conditions
Maximum Clock Frequency
CS Setup Time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tCSH
CS Hold Time
tDIS
DI Setup Time
240
240
120
120
60
60
tDIH
DI Hold Time
tPD1
Output Delay to 1
480
480
240
240
240
120
120
120
60
CL = 100 pF
(3)
tPD0
Output Delay to 0
(1)
tHZ
Output Delay to High-Z
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Program/Erase Pulse Width
tCSMIN
tSKHI
tSKLOW
tSV
240
480
240
120
240
120
60
120
60
480
5
240
5
120
5
tEW
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
PUR
PUW
CC
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 10 ns
0.4 V to 2.4 V
4.5 V ≤ VCC ≤ 5.5 V
4.5 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC ≤ 4.5 V
1.8 V ≤ VCC ≤ 4.5 V
Timing Reference Voltages
Input Pulse Voltages
0.8 V, 2.0 V
VCC x 0.2 to VCC x 0.8
VCC x 0.5
Timing Reference Voltages
Doc. No. 1008, Rev. H
3
CAT93HC46
DEVICE OPERATION
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state by shifting a dummy “1” into the DI pin. The DO pin
will enter the high impedance state on the falling edge of
theclock(SK).PlacingtheDOpinintothehighimpedance
state is recommended in applications where the DI pin
and the DO pin are to be tied together to form a common
DI/O pin.
The CAT93HC46 is a 1024-bit nonvolatile memory
intendedforusewithindustrystandardmicroprocessors.
TheCAT93HC46canbeorganizedasregistersofeither
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the operation of the device.
TheCAT93HC46operatesonasinglepowersupplyand
will generate on chip the high voltage required during
write operation.
Instructions, addresses, anddataareclockedintotheDI
pin on the rising edge of the clock (SK). The DO pin is
normallyinahighimpedancestate,exceptwhenreading
data from the device, or when checking the ready/busy
status after a write operation.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organization).
INSTRUCTION SET
Start
Bit Opcode x8
Address
x16
Data
Instruction
READ
x8
x16 Comments
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6-A0 A5-A0
A6-A0 A5-A0
A6-A0 A5-A0
Read Address AN–A0
Clear Address AN–A0
ERASE
WRITE
EWEN
EWDS
ERAL
D7-D0
D7-D0
D15-D0 Write Address AN–A0
Write Enable
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
Write Disable
Clear All Addresses
D15-D0 Write All Addresses
WRAL
Figure 1. Sychronous Data Timing
t
t
t
SKLOW
SKHI
CSH
SK
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
t
DIS
PD0, PD1
CSMIN
DO
DATA VALID
Doc. No. 1008, Rev. H
4
CAT93HC46
Read
Write
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state; after an initial
dummy zero bit, data will be shifted out, MSB first. The
output will toggle on the rising edge of the SK clock and
After receiving a WRITE command, address and data,
the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self-timed clear and data store cycle into the specified
memory location. The clocking of the SK pin is not
necessary after the device has entered the self-timed
mode.(Note1.)Theready/busystatusoftheCAT93HC46
can be determined by selecting the device and polling
theDOpin. SincethisdevicefeaturesAuto-Clearbefore
write, it is NOT necessary to erase a memory location
before it is written into.
will be stable after the specified time delay (tPD0 or tPD1
)
After the 1st data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word. As long as CS
is continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit; all subsequent data words will follow
without a dummy zero bit.
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self-timed
clearcycleoftheselectedmemorylocation.Theclocking
of the SK pin is not necessary after the device has
entered the self-timed mode. (Note 1.) The ready/busy
statusoftheCAT93HC46canbedeterminedbyselecting
the device and polling the DO pin. Once cleared, the
contentofaclearedlocationreturnstoalogical“1”state.
Figure 2a. Read Instruction Timing
SK
t
CSMIN
CS
STANDBY
A
A
A
0
N
N—1
DI
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
N
D
N—1
D
1
D
0
Figure 2b. Sequential Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don't Care
A
A
A
0
N
N–1
1
1
0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
7 . . .
D
0
or
or
or
D
7 . . .
D
D
D
D
7 . . .
0
7 . . .
0
Doc. No. 1008, Rev. H
5
CAT93HC46
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self-timed
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self-timed mode. The ready/busy status
of the CAT93HC46 can be determined by selecting the
device and polling the DO pin. It is not necessary for all
memory locations to be cleared before the WRAL
command is executed. Once written, the contents of all
memory locations will return to a logical “0” state.
The CAT93HC46 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once write is enabled, it will
remain enabled until power to the device is removed, or
theEWDSinstructionissent. TheEWDSinstructioncan
be used to disable all CAT93HC46 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Erase All
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
the addressed location will not be programmed or erased.
UponreceivinganERALcommand,theCS(ChipSelect)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self-timed clear cycle of
all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self-timed mode. (Note 1.) The ready/busy status of the
CAT93HC46 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory locations will return to a logical “1” state.
Figure 3. Write Instruction Timing
SK
t
CS MIN
STANDBY
STATUS
VERIFY
CS
A
A
A
0
D
N
D
0
N
N-1
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
Figure 4. Erase Instruction Timing
SK
CS
STANDBY
STATUS VERIFY
CS MIN
t
A
N
A
0
A
N-1
DI
1
1
1
t
t
HZ
SV
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1008, Rev. H
6
CAT93HC46
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS MIN
DI
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
HIGH-Z
DO
BUSY
READY
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
CS MIN
STANDBY
t
D
D
0
DI
0
0
1
0
1
N
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1008, Rev. H
7
CAT93HC46
ORDERING INFORMATION
Prefix
Device #
93HC46
Suffix
Rev H(2)
-1.8
I
S
CAT
TE13
Optional
Company ID
Temperature Range
Tape & Reel
Product
Blank = Commercial (0¡C to +70¡C)
I = Industrial (-40¡C to +85¡C)
A = Automotive (-40¡C to +105¡C)
Number
93HC46: 1K
E = Extended (-40ßC to +125ßC)
Die Revision
Package
P = PDIP
S = SOIC (JEDEC)
J = SOIC (JEDEC)
U = TSSOP
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
* available upon request
Notes:
(1) The device used in the above example is a 93HC46SI-TE13 (SOIC, Industrial Temperature,Tape & Reel).
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWH.) For additional
information, please contact your Catalyst sales office.
Doc. No. 1008, Rev. H
8
REVISION HISTORY
Date
Rev.
Reason
11/11/2003
E
Updated Features
Eliminated Commercial temperature range
Updated DC Operating Characteristics
Updated AC Characteristics
Updated Ordering Information
Updated DC Operating Characteristics
11/14/2003
7/27/2004
03/11/2005
F
G
H
Add die revision to Ordering Information
Updated Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1008
Revison:
Issue date:
Type:
H
03/11/05
Final
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