CEM0310 [CET]

Single N-Channel Enhancement Mode Field Effect Transistor; 单N沟道增强型场效应晶体管
CEM0310
型号: CEM0310
厂家: CHINO-EXCEL TECHNOLOGY    CHINO-EXCEL TECHNOLOGY
描述:

Single N-Channel Enhancement Mode Field Effect Transistor
单N沟道增强型场效应晶体管

晶体 晶体管 场效应晶体管
文件: 总4页 (文件大小:741K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CEM0310  
Single N-Channel Enhancement Mode Field Effect Transistor  
FEATURES  
100V, 2.6A, RDS(ON) = 180m@VGS = 10V.  
Super high dense cell design for extremely low RDS(ON)  
High power and current handing capability.  
Lead free product is acquired.  
.
D
8
D
D
6
D
5
Surface mount Package.  
7
SO-8  
1
2
3
4
1
S
S
S
G
ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted  
Parameter  
Symbol  
VDS  
VGS  
ID  
Limit  
Units  
Drain-Source Voltage  
100  
±20  
2.6  
V
V
A
A
Gate-Source Voltage  
Drain Current-Continuous  
Drain Current-Pulsed a  
IDM  
10.4  
Maximum Power Dissipation  
PD  
2.5  
W
C
Operating and Store Temperature Range  
TJ,Tstg  
-55 to 150  
Thermal Characteristics  
Parameter  
Symbol  
Limit  
Units  
Thermal Resistance, Junction-to-Ambient b  
RθJA  
50  
C/W  
Rev 1. 2009.Dec.  
http://www.cetsemi.com  
Details are subject to change without notice .  
1
CEM0310  
Electrical Characteristics T = 25 C unless otherwise noted  
c
Parameter  
Off Characteristics  
Symbol  
Test Condition  
Min  
Typ  
Max  
Units  
Drain-Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
Gate Body Leakage Current, Forward  
Gate Body Leakage Current, Reverse  
On Characteristics c  
BVDSS  
IDSS  
VGS = 0V, ID = 250µA  
VDS = 100V, VGS = 0V  
VGS = 20V, VDS = 0V  
VGS = -20V, VDS = 0V  
100  
V
1
µA  
nA  
nA  
IGSSF  
IGSSR  
100  
-100  
Gate Threshold Voltage  
Static Drain-Source  
VGS(th)  
RDS(on)  
VGS = VDS, ID = 250µA  
VGS = 10V, ID = 2.1A  
2
4
V
145  
180  
m  
On-Resistance  
Dynamic Characteristics d  
Input Capacitance  
Ciss  
Coss  
Crss  
385  
84  
pF  
pF  
pF  
VDS = 25V, VGS = 0V,  
f = 1.0 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Switching Characteristics d  
Turn-On Delay Time  
23  
td(on)  
tr  
td(off)  
tf  
11  
3
22  
6
ns  
ns  
VDD = 50V, ID = 1A,  
VGS = 10V, RGEN = 22Ω  
Turn-On Rise Time  
Turn-Off Delay Time  
33  
6
65  
12  
13  
ns  
Turn-Off Fall Time  
ns  
Total Gate Charge  
Qg  
9.2  
1.5  
2.7  
nC  
nC  
nC  
VDS = 80V, ID = 2.1A,  
VGS = 10V  
Gate-Source Charge  
Qgs  
Qgd  
Gate-Drain Charge  
Drain-Source Diode Characteristics and Maximun Ratings  
Drain-Source Diode Forward Current b  
Drain-Source Diode Forward Voltage c  
IS  
2.2  
1.2  
A
V
VSD  
VGS = 0V, IS = 2.6A  
Notes :  
a.Repetitive Rating : Pulse width limited by maximum junction temperature.  
b.Surface Mounted on FR4 Board, t < 10 sec.  
c.Pulse Test : Pulse Width < 300µs, Duty Cycle < 2%.  
d.Guaranteed by design, not subject to production testing.  
2
CEM0310  
10  
8
5
4
3
2
1
0
VGS=10,6,5,4.5V  
VGS=4.0  
V
6
4
VGS=3.5  
V
25 C  
2
0
TJ=125 C  
-55 C  
0
2
4
6
8
10  
0
1
2
3
4
5
VDS, Drain-to-Source Voltage (V)  
VGS, Gate-to-Source Voltage (V)  
Figure 1. Output Characteristics  
Figure 2. Transfer Characteristics  
600  
500  
400  
300  
200  
100  
0
2.7  
2.3  
1.9  
1.5  
1.1  
0.7  
0.4  
ID=2.6A  
VGS=10V  
C
iss  
C
oss  
C
rss  
0
5
10  
15  
20  
25  
-100  
-50  
0
50  
100  
150  
200  
VDS, Drain-to-Source Voltage (V)  
TJ, Junction Temperature( C)  
Figure 3. Capacitance  
Figure 4. On-Resistance Variation  
with Temperature  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
VDS=VGS  
ID=250µA  
V
GS=0V  
101  
100  
10-1  
-50 -25  
0
25 50 75 100 125 150  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
TJ, Junction Temperature( C)  
VSD, Body Diode Forward Voltage (V)  
Figure 5. Gate Threshold Variation  
with Temperature  
Figure 6. Body Diode Forward Voltage  
Variation with Source Current  
4
CEM0310  
10  
8
102  
101  
100  
10-1  
10-2  
VDS=80V  
ID=2.1A  
RDS(ON)Limit  
100ms  
1s  
6
4
10s  
DC  
2
TA=25 C  
TJ=150 C  
Single Pulse  
0
10-1  
100  
101  
102  
0
3
6
9
12  
15  
Qg, Total Gate Charge (nC)  
VDS, Drain-Source Voltage (V)  
Figure 7. Gate Charge  
Figure 8. Maximum Safe  
Operating Area  
VDD  
on  
t
toff  
d(off)  
t
r
t
d(on)  
OUT  
RL  
t
f
t
VIN  
90%  
10%  
90%  
D
OUT  
V
V
VGS  
10%  
INVERTED  
RGEN  
G
90%  
50%  
50%  
S
IN  
V
10%  
PULSE WIDTH  
Figure 10. Switching Waveforms  
Figure 9. Switching Test Circuit  
100  
D=0.5  
0.2  
10-1  
PDM  
0.1  
t1  
t2  
0.05  
0.02  
1. Rθ JA (t)=r (t) * Rθ JA  
2. Rθ JA=See Datasheet  
3. TJM-TA = P* Rθ JA (t)  
4. Duty Cycle, D=t1/t2  
Single Pulse  
10-2  
10-4  
10-3  
10-2  
10-1  
100  
101  
102  
Square Wave Pulse Duration (sec)  
Figure 11. Normalized Thermal Transient Impedance Curve  
4

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