CH7308B-TF-I_技术文档

CH7308B

Chrontel

CH7308B SDVO¹LVDS Transmitter

Features

General Description

The CH7308B is a display controller device, which accepts

digital graphics input signals, upscales, encodes, and transmits

data through an LVDS transmitter to a LCD panel. This

device accepts one channel of RGB data over three pairs of

serial data ports.

•

Single/Dual LVDS Transmitter up to 165Mpixels/s

Support resolutions up to 1600x1200 (1920x1200

with reduced blanking)

•

LVDS low jitter PLL accepts spread spectrum input

LVDS 18-bit and 24-bit outputs

2D dither engine

The LVDS Transmitter includes a low jitter PLL to generate a

high frequency serialized clock and all circuitry required to

upscale, encode, serialize and transmit data. The CH7308B

supports a maximum pixel rate of 165MP/s.

Panel protection and power sequencing

High-speed SDVO¹serial (1G~2Gbps) AC-coupled

differential RGB inputs

•

Low voltage interface support to graphics device

Programmable power management

Fully programmable through serial port

Configuration through OpCodes¹

Complete Windows driver support

Boundary scan support

The LVDS transmitter includes a panel fitting up-scaler and a

programmable dither function to support 18-bit LCD panels.

Data is encoded into commonly used formats, including those

specified in the OpenLDI and SPWG specifications.

Serialized data is outputted on three to eight differential

channels.

Offered in a 64-pin LQFP package

¹Intel Proprietary

SC_PROM

SD_PROM

SC_DDC

RESET*

AS

SPC

Serial Port/

Power

Control

SD_DDC

SPD

SDVO_STALL(+/-)

ENAVDD

ENABKL

STALL(+/-) Generator/

Power Sequencing

SDVO_CLK(+/-)

Clock Driver

XTAL

XI/FIN, XO

SDVO_R(+/-)

SDVO_G(+/-)

SDVO_B(+/-)

Data Latch,

Serial To

Parallel

SDVO

Character

Decoder

Up-Scaler

LVDS PLL

LDC[3:0],LDC*[3:0]

LL1C,LL1C*

LDC[7:4],LDC*[7:4]

LL2C,LL2C*

LVDS

Encoder

LVDS

Serializer

LVDS

Driver

Dither

FIFO

VSWING

Figure 1: Functional Block Diagram

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CH7308B

Table of Contents

1.0 Pin Assignment .............................................................................................................................3

1.1

1.2

Package Diagram.......................................................................................................................................3

Pin Description ..........................................................................................................................................4

2.0 Functional Description.................................................................................................................6

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Input Interface............................................................................................................................................6

Automatic Panel-Fitting.............................................................................................................................8

Emission Reduction Clock.........................................................................................................................9

Dithering....................................................................................................................................................9

Power Sequencing .....................................................................................................................................9

Panel Protection.......................................................................................................................................10

Command Interface .................................................................................................................................10

3.0 Register Control..........................................................................................................................13

4.0 Electrical Specifications.............................................................................................................13

4.1

4.2

4.3

4.4

4.5

4.6

4.7

Absolute Maximum Ratings ....................................................................................................................13

Recommended Operating Conditions......................................................................................................13

Electrical Characteristics .........................................................................................................................14

DC Specifications ....................................................................................................................................14

AC Specifications ....................................................................................................................................16

LVDS Output Specifications ...................................................................................................................17

LVDS Output Timing..............................................................................................................................19

5.0 Package Dimensions...................................................................................................................20

6.0 Revision History..........................................................................................................................21

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CH7308B

1.0 Pin Assignment

1.1 Package Diagram

ENABKL

ENAVDD

AVDD_PLL

RESET*

AS

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

SDVO_STALL-

SDVO_STALL+

LDC0*

LDC0

2

3

4

5

LVDD

SPC

6

LDC1*

LDC1

SPD

7

Chrontel

AGND_PLL

SD_PROM

SC_PROM

SD_DDC

SC_DDC

DGDD

8

LGND

9

LDC2*

LDC2

CH7308B

10

11

12

13

14

15

16

LVDD

LL1C*

LL1C

XI/FIN

XO

LGND

LDC3*

LDC3

DVDD

Figure 2: 64 Pin LQFP Pin Out (Top View)

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CH7308B

1.2 Pin Description

Table 1: Pin Description

Pin #

Type

Symbol

Description

4

In

RESET*

Reset* Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset

condition. When this pin is high, reset is controlled through the

serial port interface.

5

6

In

AS

Address Select (Internal pull-up)

This pin determines the serial port address of the device

(0,1,1,1,0,0,AS*,0).

In/Out

SPC

Serial Port Clock Input

This pin functions as the clock input of the serial port interface

and operates with from 0 to 2.5V. This pin requires an external

4kΩ - 9kΩ pull-up resistor to 2.5V

7

In/Out

SPD

Serial Port Data Input/Output

This pin functions as the bi-directional data pin of the serial port

interface and operates with inputs from 0 to 2.5V. Outputs are

driven from 0 to 2.5V. This pin requires an external 4kΩ - 9kΩ

pull-up resistor to 2.5V.

9

SD_PROM

SC_PROM

SD_DDC

SC_DDC

Routed Data Output to PROM

This pin functions as the bi-directional data pin of the serial port

interface for the external 5V serial EEPROM used for ADD2 card

designs. This pin requires an external 5.6K pull-up resistor to the

desired high state voltage. Leave open if unused.

Routed Clock Output to PROM

This pin functions as the clock bus of the serial port interface for

the external 5V serial EEPROM used for ADD2 card designs.

This pin requires an external 5.6K pull-up resistor to the desired

high state voltage. Leave open if unused.

10

11

12

Routed Serial Port Data Output to DDC

This pin functions as the bi-directional data pin of the serial port

to the DDC of the receiver. This pin requires an external 4–9kΩ

pull-up resistor to the desired high state voltage. Leave open if

unused.

Routed Serial Port Clock Output to DDC

This pin functions as the clock bus of the serial port to the DDC of

the receiver. This pin requires an external 4–9kΩ pull-up resistor

to the desired high state voltage. Leave open if unused.

Panel Power Enable

2

Out

In

ENAVDD

ENABKL

BSCAN

Enable LCD panel VDD (2.5V).

1

Backlight Enable

Enable backlight of LCD panel (2.5V).

63

BSCAN (internal pull-low)

This pin should be pulled low with a 10K ohm resistor. This pin

enables the boundary scan for in-circuit testing. Voltage level is 0

to DVDD.

50

64

Out

In

TEST

Internal test pin to monitor the state of the ENEXBUF (External

Buffer Enable) signal. See TB49 for details. If the ENEXBUF

signal does not need to be monitored, this pin may be left open.

Reserved

Reserved (internal pull-low)

This pin should be pulled low with a 10K ohm resistor.

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CH7308B

Pin#

Type

Symbol

Description

51, 52, 54,

55, 57, 58

In

SDVO_R+/-

SDVO_G+/-

SDVO_B+/-

SDVO Data Channel Inputs

These pins accept 3 AC-coupled differential pair of inputs from

the digital video port of a graphics controller. These 3 pairs of

inputs can be R, G, B. The differential p-p input voltage has a

maximum value of 1.2V, with a minimum value of 175mV.

Differential Clock Input associated with SDVO Data Channel

(SDVO_R+/-, SDVO_G+/-, SDVO_B+/-)

60, 61

In

SDVO_CLK+/-

These pins accept one AC-coupled differential pair of inputs from

the digital video port of a graphics controller. The range of this

clock pair is 100~200MHz. For specific pixel rates in specific

modes, this clock pair will run at an integer multiple of the pixel

rate. Refer to section 2.1.2 for details.

47, 48

Out

SDVO_STALL+/-

Stall Signal Pair associated with SDVO Data Channel

(SDVO_R+/-, SDVO_G+/-, SDVO_B+/-)

These pins output one AC-coupled differential pair of signals used

as a stall indication for a VGA controller, which is capable of

driving out SDVO_R+/-, SDVO_G+/-, SDVO_B+/- data. When

toggling between 100MHz and 200MHz, the stall indication state

is asserted (‘1’ value); when not toggling at all the state is de-

asserted (‘0’ value). The differential p-p output voltage has a

maximum value of 1.2V, with a minimum value of 175mV.

LVDS Differential Clock Channel 1

36, 37

Out

LL1C, LL1C*

17, 18

LL2C, LL2C*

LVDS Differential Clock Channel 2

33, 39, 42,

45, 34, 40,

43, 46

LDC[3:0], LDC*[3:0]

LVDS Differential Data[3:0]

20, 23, 26,

29, 21, 24,

27, 30

Out

In

LDC[7:4], LDC*[7:4]

VSWING

LVDS Differential Data [7:4]

32

LVDS Swing Control

This pin sets the swing level of the LVDS outputs. A 2.4KOhm

resistor should be connected between this pin and LGND using

short and wide traces.

14

15

In

XI/FIN

XO

Crystal Input/External Reference Input

A parallel resonant 14.31818 MHz crystal (+/-1000 ppm) should

be attached between this pin and XO. Alternatively, an external

CMOS compatible clock may be used to drive the XI/FIN input.

Crystal Output

Out

A parallel resonant 14.31818 MHz crystal (+/-1000 ppm) should

be attached between this pin and XI/FIN. However, if an external

CMOS clock is attached to XI/FIN, XO should be left open.

Digital Supply Voltage (2.5V)

16, 49

13, 31

19, 25, 38,

44

Power

DVDD

DGND

LVDD

Digital Ground

LVDS Supply Voltage (3.3V)

22, 28, 35,

41

Power

LGND

LVDS Ground

56, 62

53, 59

3

Power

AVDD

Analog Supply Voltage (2.5V)

Analog Ground

AGND

AVDD_PLL

AGND_PLL

LVDS PLL Supply Voltage (3.3V)

LVDS PLL Ground

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CH7308B

2.0 Functional Description

2.1 Input Interface

One pair of differential clock signals and three differential pairs of signals (R/G/B) form one channel data. The input

data is 10-bit serialized data. Input data operates from 1GHz~2GHz and is a 10x multiple of the clock rate

(SDVO_CLK+/-). The CH7308B first de-serializes the input into 10-bit parallel data with synchronization and

alignment then the 10-bit characters are mapped into 8-bit color data or control data (HSYNC, VSYNC, DE).

2.1.1 Interface Voltage Levels

All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level

for the signals to operate at. The minimum differential p-p input voltage is 175mVand the maximum differential p-p

input voltage is 1.2V. The minimum differential p-p output voltage is 0.247V and the maximum differential p-p

output voltage is 0.453V.

2.1.2 Input Clock and Data Timing

A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of

the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.

The clock rate must be between 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the

clock rate do not have to be equal. The clock rate is a multiple of the pixel rate (1x, 2x or 4x depending on the pixel

rate) such that the clock rate remains within the 100MHz~200MHz range. In the condition that the clock rate is

running at a multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters

(‘0001111010’) are used to stuff the data stream. The CH7308B supports the following clock rate multipliers and fill

patterns shown in Table 2.

Table 2: CH7308B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns

Pixel Rate

Clock Rate – Multiplier

Stuffing Format

Data Transfer Rate - Multiplier

CH7308B

25~50 MP/s

50~100 MP/s

100~165 MP/s

100~200 MHz – 4xPixel Rate

100~200 MHz – 2xPixel Rate

100~200 MHz – 1xPixel Rate

Data, Fill, Fill, Fill

Data, Fill

1.00~2.00 GHz – 10xClock Rate

Data

2.1.3 Synchronization

Synchronization and channel-to-channel deskewing is facilitated by the transmission of special characters during the

blank period. The CH7308B synchronizes during the initialization period and subsequently uses the blank periods to

re-synch to the data stream.

2.1.4 LVDS-Output

Table 3: Signal Mapping for Single LVDS Channel

18-bit SPWG / 18-bit OpenLDI

24-bit SPWG / 24-bit OpenLDI

LDC[0](1)

LDC[0](2)

LDC[0](3)

LDC[0](4)

LDC[0](5)

LDC[0](6)

LDC[0](7)

LDC[1](1)

LDC[1](2)

R0 / R0

R1 / R1

R2 / R2

R3 / R3

R4 / R4

R5 / R5

G0 / G0

G1 / G1

G2 / G2

R0 / R2

R1 / R3

R2 / R4

R3 / R5

R4 / R6

R5 / R7

G0 / G2

G1 / G3

G2 / G4

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CH7308B

LDC[1](3)

LDC[1](4)

LDC[1](5)

LDC[1](6)

LDC[1](7)

LDC[2](1)

LDC[2](2)

LDC[2](3)

LDC[2](4)

LDC[2](5)

LDC[2](6)

LDC[2](7)

LDC[3](1)

LDC[3](2)

LDC[3](3)

LDC[3](4)

LDC[3](5)

LDC[3](6)

LDC[3](7)

G3 / G3

G4 / G4

G5 / G5

G3 / G5

G4 / G6

G5 / G7

B0 / B2

B1 / B3

B2 / B4

B3 / B5

B4 / B6

B5 / B7

B0 / B0

B1 / B1

B2 / B2

B3 / B3

B4 / B4

B5 / B5

HSYNC / HSYNC

VSYNC / VSYNC

DE / DE

HSYNC / HSYNC

VSYNC / VSYNC

DE / DE

R6 / R0

R7 / R1

G6 / G0

G7 / G1

B6 / B0

B7 / B1

RES / RES

Table 4: Signal Mapping for Dual LVDS Channel

18-bit SPWG / 18-bit OpenLDI

24-bit SPWG / 24-bit OpenLDI

Ro0 / Ro2

Ro1 / Ro3

LDC[0](1)

LDC[0](2)

LDC[0](3)

LDC[0](4)

LDC[0](5)

LDC[0](6)

LDC[0](7)

LDC[1](1)

LDC[1](2)

LDC[1](3)

LDC[1](4)

LDC[1](5)

LDC[1](6)

LDC[1](7)

LDC[2](1)

LDC[2](2)

LDC[2](3)

LDC[2](4)

LDC[2](5)

LDC[2](6)

LDC[2](7)

LDC[3](1)

LDC[3](2)

LDC[3](3)

LDC[3](4)

LDC[3](5)

LDC[3](6)

LDC[3](7)

LDC[4](1)

LDC[4](2)

LDC[4](3)

LDC[4](4)

LDC[4](5)

Ro0 / Ro0

Ro1 / Ro1

Ro2 / Ro2

Ro2 / Ro4

Ro3 / Ro5

Ro3 / Ro3

Ro4 / Ro4

Ro5 / Ro5

Ro4 / Ro6

Ro5 / Ro7

Go0 / Ro2

Go0 / Go0

Go1 / Go1

Go2 / Go2

Go3 / Go3

Go4 / Go4

Go5 / Go5

Bo0 / Bo0

Bo1 / Bo1

Bo2 / Bo2

Bo3 / Bo3

Bo4 / Bo4

Bo5 / Bo5

HSYNC / HSYNC

VSYNC / VSYNC

DE / DE

Go1 / Ro3

Go2 / Go4

Go3 / Go5

Go4 / Go6

Go5 / Go7

Bo0 / Bo2

Bo1 / Bo3

Bo2 / Bo4

Bo3 / Bo5

Bo4 / Bo6

Bo5 / Bo7

HSYNC / HSYNC

VSYNC / VSYNC

DE / DE

Ro6 / Ro0

Ro7 / Ro1

Go6 / Ro0

Go7 / Go1

Bo6 / Bo0

Bo7 / Bo1

RES / RES

Re0 / Re2

Re1 / Re3

Re0 / Re0

Re1 / Re1

Re2 / Re2

Re3 / Re3

Re4 / Re4

Re2 / Re4

Re3 / Re5

Re4 / Re6

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CH7308B

LDC[4](6)

LDC[4](7)

LDC[5](1)

LDC[5](2)

LDC[5](3)

LDC[5](4)

LDC[5](5)

LDC[5](6)

LDC[5](7)

LDC[6](1)

LDC[6](2)

LDC[6](3)

LDC[6](4)

LDC[6](5)

LDC[6](6)

LDC[6](7)

LDC[7](1)

LDC[7](2)

LDC[7](3)

LDC[7](4)

LDC[7](5)

LDC[7](6)

LDC[7](7)

Re5 / Re5

Ge0 / Ge0

Ge1 / Ge1

Re5 / Re7

Ge0 / Ge2

Ge1 / Ge3

Ge2 / Ge4

Ge3 / Ge5

Ge4 / Ge6

Ge5 / Ge7

Be0 / Be2

Be1 / Be3

Be2 / Be4

Be3 / Be5

Be4 / Be6

Be5 / Be7

HSYNC / LCTLE

VSYNC / LCTLF

DE / LA6RL

Re6 / Re0

Re7 / Re1

Ge6 / Re0

Ge7 / Re1

Be6 / Be0

Be7 / Be1

RES

Ge2 / Ge2

Ge3 / Ge3

Ge4 / Ge4

Ge5 / Ge5

Be0 / Be0

Be1 / Be1

Be2 / Be2

Be3 / Be3

Be4 / Be4

Be5 / Be5

HSYNC / LCTLE

VSYNC / LCTLF

DE / LA6RL

2.2 Automatic Panel-Fitting

Serialized input data, sync and clock signals are input to the CH7308B from the graphics controller’s serial digital

video output port. Input is through three differential data pairs and one differential clock pair. The data rate is in the

range of 1.0~2.0GHz. The clock rate, independent from the pixel rate, is 1/10 of the data rate, resulting in the range

of 100M~200MHz. Horizontal sync and vertical sync information are embedded in the data stream.

Given the panel information (output timing information), the CH7308B can automatically fit the output timing to the

panel. The up-scaler in the CH7308B supports but is not limited to the following LVDS panel sizes:

Table 5: Popular Panel Sizes

WUXGA

UXGA

1920x1200 (Reduced Blanking)

1600x1200

1680x1050

1400x1050

1360x1024

1440x900

Wide SXGA+

SXGA+

WSXGA

SXGA

1280x1024

1280x960

1366x768

WXGA

XGA

1024x768

1024x600

800x600

SVGA

The CH7308B is capable of up-scaling images containing 1400 active horizontal pixels or less to the native

resolution of the supported LVDS panel. For resolutions containing more than 1400 horizontal pixels, no up-scaling

will be done. The up-scaler periodically sends a pair of SDVO_STALL(+/-) signals to the graphics controller to halt

the transmission of one line of active video data. When the SDVO_STALL(+/-) signals toggle between 100MHz

and 200MHz, this is interpreted as asking for next line of video data to be “stalled”; not toggling at all is considered

as asking for the next line of video data to be sent. The Up-scaler performs 2D interpolation of the graphics input

data and does not change the pixel rate between the input and the output. The 2D interpolation consists of

programmable non-linear functions. The maximum pixel rate supported by the Up-scaler is 200MP/s.

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CH7308B

2.3 Emission Reduction Clock

LVDS output can support a 2.5% spreading in the output clock to reduce EMI emissions. The frequency and the

amplitude of the spreading triangle waveform can be programmed via opcode commands.

2.4 Dithering

The dither engine in the CH7308B converts 24-bit per pixel RGB data to 18-bit per pixel RGB data before sending

the data to the LVDS encoder. The maximum pixel rate supported is 165MP/s. This feature supports 18-bit LVDS

panels only.

2.5 Power Sequencing

The CH7308B conforms to the SPWG requirements on power sequencing. The timing specification shown in figure

4 is a superset of the requirements dictated by the SPWG specification. The timing parameters can be programmed

to different values via opcode commands to suit the timing requirements defined by the particular panel

specifications to be used.

T1 T2

T3 T4

T5

ENAVDD

ENEXBUF

ENABKL

LVDS Clocks

LVDS Data

Valid Clock

Valid Data

Tristate or GND

Figure 3: Power Sequencing

Table 6: Power Sequencing

Range

Increment

1 ms

1ms

T1

T2

T3

T4

T5

1-1023 ms

1ms

1 ms

1ms

The power-on sequence begins when the LVDS software registers are set properly via opcode commands and the

internal PLL lock detection circuit, the internal Sync detection circuit, and the XCLK detection circuit (see section

2.6) indicate that HSYNC, VSYNC and XCLK are stable. The power-off sequence begins when any of the

detection circuits indicates instability in the timing signals (see section 2.6), or through opcode programming. Once

the power-off sequence starts, the internal state machine will complete the power-off sequence and power-on

sequence is allowed only after T5 is passed.

To verify the T1 – T5 LVDS Panel Power Sequencing, please see TB49 for more details.

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CH7308B

2.6 Panel Protection

Damage to the LCD panel may occur if either HSYNC or VSYNC signals are absent from the LVDS link. This

situation can happen when there is a catastrophic failure in the PC or the graphics system. The CH7308B is designed

to prevent damage to the panel under such a failure. If the system fails, the CH7308B does not expect any software

instruction from the graphics controller to power down the panel. Detection circuits are used to monitor the three

timing signals – HSYNC, VSYNC and XCLK. If any one, combination of, or all of these signals becomes unstable

or missing, the CH7308B will commence Power Down Sequencing.

The power up sequence can occur only if there are no missing HSYNC and VSYNC, the input clock is available, the

PLL clock is stable and the SetActiveOutput opcode is called. The power down sequence is initiated if one of those

conditions fails. The panel protection circuitry is comprised of the PLL Lock Detection block, which detects an

unstable clock from the LVDS PLL, the SYNC Detection block, which detects missing inputs HSYNC and

VSYNC, and the Clock Detection block, which detects missing input CLOCK.

The SYNC Detection block consists of counters to count HSYNC and VSYNC pulses. One counter is used to count

the number of HSYNC pulses per frame over 3 frames. The end counts for all 3 frames must be equal to enable the

power up sequence. In addition, the SYNC Detection block checks for the presence of VSYNC and HSYNC. If

VSYNC is missing for 2 frames or if HSYNC is missing for 32us, the power up sequence is disabled. Conversely, if

the panel has been enabled and the number of HSYNC pulses per frame is different over 3 frames, VSYNC is

missing for 2 frames, or HSYNC is missing for 32us, the CH7308B will go into a power down sequence.

The PLL Lock Detection, SYNC Detection and Clock Detection blocks can be defeated independently. Opcode

commands are supported for these features. The power up sequence can also occur if the panel protection circuitry is

defeated.

2.7 Command Interface

Communication is through a two-wire path, control clock (SPC) and data (SPD). The CH7308B accepts incoming

control clock and data from a graphics controller, and is capable of redirecting that data stream to the ADD2 card

PROM, DDC, or CH7308B internal registers. The control bus is able to run up to 1MHz.

Internal

Device

Registers

control

the

observer

switch

on/off

Control Bus

from VGA

DDC

default

position

PROM

Figure 4: Control Bus Switch

Upon reset, the default state of the control bus direction switch is to redirect the control bus interface to the ADD2

PROM. At this stage, the CH7308B observes the Control bus traffic. If the observing logic sees a control bus

transaction destined for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and

switches to internal registers. In the condition that traffic is to the internal registers, an opcode command is used to

set the redirection circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal

registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus.

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CH7308B

2.7.1 NAND Tree Test

CH7308B provides “NAND TREE Testing” to verify IO cell functions at the PC board level. This test will check

the interconnection between the chip’s I/O and the printed circuit board for faults (soldering, bent leads, open

printed circuit board traces, etc.). The NAND tree test is a simple serial logic which turns all IO cell signals to input

mode, connects all inputs with NAND gates as shown in Figure 6 and switches each signal to high or low according

to the sequence in Table 7. The test results are then passed out of pin 48 (SDVO_STALL-). This test is enabled

when the BSCAN pin (pin 63) is set to “1”.

Figure 5: NAND Tree Connection

Testing Sequence

Set BSCAN = 1; (internal weak pull-low)

Set all signals listed in Table 7 to 1.

Set all signals listed in Table 7 to 0, toggle one by one with a suggested time period of 200 ns.

Pin 48 will change its value each time an input value changed.

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CHRONTEL

CH7308B

Table 7: Signal Order in the NAND Tree Testing

Order

Pin Name

LQFP Pin

1

ENABKL

ENAVDD

RESET*

AS

1

2

3

4

5

SPC

SPD

6

7

SD_PROM

SC_PROM

SD_DDC

SC_DDC

XI

9

8

10

11

12

14

15

17

18

20

21

23

24

26

27

29

30

33

34

36

37

39

40

42

43

45

46

47

48

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

XO

LL2C

LL2C*

LDC7

LDC7*

LDC6

LDC6*

LDC5

LDC5*

LDC4

LDC4*

LDC3

LDC3*

LL1C

LL1C*

LDC2

LDC2*

LDC1

LDC1*

LDC0

LDC0*

SDVOB_STALL+

SDVOB_STALL-

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CHRONTEL

CH7308B

3.0 Register Control

The CH7308B is controlled by Intel opcodes through the serial port. The serial bus uses only the SPC clock to latch

data into registers, and does not use any internally generated clocks so that the device can be written to in all power

down modes. The device will retain all register values during power down modes.

For details regarding Intel^®SDVO opcodes, please contact Intel^®.

4.0 Electrical Specifications

4.1 Absolute Maximum Ratings

Symbol

Description

Min

Typ

Max

Units

All 2.5V power supplies relative to GND

All 3.3V power supplies relative to GND

-0.5

3.5

5.0

V

T

Analog output short circuit duration

Storage temperature

Indefinite

Sec

°C

SC

T

-65

150

260

245

225

STOR

T

Junction temperature

J

T

Vapor phase soldering (5 seconds)

Vapor phase soldering (11 seconds)

Vapor phase soldering (60 seconds)

VPS1

T

VPS2

T

VPS3

Note:

1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions above those

indicated under the normal operating condition of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor

phase soldering apply to all standard and lead free parts.

2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive

device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce a

destructive latchup.

4.2 Recommended Operating Conditions

Symbol

Description

Min

2.375

3.100

2.375

3.100

2.375

Typ

2.5

3.3

2.5

3.3

2.5

Max

2.625

3.500

2.625

3.500

2.625

Units

AVDD

Analog Power Supply Voltage

Analog PLL Power Supply Voltage

Digital Power Supply Voltage

LVDS Power Supply

V

AVDD_PLL

DVDD

LVDD

VDD33

VDD25

Generic for all 3.3V supplies

Generic for all 2.5V supplies

Ambient operating temperature (Commercial / Automotive

Grade 4)

0

70

85

°C

T

AMB

Ambient operating temperature (Industrial / Automotive

Grade 3)

-40

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CHRONTEL

CH7308B

4.3 Electrical Characteristics

(Operating Conditions: T_A= 0°C to 70°C for parts qualified as Commercial / Automotive Grade 4, T_A= –40°C to

85°C for parts qualified as Industrial / Automotive Grade 3, VDD25 =2.5V 5%, VDD33=3.3V 5%)

Symbol

Description

Total VDD25 supply current (2.5V supplies)

(no upscaler)

Total VDD33 supply current (3.3V supply)

(no upscaler)

Min

Typ

Max

Units

I

VDD25

VDD33

VDD25UP

VDD33UP

PD

170

200

mA

70

270

70

85

340

85

mA

uA

Total VDD25 supply current (2.5V supplies)

(with upscaler enabled)

Total VDD33 supply current (3.3V supply)

(with upscaler enabled)

Total Power Down Current (all supplies)

30

4.4 DC Specifications

Symbol

Description

Test Condition

Min

Typ

Max

Unit

SDVO Receiver Differential

Input Peak to Peak Voltage

0.175

1.200

V

V_RX-DIFFp-p

V_RX-DIFFp-p= 2 *

V_RX-D+- V_RX-D-



SDVO Receiver DC

Differential Input Impedance

80

100

50

120

60

Ω

Z_RX-DIFF-DC

SDVO Receiver DC Common

Mode Input Impedance

40

Z_RX-COM-DC

SDVO Receiver Initial DC

Common Mode Input

Impedance

Impedance allowed

when receiver

terminations are first

turned on

5

50

60

Z_RX-COM-

INITIAL-DC

SDVO Stall Differential Output V_{STALL-DIFFp-p}= 2 *

Peak to Peak Voltage

0.8

1.200

0.4

V

V_{STALL-DIFFp-p}

V_STALL-D+- V_STALL-D-



1

SPD (serial port data) Output

Low Voltage

V_SDOL

I

OL

= 2.0 mA

2

Serial Port (SPC, SPD) Input

High Voltage

2.0

GND-0.5

0.25

VDD25+

0.5

V_SPIH

2

Serial Port (SPC, SPD) Input

Low Voltage

0.4

V_SPIL

Hysteresis of Serial Port

Inputs

V

V_HYS

V_DDCIH

DDC Serial Port

VDD5 +

0.5

Input High Voltage

4.0

V_DDCIL

DDC Serial Port

V

Input Low Voltage

GND-0.5

4.0

0.4

V_PROMIH

PROM Serial Port

Input High Voltage

VDD5 +

0.5

V_PROMIL

PROM Serial Port

Input Low Voltage

V

GND-0.5

0.4

3

SPD (serial port data) Output

Low Voltage from SD_DDC

(or SD_EPROM)

Input is V_INLat

SD_DDC or

SD_EPROM.

0.9*V_INL

0.25

+

V_SD__DDCOL

4.0KΩ pull-up to 2.5V.

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CH7308B

Symbol

Description

Test Condition

Min

Typ

Max

Unit

4

SC_DDC and SD_DDC

Output Low Voltage

Input is V_INLat SPC

and SPD.

0.933*V_INL

+ 0.35

V

V_DDCOL

5.6KΩ pull-up to 5.0V.

5

SC_EPROM and

SD_EPROM Output Low

Voltage

Input is V_INLat SPC

and SPD.

0.933*V_INL

+ 0.35

V

V_EPROMOL

5.6KΩ pull-up to 5.0V.

AS

Input High Voltage

2.0

VDD25 +

0.5

V

V_ASIH

V_ASIL

AS

GND-0.5

0.5

Input Low Voltage

AS Pull-Up Current

V_IN= 0V

10

40

uA

V

I_ASPU

RESET*

Input High Voltage

2.7

VDD33 +

0.5

V_RESETIH

RESET*

Input Low Voltage

GND-0.5

0.5

V

V_RESETIL

RESET* Pull-Up Current

V_IN= 0V

10

40

uA

V

I_RESETPU

V_TESTIH

BSCAN

Input High Voltage

2.0

VDD25 +

0.5

BSCAN

Input Low Voltage

GND-0.5

0.5

V

V_TESTIL

BSCAN

Pull-Down Current

V_IN= 2.5V

10

40

uA

V

I_TESTPD

V_XIIH

XI (for clock input)

Input High Voltage

2.6

VDD33 +

0.5

XI (for clock input)

Input Low Voltage

GND-0.5

VDD-0.2

0.6

V

V_XIIL

ENAVDD, ENABKL

Output High Voltage

I_OH= -6.5mA

I_OL= 9.0mA

V_MISCAOH

V_MISCAOL

ENAVDD, ENABKL

Output Low Voltage

0.2

Notes:

1.

V

_SDOLis the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM.

2. V_SPIHand V_SPILare the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate

requirements may exist for transmission to the DDC and EEPROM.

3. V_{SD_DDCOL}is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is V_INL. Maximum output

voltage has been calculated with the worst case of pull-up of 4.0kΩ to 2.5V on SPD.

4. V_DDCOLis the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is V_INL. Maximum output

voltage has been calculated with 5.6k pull-up to 3.3V on SC_DDC and SD_DDC.

5. V_EPROMOLis the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is V_INL

Maximum output voltage has been calculated with 5.6kΩ pull-up to 5V on SC_EPROM and SD_EPROM.

.

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CHRONTEL

CH7308B

4.5 AC Specifications

Symbol

Description

Test Condition

Min

Typ.

Typ

Max

Unit

UI_DATA

SDVO Receiver Unit Interval

for Data Channels

1/[Data

Transfer

Rate]

Typ.

ps

– 300ppm

+ 300ppm

f_{SDVOB_CLK}

f_PIXEL

SDVO CLK Input Frequency

100

25

200

MHz

SDVO Receiver Pixel

frequency

f_SYMBOL

SDVO Receiver Symbol

frequency

1

2

GHz

UI

t_RX-EYE

SDVO Receiver Minimum Eye

Width

0.4

t_{RX-EYE-JITTER}

SDVO Receiver Max. time

between jitter median and

max. deviation from median

0.3

UI

V_RX-CM-ACp

SDVO Receiver AC Peak

150

mV

Common Mode Input Voltage

RL_RX-DIFF

RL_RX-CM

t_SKEW

Differential Return Loss

50MHz – 1.25GHz

Across all lanes

10

6

dB

ns

Common Mode Return Loss

SDVO Receiver Total Lane to

Lane Skew of Inputs

2

XI

C_XI

15

pF

Input Capacitance

XI

f_{TOL XI}

-1000

+1000

ppm

Input Clock Frequency

Tolerance (when crystal not

used)

XI

DC_XI

45

55

%

Input Clock Duty Cycle (when

crystal not used)

T_SPR

SPC, SPD Rise Time

(20% - 80%)

Standard mode 100k

Fast mode 400k

1000

300

150

300

150

300

ns

1M running speed

Standard mode 100k

Fast mode 400k

T_SPF

SPC, SPD Fall Time

(20% - 80%)

1M running speed

Fast mode 400K

T_PROMR

T_PROMF

T_DDCR

T_DDCF

SC_PROM, SD_PROM Rise

Time (20% - 80%)

SC_PROM, SD_PROM Rise

Time (20% - 80%)

Fast mode 400K

300

1000

300

ns

SC_DDC, SD_DDC Rise

Time (20% - 80%)

Standard mode 100k

SC_DDC, SD_DDC Fall

Time (20% - 80%)

16

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CH7308B

Symbol

Description

Test Condition

Min

Typ

Max

Unit

1

T_DDCR-DELAY

SC_DDC, SD_DDC Rise

Time Delay (50%)

Standard mode 100k

0

ns

1

T_DDCF-DELAY

SC_DDC, SD_DDC Fall

Time Delay (50%)

Standard mode 100k

3

ns

Notes:

1. Refers to the figure below, the delay refers to the time pass through the internal switches.

3.3V typ.

2.5V typ.

R=5K

To SPC/SPD pin

To DDC pin

Figure 6: DDC – SPC/SPD Circuit

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CHRONTEL

CH7308B

4.6 LVDS Output Specifications

The LVDS specifications meet the requirements of ANSI/EIA/TIA-644. Refer to Figure

7 for definitions of parameters.

Symbol

Description

Test Condition

Min

Typ

Max

Unit

|V_t|

Steady State Differential

100Ω differential load

247

453

mV

Output Magnitude for logic 1

| V_t*|

Steady State Differential

100Ω differential load

247

453

50

mV

Output Magnitude for logic 0

| V_t| - | V_t*|

Steady State Magnitude of

Differential between Logic 1

and 0 Outputs

|V_OS

|

Steady State Magnitude of

Offset Voltage for Logic 1

Measured at

1.125

1.375

50

V

centertap of two 50Ω

resistors connected

between outputs

|V_OS*|

Steady State Magnitude of

Offset Voltage for Logic 0

Measured at

centertap of two 50Ω

resistors connected

between outputs

|Vos|-|Vos*|

Steady State Magnitude of

Offset Difference between

Logic States

Measured at

mV

centertap of two 50Ω

resistors connected

between outputs

1

f_LLC

LVDS Output Clock

Frequency

25

108

MHz

ns

1

t_UI

LVDS data unit time interval

25MHz <

1.3

5.7

f_LLC<108MHz

t_r

LVDS data rise time

t_UI> 5ns

100Ω and 5pF

differential load

0.3*t_UI

1.5

ns

20%->80% Vswing

1.3ns<t_UI<5ns

LVDS data fall time

T_UI> 5ns

t_f

100Ω and 5pF

differential load

0.3*t_UI

1.5

ns

80%->20% Vswing

1.3ns<t_UI<5ns

Vring

Voltage ringing after transition 100Ω and 5pF

differential load

20%

Vswing

Note 1: Corresponds to maximum pixel rate f_XCLKfor single channel operation. Dual channel operation is required for pixel rates

greater than 108MHz.

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CH7308B

4.7 LVDS Output Timing

V_ring

+/-20% V_swing

0.8 V_swing

+V_t

V_swing

0V Differential

-V_t

0.2 V_swing

t_r

t_f

t_ui

Figure 7: AC Timing for LVDS Outputs

Table 8: AC Timing for LVDS Outputs

Symbol

Parameter

Min

Typ

Max

Steady State Differential Output Magnitude

| V_t|

See section 4.6

| V_t| + | V_t*|

Voltage Difference between the two Steady State Values of Output

V_SWING

Unit time interval

Rise time

t_Ui

t_r

See section 4.6

t_f

Fall time

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CHRONTEL

CH7308B

5.0 Package Dimensions

A

B

1X 4

I

1

A

B

H

3X

5

C

D

J

LEAD

CO-PLANARITY

E

.004 “

F

G

Figure 8: 64 Pin LQFP Package

Table of Dimensions

No. of Leads

SYMBOL

64 (10 X 10 mm)

A

B

C

D

E

F

G

H

I

J

Milli-

meters

MIN

11.80

-

0.17

0.27

1.35

1.45

0.05

0.15

0.45

0.75

0.09

0.20

0°

7°

0.50

1.00

MAX

12.20 10.00

Notes:

1. Conforms to JEDEC standard JESD-30 MS-026D.

2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.

3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.

4. (1X) Corner in quadrant with Pin1 identifier (dot) is always chamfered. Exact shape of chamfer is optional.

5. (3X) Corners in quadrants without Pin1 identifier (dot) may be square or chamfered. Exact shape of corner

or chamfer is optional.

20

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CH7308B

6.0 Revision History

Table 9: Revisions

Rev. #

1.0

1.1

Date

Section

Description

11/23/04

12/20/04

All

2.2

Version 1.0

Updated panel-fitting scaler information.

Updated T_VPS– Vapor phase soldering information.

Lead Free tape and reel part number added.

Note 1 updated.

4.1

1.2

01/05/05

Ordering Information

4.1

1.3

1.4

01/27/05

02/02/05

4.4

1.1, 1.2

2.5

Added V_MISCAOHand V_MISCAOLDC Specification data.

Added TEST pin (pin50) and description.

Updated Figure 4 and added reference to TB49.

Corrected note to which section to refer to

Added Wide SXGA+, 1680 x 1050, to Table 5

Change descriptions for pin 11, 12, 14, 15, 60, 61

Table 8

2.2

1.5

02/07/05

08/08/05

1.2

2.6

Replace “PANEN set to 1” with “SetActiveOutput is called”.

Change spec. values.

4.4, 4.5, 4.6, 4.7

4.4

4.5

Changed conditions and value for V_DDCOL

Changed definition of f_PIXELand value for RL_RX-DIFF

Changed parameters f_LLC, t_UI, t_R, t_F.

4.6

All

1.61

Changed the maximum pixel rate to 140MP/s

Changed the maximum upscale resolution to 1600x900

Updated the table to reflect the new maximum pixel rate of 140MP/s

Removed panel sizes no longer supported.

Features, 2.2

Table 2

2.2

Ordering Information

Added a footnote stating the current revision of the CH7308A is

revision D and marked as XUD

The last sentence of the 2^ndparagraph was edited to avoid confusion in

what is the maximum pixel rate per channel.

General Description

1.7

1.8

10/12/05

12/20/05

Ordering information

4.4, 4.5

Added Green parts into the ordering information.

Added serial interface AC and DC Electrical Specification information.

Sentence mentioning supported pixel rates for dual panel LVDS panels

(100MP/s to 140MP/s).

General Description

3.0 Register Control

Changed the first sentence to clarify that the CH7308A is controlled by

use of Intel Opcodes instead of register reads/writes.

Modified the datasheet to include the CH7308B.

Added CH7308B related information in the features section and the

second paragraph of the General Description section.

Added CH7308B ordering information.

2.0

2.1

01/11/06

03/13/08

All text and figures

Features and General

Description

Ordering Information

Features

Added 1600x1200 and 1920x1200 reduced blanking resolution

support.

Pin Description

Table 5

Figure 3

Pin 63 and Pin 64 are changed to “open”

Added 1920x1200 resolution reduced blanking to Table 5.

Added LVDS Clock and LVDS Data to Figure 3.

Updated DC Specifications.

2.2

2.3

2.4

2.41

3.0

08/05/08

09/22/08

12/02/08

03/30/08

05/10/11

4.4

4.2, 4.3.

Updated operating temperature.

Updated description for Pin 63.

1.2 Table 1

4.1, 4.2

All

Update Ambient operating temperature to -40°C to +85°C.

Remove CH7308A

3.1

05/08/12

1.2, 4.1, 4.2, 4.3, 5.0

Update ambient operating temperature into Commercial /

Automotive Grade 4 and Industrial / Automotive Grade 3. Unify

the description of pin 63 and pin 64. Modify some “Absolute

Maximum Ratings”. Add some notes for “Package

Dimensions”.

3.2

3.3

11/26/12

1/07/14

1.2

Pin 63 and pin 64 should be connected to ground through a 10K

resistor.

1.2, 4.1, 4.2

Pins 47/48 (SDVO_STALL+/-) and 60/61 (SDVO_CLK+/-)

should be AC-coupled. Move T_AMBfrom 4.1 to 4.2.

201-0000-064

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1/07/2014

21

CHRONTEL

CH7308B

Disclaimer

This document provides technical information for the user. Chrontel reserves the right to make changes at any time

without notice to improve and supply the best possible product and is not responsible and does not assume any

liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use

of our products and assume no liability for errors contained in this document. The customer should make sure that

they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the

products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not

infringe upon or assist others to infringe upon such rights.

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT

SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF

Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used

as directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Number of

Pins

Temperature Grade

Part Number

CH7308B-TF

Package Type

Voltage Supply

2.5V, 3.3V

Lead Free -

LQFP

Lead Free -

Commercial /

Automotive Grade 4

64

Industrial / Automotive

Grade 3

CH7308B-TF-I

CH7308B-TF-TR

CH7308B-TF-I-TR

64

LQFP

Lead Free - Tape

and Reel LQFP

Lead Free - Tape

and Reel LQFP

Commercial /

Automotive Grade 4

Industrial / Automotive

Grade 3

Chrontel

2210 O’Toole Avenue, Suite 100,

San Jose, CA 95131-1326

Tel: (408) 383-9328

Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

Printed in the U.S.A.

22

201-0000-064

Rev. 3.3,

1/07/2014


型号：	CH7308B-TF-I
厂家：	CHRONTEL, INC
描述：	Consumer Circuit, CMOS, PQFP64, LEAD FREE, MS-026D, LQFP-64 商用集成电路
文件：	总22页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CH7308B-TF-I [CHRONTEL]

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