CH7312A-DE-TR [CHRONTEL]

Micro Peripheral IC;


型号：	CH7312A-DE-TR
厂家：	CHRONTEL, INC
描述：	Micro Peripheral IC
文件：	总6页 (文件大小：137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CH7312

Chrontel

Preliminary Brief Datasheet

CH7312 DVI Transmitter

Features

General Description

•

Digital Visual Interface (DVI) Transmitter up to

165M pixels/second

The CH7312 is a Display Controller device, which accepts a

digital graphics input signal, encodes and transmits data

•

High-bandwidth Digital Content Protection (HDCP) through a DVI link (DFP can also be supported) with optional

support

DVI low jitter PLL

HDCP support. The device accepts one channel of RGB data

over three pairs of serial data ports.

•

DVI hot plug detection

High-speed SDVO^◊(1G~2Gbps) AC-coupled serial

differential RGB inputs

The DVI processor includes a low jitter PLL for

generation of the high frequency serialized clock, and all

circuitry required to encode, serialize and transmit the

data. The CH7312 is able to drive a DFP display at a

pixel rate of up to 165MHz, supporting UXGA

(1600x1200) resolution displays.

•

Programmable power management

Fully programmable through serial port

Configuration through Intel^®Opcodes^◊

Complete Windows and DOS driver support

Offered in a 48-pin LQFP package

Boundary scan support

The CH7312 has the ability to become a HDCP rev1.1

Down-stream compliant DVI transmitter by using an

external HDCP key containing the proper device keys

which can be obtained from Chrontel, Inc.

^◊Intel® Proprietary.

SDVO _R(+,-)

SDVO _G(+,-)

SDVO _B(+,-)

10bit-8bit

decoder

Data Latch ,

Serial to Parallel

Interrept

Generation

SDVO_INT(+/-)

H,V,DE

HPDET

SDVO _Clk(+,-)

Clock Driver

Test Block

HDCP

Encrypter

PROM 2

PROM 1

TLC, TLC*

DVI PLL

TDC0, TDC0*

TDC1, TDC1*

TDC2, TDC2*

DVI

Encoder

DVI

FIFO

BSCAN

Serializer Driver

VSWING

Reset & Control

RESET *

SC_PROM

SD_PROM

SC_DDC

SD_DDC

SPC

SPD

Serial Port

Control

Figure 1: Functional Block Diagram

201-0000-071

Rev. 0.41, 2/8/2005

CHRONTEL

CH7312

1.0 PIN-OUT

1.1 Package Diagram

AVDD_PLL

AVDD

RESET*

BSCAN

SPC

SDVO_INT-

SDVO_INT+

SPD

CHRONTEL

CH7312

AGND_PLL

DGND

31 AGND

DGND

SD_PROM

SC_PROM

SD_DDC

SC_DDC

DVDD

HPDET

28 DVDD

PROM2

PROM1

VSWING

Figure 2: 48-Pin LQFP Pin Out

201-0000-071

Rev. 0.41,

2/8/2005

CHRONTEL

CH7312

1.2 Pin Description

Table 1: Pin Description

Pin #

Type

Symbol

RESET*

Description

Reset* Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset condition. When

this pin is high, reset is controlled through the serial port register.

Address Select (Internal pull-up)

This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0).

When AS is low the address is 72h, when high the address is 70h.

SPC

Serial Port Clock Input

This pin functions as the clock input of the serial port and operates with inputs

from 0 to 2.5V. This pin requires an external 4kΩ - 9kΩ pull up resistor to

2.5V.

In/Out

Out

SPD

Serial Port Data Input / Output

This pin functions as the bi-directional data pin of the serial port and operates

with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin

requires an external 4kΩ - 9 kΩ pull up resistor to 2.5V.

SD_PROM

SC_PROM

SD_DDC

SC_DDC

TLC*, TLC

Routed Data to PROM

This pin functions as the bi-directional data pin of the serial port for PROM on

ADD2 card. This pin will require a pull-up resistor to the desired high state

voltage. Leave open if unused.

Routed Clock Output to PROM

This pin functions as the clock bus of the serial port to PROM on ADD2 card.

This pin will require a pull-up resistor to the desired high state voltage. Leave

open if unused.

In/Out

Out

Routed Serial Port Data to DDC

This pin functions as the bi-directional data pin of the serial port to DDC

receiver. This pin will require a pull-up resistor to the desired high state

voltage. Leave open if unused.

Routed Serial Port Clock Output to DDC

This pin functions as the clock bus of the serial port to DDC receiver. This pin

will require a pull-up resistor to the desired high state voltage. Leave open if

unused.

13, 14

DVI Clock Outputs

These pins provide the differential clock output for the DVI interface

corresponding to data on the TDC[2:0] outputs.

16,17

19, 20

22, 23

Out

TDC0*, TDC0

TDC1*, TDC1

TDC2*, TDC2

VSWING

DVI Data Channel 0 Outputs

These pins provide the DVI differential outputs for data channel 0 (blue).

DVI Data Channel 1 Outputs

These pins provide the DVI differential outputs for data channel 1 (green).

DVI Data Channel 2 Outputs

These pins provide the DVI differential outputs for data channel 2 (red).

DVI Swing Control

This pin sets the swing level of the DVI outputs. A 1.2K ohm resistor should

be connected between this pin and TGND using short and wide traces.

In / Out PROM1

PROM Interface 1

This pin functions as an interface to the external EEPROM. Contact Chrontel

Applications for detailed instructions.

201-0000-071

Rev. 0.41, 2/8/2005

CHRONTEL

CH7312

Table 1: Pin Description (contd.)

Pin #

Type

Out

Symbol

PROM2

Description

PROM Interface 2

This pin functions as an interface to the external EEPROM. Contact Chrontel

Applications for detailed instructions.

Hot Plug Detect (internal pull-down)

This input pin determines whether the DVI output driver is connected to a DVI

monitor. When terminated, the monitor is required to apply a voltage greater

than 2.4 volts. Changes on the status of this pin will be relayed to the graphics

controller via the SDVO_INT+/- pins, where toggling between 100MHz and

200MHz is considered an assertion (‘1’ value), not toggling at all is considered

a de-assertion (‘0’ value).

HPDET

Interrupt Output Pair associated with SDVO Data Channel

This pair is used as a hot plug attach/detach notification to VGA controller of a

monitor driven by data SDVO_R+/-, SDVO_G+/-, SDVO_B+/-.

Toggling between 100MHz and 200MHz on this pair is considered an assertion

(‘1’ value); not toggling at all is considered a de-assertion (‘0’ value).

32, 33

Out

SDVO_INT+/-

BSCAN

BSCAN (internal pull low)

This pin must be left open (not connected) in the application. This pin enables

the boundary scan for in-circuit testing. See section Error! Reference source

not found. for details. Voltage level is 0 to DVDD.

Test Pin (internal pull-down)

This pin must be left open (not connected) in the application.

37, 38, 40, In

41, 43, 44

SDVO_R+/-,

SDVO_G+/-,

SDVO_B+/-

SDVO Data Channel Inputs

These pins accept 3 AC-coupled differential pair of inputs from a digital video

port of a graphics controller. These 3 pairs of inputs are R, G, B. The

differential p-p input voltage has a max. value of 1.2V, with a min. value of

175mV.

Differential Clock Input associated with SDVO Data channel

The range of this clock pair is 100~200MHz. For specified pixel rates in

specified modes this clock pair will run at an integer multiple of the pixel rate.

Refer to section Error! Reference source not found. for details. The

differential p-p input voltage has a max. value of 1.2V, with a min. value of

175mV.

46, 47

SDVO_CLK+/-

12,28

7,30

15, 21

18, 24

36, 42, 48 Power

31, 39, 45 Power

Power

DVDD

DGND

TVDD

TGND

AVDD

AGND

Digital Supply Voltage (2.5V)

Digital Ground

DVI Transmitter Supply Voltage (3.3V)

DVI Transmitter Ground

Analog Supply Voltage (2.5V)

Analog Ground

Power

AVDD_PLL

AGND_PLL

DVI PLL Supply Voltage (3.3V)

DVI PLL Ground

201-0000-071

Rev. 0.41,

2/8/2005

CHRONTEL

CH7312

2.0 PACKAGE DIMENSIONS

TOP VIEW

BOTTOM VIEW

EXPOSED PAD

.008"

Figure 3: 48 Pin LQFP Package

Table of Dimensions

No. of Leads

SYMBOL

48 (7 X 7 mm)

Milli-

MIN

0.17

0.27

1.35

1.45

0.05

0.15

0.45

0.75

0.09

0.20

0°

7°

0.50

1.00

meters

MAX

5.5

Notes:

1. Conforms to JEDEC standard JESD-30 MS-026D.

2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.

3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.

201-0000-071

Rev. 0.41, 2/8/2005

CHRONTEL

CH7312

Disclaimer

This document provides technical information for the user. Chrontel reserves the right to make changes at any time

without notice to improve and supply the best possible product and is not responsible and does not assume any

liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use

of our products and assume no liability for errors contained in this document. The customer should make sure that

they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the

products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not

infringe upon or assist others to infringe upon such rights.

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT

SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF

Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used

as directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Number of

Part Number

CH7312A-DE

Package Type

Voltage Supply

2.5V & 3.3V

Pins

LQFP with exposed

pad

LQFP with exposed

pad in Tape & Reel

Lead free LQFP with

exposed pad

CH7312A -DE-TR

CH7312A -DEF

Lead free LQFP with

CH7312A -DEF-TR exposed pad in Tape &

Reel

2.5V & 3.3V

Chrontel

2210 O’Toole Avenue, Suite 100,

San Jose, CA 95131-1326

Tel: (408) 383-9328

Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

Printed in the U.S.A.

201-0000-071

Rev. 0.41,

2/8/2005

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