CH7315B-TEF-I-TR_技术文档

CH7315B

Chrontel

CH7315B HDMI Transmitter

FEATURES

GENERAL DESCRIPTION

The CH7315B HDMI transmitter is mixed-signal video

interface chip that transmits uncompressed, copy-

protected video and audio data over a secure link from

PCs to external television, HDTVs, DVD recorders and

A/V receivers using HDMI standard.

•

Supports High-Definition Multimedia Interface

(HDMI) version 1.1 and 1.2

•

High-speed SDVO^*(1G~2Gbps) AC-coupled serial

differential inputs

Supports Intel® High Definition Audio (HD Audio)

version 1.0

The CH7315B also complies with Intel SDVO (Serial

Digital Video Output} PC interface specification. The

CH7315B HDMI transmitter receives video data through

the SDVO bus, and it receives audio data from via an

Intel HD (High Definition) Audio bus. CH7315B

combines video and audio data, converting it into a single

HDMI compliant bit stream for transmission to external

CE (consumer electronics) devices. . The CH7315B

device contains HDCP cryptographic functions and

HDCP keys.

•

Supports S/PDIF sampling rate up to 192 kHz

Supports switched DVI/HDMI encoding two outputs

port A and B one at the time

•

Provides High-Bandwidth Digital Content Protection

(HDCP) version 1.1 over HDMI

Support HDMI repeater, a maximum depth of two

with maximum number of two leaves (non-repeating

receivers)

•

Supports HDMI video formats

(480i/576i/240p/480p/288p/576p/720p/1080i/1080p)

specified in EIA/CEA-861C, DVI and VGA outputs.

Supports DVI video formats

Supporting graphics resolutions up to 1600x1200

pixels and 1920x1200 (reduced blanking), refer to

Table 4 for more information

The CH7315B accepts SDVO serial input speeds of

1Gbps to 2Gbps and transmits video output at 25Mpps

(pixels per second) to 165Mpps – pixel rates that support

all HDTV display modes from 480I to 1080i/1080p.

The CH7315B device accepts RGB signals of 256-level

(0-255) or 220-level (16-235) over three pairs of serial

differential data ports, then performs the color space

conversion and outputs 256-level (0-255) or 220-level

(16-235) RGB, 4:2:2 YCbCr or 4:4:4 YcbCr data.

•

Supports VESA video formats for both the CVT

standard and the CEA-861-C standard

Support video pixel rate range from 25M to165M

pixels per second

Support fixed 24MHz clock input for audio data

synchronization

HDMI video low jitter PLL

The CH7315B device also supports up to 8-channel audio

output at 192 KHz. audio data. Available audio

bandwidth depends on the pixel clock frequency, the

video format timing, and whether or not content

protection re-synchronization is needed.

•

HDMI hot plug detection

Automatically enters power saving mode if TV

monitor is turned off or is disconnected from the

input video source

Chrontel’s advanced “Audio Listening Mode” can

automatically intercept digital audio stream from a

HD controller to a third party HD audio device

Configuration through Intel® OpCodes^*

Windows XP and Vista support (including MCE and

64-bit variations)

Auto Power Saving mode is a new feature in the

CH7315B that saves PC laptop power by automatically

putting the chip into a low power consumption state if a

no-need-for-transmission situation is detected.

•

Audio, video and auxiliary data are transmitted across the

three HDMI data channels. The video pixel clock is

transmitted on the HDMI clock channel. In order to

transmit audio and auxiliary data across the HDMI

channels, HDMI uses a packet structure and a special

error reduction coding.

•

Offered in a 64-pin LQFP package

The CH7315B features dual output ports with

dedicated DDC pins so that two external CE devices can

be connected simultaneously and can be selected one at a

time via software control. This eliminates the need to

manually switch connectors as consumers swap the active

receiving device from one connector to another. This

feature allows easy implementation of a second HDMI

output via the docking station of a notebook PC.

^*Intel® Proprietary.

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CHRONTEL

CH7315B

2

SDVOB_INT(+,-)

Interrupt

Generation

Audio encryption status

change request

HPDET1

HPDET2

2

SDVO_ CLK(+,-)

SDVO

Decoder

Color Space

Conversion

SDVO_R (+,-)

SDVO_G (+,-)

SDVO_B (+,-)

6

2

TLAC (+,-)

HDMI

Output

Switch

(+,-)

TDAC 0

SC_KEY

SD_KEY

PROM2

PROM1

2

TDAC 1 (+,-)

TDAC 2 (+,-)

TLBC (+,-)

HDMI

(TERC4)

Encoder

HDCP

Encryption

TDBC 0 (+,-)

Video/Audio

Mixer

(+,-)

TDBC 1

2

(+,-)

TDBC 2

S/PDIF

BCLK

SYNC

SDO

Audio

Decoder

Memory AV Buffer

Timing Control

Audio

Packet

Generator

SDI

RSTB

AS

Control

Register

SPC

SPD

A

I

F

G

P

6

G

P

5

G

P

4

G

P

3

G

P

2

G

P

1

G

P

0

A

V

I

E

L

D

A/V buffers

SC_PROM

SD_PROM

SC_DDC0

SD_DDC0

SC_DDC1

SD_DDC1

Figure 1: Functional Block Diagram

2

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CH7315B

Table of Contents

1.0 Pin-Out ____________________________________________________________________ 4

1.1

1.2

Package Diagram ___________________________________________________________________4

Pin Description _____________________________________________________________________5

2.0 Functional Description________________________________________________________ 8

2.1

2.2

2.3

2.4

2.5

2.6

Video Input Interface ________________________________________________________________8

Audio ____________________________________________________________________________8

Power Saving ______________________________________________________________________9

HDCP Compatibility ________________________________________________________________9

HDMI Transmitter _________________________________________________________________10

Command Interface ________________________________________________________________12

3.0 Register Control ____________________________________________________________ 13

4.0 Electrical Specifications______________________________________________________ 14

4.1

4.2

4.3

4.4

4.5

Absolute Maximum Ratings __________________________________________________________14

Recommended Operating Conditions___________________________________________________14

Electrical Characteristics ____________________________________________________________15

DC Specifications __________________________________________________________________15

AC Specifications __________________________________________________________________18

5.0 Package Dimensions_________________________________________________________ 20

6.0 Revision History ____________________________________________________________ 21

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CH7315B

1.0 PIN-OUT

1.1 Package Diagram

AUDRST*

BCLK

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AVDD_INT

SDVO_INT-

SDVO_INT+

AGND_INT

S/PDIF

DVDD

2

AGND_PLL

SC_PROM

SD_PROM

AVDD_PLL

SC_DDC0

SD_DDC0

SPC

3

4

5

6

7

AS

Chrontel

CH7315B

8

PROM2

9

PROM1

SPD

10

11

12

13

14

15

16

HPDET1

HPDET0

DGND

SC_DDC1

SD_DDC1

DVDD

TDBC2

TDAC2

RESET*

VSWING

TDAC2*

TDBC2*

Figure 2: 64-Pin LQFP Pin Out

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CH7315B

1.2 Pin Description

Table 1: Pin Description

Pin #

Type

Symbol

AUDRST*

Description

1

In

Audio Reset

This signal sources from HD audio link. When it is low, the device is in default

power on reset state.

2

4

BCLK

Audio Bit Clock

24.00MHz clock sources from HD audio link.

In/Out

SC_PROM

Routed Clock Output to PROM

This pin functions as the clock bus of the serial port to PROM on ADD2 card.

This pin will require a pull-up resistor to the desired high state voltage. Leave

open if unused.

5

7

8

SD_PROM

SC_DDC0

SD_DDC0

Routed Data to PROM

This pin functions as the bi-directional data pin of the serial port for PROM on

ADD2 card. This pin will require a pull-up resistor to the desired high state

voltage. Leave open if unused.

Routed Serial Port Clock to Port A DDC

This pin functions as the clock bus of the serial port to DDC receiver. This pin

will require a pull-up resistor of 1.8kΩ to the desired high state voltage. Leave

open or tied high with a 10kΩ resistor if unused.

Routed Serial Port Data to Port A DDC

This pin functions as the bi-directional data pin of the serial port to DDC

receiver. This pin will require a pull-up resistor of 1.8kΩ to the desired high

state voltage. Leave open or tied high with a 10kΩ resistor if unused.

9

In/Out

SPC

SPD

Serial Port Clock Input / Output

This pin functions as the clock input of the serial port and operates with inputs

from 0 to 2.5V. This pin requires an external 2.2kΩ pull up resistor to 2.5V.

Serial Port Data Input / Output

10

This pin functions as the bi-directional data pin of the serial port and operates

with inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin

requires an external 2.2kΩ pull up resistor to 2.5V.

12

13

In/Out

SC_DDC1

SD_DDC1

Routed Serial Port Clock to Port B DDC

This pin functions as the clock bus of the serial port to DDC receiver.

This pin will require a pull-up resistor of 5.6kΩ to the desired high

state voltage. This pin should be pulled low with a 10K ohm resistor

(recommended) or left open if unused.

Routed Serial Port Data to Port B DDC

This pin functions as the bi-directional data pin of the serial port to

DDC receiver. This pin will require a pull-up resistor of 5.6kΩ to the

desired high state voltage. This pin should be pulled low with a 10K

ohm resistor (recommended) or left open if unused.

15

16

In

RESET*

Reset* Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset condition. When

this pin is high, reset is controlled through the serial port register.

VSWING

HDMI Swing Control

This pin sets the swing level of the HDMI outputs. A 1.2K-ohm resistor

should be connected between this pin and TGND using short and wide traces.

19, 20

24, 25

29, 30

34, 35

Out

TLAC*, TLAC

HDMI Port A Clock Outputs

These pins provide the differential clock output for the HDMI port A

corresponding to data on the TDAC [2:0] outputs.

TDAC0*, TDAC0

TDAC1*, TDAC1

TDAC2*, TDAC2

HDMI Port A Data Channel 0 Outputs

These pins provide the HDMI port A differential outputs for data channel 0

(blue).

HDMI Port A Data Channel 1 Outputs

These pins provide the HDMI port A differential outputs for data channel 1

(green).

HDMI Port A Data Channel 2 Outputs

These pins provide the HDMI port A differential outputs for data channel 2

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CH7315B

Pin #

18, 21

Type

Out

Symbol

Description

(red).

TLBC*, TLBC

HDMI Port B Clock Outputs

These pins provide the differential clock output for the HDMI port B

corresponding to data on the TDBC [2:0] outputs.

23, 26

28, 31

33, 36

38

Out

In

TDBC0*, TDBC0

TDBC1*, TDBC1

TDBC2*, TDBC2

HPDET0

HDMI Port B Data Channel 0 Outputs

These pins provide the HDMI port B differential outputs for data channel 0

(blue).

HDMI Port B Data Channel 1 Outputs

These pins provide the HDMI port B differential outputs for data channel 1

(green).

HDMI Port B Data Channel 2 Outputs

These pins provide the HDMI port B differential outputs for data channel 2

(red).

Hot Plug Detect (internal pull-down)

This input pin determines whether the HDMI output driver is connected to a

HDMI monitor. When port A is connected, the monitor is required to supply a

voltage greater than 2.4 volts.

39

40

41

42

In

HPDET1

PROM1

PROM2

AS

Hot Plug Detect (internal pull-down)

This input pin determines whether the HDMI output driver is connected to a

HDMI monitor. When port B is connected, the monitor is required to supply a

voltage greater than 2.4 volts.

In/Out

In

Routed Data to PROM

This pin functions as the bi-directional data pin of the serial port for PROM on

ADD2 card. This pin will require a pull-up resistor of 1.8 kΩ to the desired

high state voltage. Leave open or tied high with a 10kΩ resistor if unused.

Routed Clock to PROM

This pin functions as the clock bus of the serial port to PROM on ADD2 card.

This pin will require a pull-up resistor of 1.8kΩ to the desired high state

voltage. Leave open or tied high with a 10kΩ resistor if unused.

Address Select

This pin determines the serial port address of the device (0,1,1,1,0,0,AS*, 0).

When AS is tied low (10kΩ), the address is 72h. When AS is tied high (10kΩ),

the address is 70h. This pin must be externally pulled high / low.

S/PDIF Audio Input

44

In

S/PDIF

This pin accepts digital serial input that complies with IEC60958 for audio

bitstreams.

46, 47

Out

SDVO_INT+/-

Interrupt Output Pair associated with SDVO Data Channel

These pins output one AC-coupled differential pair of interrupt signals used as

a hot plug attach/detach notification to VGA controller. Toggling between

100MHz and 200MHz on this pair is considered an assertion (‘1’ value); not

toggling at all is considered a de-assertion (‘0’ value).

49, 50,

52,53,

55,56

In

SDVO_R+/-,

SDVO_G+/-,

SDVO_B+/-

SDVO Data Channel Inputs

These pins accept 3 AC-coupled (100nF) differential pair of inputs from a

digital video port of a graphics controller. These 3 pairs of inputs are R, G, B.

The differential peak-peak input voltage has a max value of 1.2V, with a min.

value of 175mV.

58,59

SDVO_CLK+/-

Differential Clock Input associated with SDVO Data channel

These pins accept one AC-coupled differential pair of input from a digital

video port of a graphics controller. The range of this clock pair is

100~200MHz. For specified pixel rates in specified modes this clock pair will

run at an integer multiple of the pixel rate. The differential peak-peak input

voltage has a max value of 1.2V, with a min. value of 175mV.

61

Out

SDI

Serial Data In for audio side

The device drives SDI and the controller samples SDI with respect to the rising

edge of BCLK.

63

64

6

In

SDO

Serial Data Out for audio side

The controller drives data onto SDO and the device samples data present on

SDO with respect to every edge of BCLK.

AUDSYNC

SYNC signal for audio side

This signal marks input and output frame boundaries (Frame Sync) as well as

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CH7315B

Pin #

Type

Symbol

Description

identifying outbound data streams (stream tags). SYNC is always sourced from

the controller.

14,43

Power

DVDD

Digital Supply Voltage (2.5V)

Digital Ground

11,37

17, 27

22,32

45

Power

DGND

TVDD

HDMI Transmitter Supply Voltage (3.3V)

HDMI Transmitter Ground

TGND

AGND_INT

AVDD_INT

AVDD

Interrupt block Ground

48

Interrupt block Supply Voltage (2.5V)

Analog Supply Voltage (2.5V)

Analog Ground

54, 60

51, 57

3

AGND

AGND_PLL

AVDD_PLL

VDDIO

HDMI PLL Ground

HDMI PLL Supply Voltage (3.3V)

HDMI audio interface supply voltage (1.5V/3.3V)

6

62

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CH7315B

2.0 FUNCTIONAL

DESCRIPTION

2.1 Video Input Interface

2.1.1

Overview

The CH7315B HDMI transmitter receives video data through the SDVO bus. One pair of differential clock signal

and three differential pairs of data signals (R/G/B) form one channel data. The input data are 10-bit serialized data.

Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate (SDVO_CLK+/-). The CH7315B de-

serializes the input into 10-bit parallel data with synchronization and alignment. Then the 10-bit characters are

mapped into 8-bit color data or control data (HSYNC, VSYNC, DE).

2.1.2

Interface Voltage Levels

All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level

for the signals to operate at. The differential peak-peak input voltage has a min of 175mV, and a max of 1.2V. The

differential peak-peak output voltage has a min of 0.8V, with a max of 1.2V.

2.1.3

Input Clock and Data Timing

A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of

the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.

The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate

do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x, or 4x depending on the pixel rate) so

that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a

multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters

(‘0001111010’) are used to stuff the data stream. The CH7315B supports the following clock rate multipliers and fill

patterns shown in Table 2

Table 2: CH7315B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns

Pixel Rate

Clock Rate – Multiplier

Stuffing Format

Data, Fill, Fill, Fill

Data, Fill

Data Transfer Rate - Multiplier

1.00~2.00Gbits/s – 10xClock Rate

25~50 MP/s

50~100 MP/s

100~200 MHz – 4xPixel Rate

100~200 MHz – 2xPixel Rate

100~200 MP/s 100~200 MHz – 1xPixel Rate

Data

2.1.4 Synchronization

Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during

the blank period. The CH7315B synchronizes during the initialization period and subsequently uses the blank

periods to re-synch to the data stream.

2.2 Audio

The CH7315B can support both HD Audio and S/PDIF audio inputs. It also has the ability to decode a third party

HD Audio Codec’s digital audio stream from the HD Audio Link

2.2.1

HD Audio General Description

The CH7315B HDMI transmitter receives audio data from via an Intel High Definition Audio with UAA (Universal

Audio Architecture) and features a digital output converter and a HDMI pin widget, which is designed for high

performance multimedia platform. The CH7315B transmitter supports up to 8 channels, 192kHz and 24 bits per

sample, and pack all these audio data into data island package, then send them out through HDMI link.

8

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CH7315B

2.2.2

HD Audio Features

•

Supports 32/44.1/48/88.2/96/176.4/192kHz sample rate input

Supports 16/20/24 bits per sample input

Supports up to 8 channels

•

Supports HDCP for audio and video

Supports multiple power states control

Supports up to 7 general-purposed buffer

Supports AC3 and LPCM

2.2.3

S/PDIF

CH7315B supports 32 kHz, 44.1 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192kHz sampling rates.

2.2.4 Audio Listening Mode

CH7315B can playback an audio stream from a HD audio controller without changing the audio driver.

In addition to supporting the HD Audio and S/PDIF, CH7315B has a capability of automatically detecting,

intercepting and transmitting through HDMI a digital audio stream that is sent from a HD Audio Controller to a

third party HD Audio decoder device. In other words, the intercepting is done automatically without changing the

audio driver in order to have such a simultaneous playback on two devices.

For more implementation, please contact Chrontel Application Support.

2.3 Power Saving

CH7315B offers two power saving features that allow for a significant reduction in the power consumed for the PC

system. If a normal system Power-off/Suspend procedure has taken place or GMCH has failed to communicate to

TV monitor through DDC lines, the Intel Software Graphic Driver will send an Opcode* Command to CH7315B to

enter Power-Down mode. The other smart feature that has been incorporated to the CH7315B is the Auto Power-

Saving Mode*. This feature detects the TV monitor connection voltage level and automatically forces CH7315B

into a low power state when a significant voltage drop has occurred. For example, if a TV monitor is switched off

or is disconnected from the input video source, a voltage drop on DVI/HDMI transmission lines will trigger the

CH7315B Auto Power Saving circuitry, and it will automatically shut off most of the device circuitry including the

HDMI Output Driver. The CH7315B will resume its normal operation once the TV monitor is plugged back in or

switched on.

2.4 HDCP Compatibility

High Bandwidth Digital Content Protect (HDCP) provides a means of protecting the video transmission between a

HDMI video transmitter and a HDMI video receiver. Under HDMI, both audio and video data are encrypted or both

are decrypted. The CH7315B supports HDCP in its audio and video output data stream. CH7315B processes

incoming audio encryption status change request along with video transmission. The content protection system

includes a process of (a) authentication in which the video transmitter verifies that a given video receiver is licensed

to receive protected content; (b) encryption in which the transmitted video data is encrypted based on secret codes

exchanged during the authentication process; and (c) renewability in which the video transmitter can identify

compromised receivers and prevent the transmission of protected content.

Each HDCP authorized device (transmitter or receiver) has an array of 40, 56-bit secret device keys and a Key

Selection Vector (KSV) obtainable from Digital Content Protection LLC (http://www.digital-cp.com/). With the

addition of the encrypted HDCP device keys, the CH7315B can be configured to be a HDCP compliant transmitter.

A possible connection diagram is shown in the following figure.

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CHRONTEL

CH7315B

Intel audio driver

Audio encryption

status change

request

SDVO Data

SDVO Clock

SDVO Data

SDVO Clock

HDCP

HDMI Data Bus

Serial Data

SPD

SPC

compliant HDMI

receiver

Serial Clock

CH7315B

Intel

Graphics

Controller

AKSV, DKSV

AKEYS, DKEYS

storage

EEPROM

Authentication exchange

Figure 3: Possible Connection Diagram for HDCP

Details of the CH7315B HDCP operation are available in a separate document. Contact Chrontel for details. See

also the “High Bandwidth Digital Content Protection System” specification available at http://www.digital-cp.com/.

2.5 HDMI Transmitter

The CH7315B HDMI link includes three Data channels and a single Clock channel. The Clock channel constantly

runs at the pixel rate of the transmitted video. During every cycle of the Clock channel, each of the three data

channels transmits a 10-bit character. This 10-bit word is encoded using one of several different coding techniques.

The input stream to CH7315B’s encoding logic contains video pixel, packet and control data. The packet data

consists of audio and auxiliary data and associated error correction codes.

These data items are processed in a variety of ways and are presented to the HDMI encoder as either 2 bits of

control data, 4 bits of packet data or 8 bits of video data per HDMI channel. CH7315B encodes one of these data

types or encodes a Guard Band character on any given clock cycle.

CH7315B allows any video format timing to be transmitted and displayed. To maximize interoperability between

products, common DTV formats have been defined. Table 4 lists all video formats CH7315B supports (Refer to

VESA CVT Standard and EIA/CEA861C for detailed timing information).

Table 3: HDMI video formats CH7315B supports

Video Code

Display Video Format

640x480p@59.94/60

Pixel Frequency (MHz)

25.175/25.200

1

2&3

4

720x480p@59.94/60

27.000/27.027

1280x720p@59.94/60

1920x1080i@59.94/60

720 (1440) x480i @59.94/60

74.176/74.250

5

74.176/74.250

6&7

8&9

27.000/27.027

720 (1440) x

240p@59.94/60

Mode1

27.000/27.027

Mode2

10&11

12&13

(2880) x 480i @ 59.94/60

54.000/54.054

(2880) x 240p @

59.94/60

Mode1

Mode2

14&15

1440x480p@59.94/60

54.000/54.054

10

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CHRONTEL

CH7315B

Video Code

16

Display Video Format

1920x1080p@59.94/60

720x576p@50

Pixel Frequency (MHz)

148.352/148.500

27.000

17&18

19

1280x720p@50

74.250

20

1920x1080i@50

74.250

21&22

23&24

720 (1440) x 576i @50

27.000

720 (1440) x288p @50

Mode1

27.000

Mode2

Mode3

25&26

27&28

(2880) x 576i @50

(2880) x 288p @50

54.000

Mode1

Mode2

Mode3

29&30

31

1440x576p@50

54.000

148.500

1920x1080p@50

1920x1080p@23.97/24

1920x1080p@25

32

74.176/74.250

74.250

33

34

1920x1080p@29.97/30

2880x480p @ 59.94/60Hz

2880x576p @ 50Hz

74.176/74.250

108.000/108.108

108.000

35,36

37,38

39

1920x1080i (1250 total) @ 50Hz

1920x1080i @ 100Hz

72.00

40

148.500

41

1280x720p @ 100Hz

148.500

42,43

44,45

46

720x576p @ 100Hz

54.000

720 (1440) x576i @ 100Hz

1920x1080i @ 119.88/120Hz

1280x720p @ 119.88/120Hz

720x480p @ 119.88/120Hz

720 (1440) x480i @ 119.88/120Hz

720X576p @ 200Hz

54.000

148.352/148.500

54.000/54.054

108.000

47

48,49

50,51

52,53

54,55

56,57

58,59

720 (1440) x 576i @ 200Hz

720x480p @ 239.76/240Hz

720 (1440) x480i @ 239.76/240Hz

108.000

108.000/108.108

Table 4: DVI Output Formats CH7315B supports

Graphics

Resolution

Active Aspect

Ratio

Pixel Aspect

Ratio

Refresh Rate

(Hz)

Input pixel

DVI

Frequency

(Mbits/Sec)

<355

Frequency

(MHz)

<35.5

<31.5

<36

720x400

640x400

4:3

8:5

1.35:1.00

1:1

<85

<75

<60

<315

<360

640x480

800x600

4:3

1:1

<57

<95

<570

<950

1024x768

1280x720

1280x768

1280x1024

1366x768

1360x1024

1400x1050

1600x1200

4:3

16:9

15:9

4:3

1:1

<110

<119

<158

<140

<145

<156

<165

<1100

<1190

<1580

<1400

<1450

<1560

<1650

1:1

16:9

4:3

1:1

4:3

1:1

◊

16:9

1:1

<165

<1650

1920x1080

16:10

1:1

<60

1920x1200

◊

This mode is implemented with reduced blanking.

201-0000-079

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CHRONTEL

CH7315B

Table 5: Popular Panel Sizes

UXGA

SXGA+

1600x1200

1400x1050

1360x1024

1280x1024

1280x960

1024x768

1024x600

800x600

SXGA

XGA

SVGA

2.6 Command Interface

Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7315B accepts incoming

control clock and data from graphics controller, and is capable of redirecting that stream to PROM, DDC, or

CH7315B internal registers. The control bus is able to run up to 1MHz when communicating with internal registers,

up to 400KHz for the PROM and up to 100KHz for the DDC.

Internal

Device

Registers

control

the

observer

switch

DDC0

on/off

Control Bus

from VGA

DDC1

DDC

default

PROM

position

Figure 4: Control Bus Switch

Upon reset, the default state of the directional switch is to redirect the control bus to PROM. At this stage, the

CH7315B observes the control bus traffic. If the observing logic sees a control bus transaction destined for the

internal registers (device address 70h or 71h based on AS pin external setting), it disables the PROM output pairs,

and switches to internal registers. In the condition that traffic is to the internal registers, an OpCode command is

used to set the redirection circuitry to the appropriate destination (PROM or DDC). Redirecting the traffic to internal

registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus.

12

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CHRONTEL

CH7315B

3.0 REGISTER

CONTROL

The CH7315B is controlled via a serial control port. The serial bus uses only the SC clock to latch data into

registers, and does not use any internally generated clocks so that the device can be written into even in all power

down modes. The device will retain all register values during power down modes.

201-0000-079

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CHRONTEL

CH7315B

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings

Table 6:

T

SC, AMB, STOR, J, VPS Ratings

T T

Symbol

Description

Min

Typ

Max

Units

All 2.5V power supplies relative to GND

All 3.3V power supplies relative to GND

-0.5

3.5

5.0

V

T

Analog output short circuit duration

Storage temperature

Indefinite

Sec

°C

SC

-65

150

260

245

225

STOR

J

Junction temperature

Vapor phase soldering (5 second)

Vapor phase soldering (11 second)

Vapor phase soldering (60 second)

VPS

Note:

1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions above those

indicated under the normal operating condition of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive

device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can cause

permanent damage.

4.2 Recommended Operating Conditions

Table 7: Recommended Operating Conditions

Test

Symbol

Description

Min

Typ

Max

Condition

2.375

3.100

2.375

3.100

1.425

3.100

2.375

0

AVDD

Analog Power Supply Voltage

Analog interrupt Power Supply Voltage

Analog PLL Power Supply Voltage

Digital Power Supply Voltage

DVI Power Supply

2.5

3.3

2.5

3.3

2.625

3.500

2.625

3.500

2.625

70

V

AVDD_INT

AVDD_PLL

DVDD

V

TVDD

V

VDDIO

Audio interface Power Supply voltage

Generic for all 3.3V supplies

Generic for all 2.5V supplies

V

VDD33

3.3

2.5

V

VDD25

V

Ambient operating temperature (Commercial / Automotive

Grade 4)

Ambient operating temperature (Industrial / Automotive

Grade 3)

T

AMB

°C

-40

85

14

201-0000-079

Rev. 1.9,

1/7/2014

CHRONTEL

CH7315B

4.3 Electrical Characteristics

(Operating Conditions: T

A

= 0°C to 70°C for parts qualified as Commercial / Automotive Grade 4, T = –40°C to

A

85°C for parts qualified as Industrial / Automotive Grade 3, VDD25 =2.5V 5%, VDD33=3.3V 5%)

Table 8: Electrical Characteristics

Symbol

Description

Min

Typ

Max

Unit

I

Total VDD25 supply current (2.5V supplies)

Pixel Rate=162MHz

VDD25

210

mA

Total VDD33 supply current (3.3V supply)

Pixel Rate=162MHz

VDD33

PD

75

mA

uA

Total Power Down Current (all supplies)

100

4.4 DC Specifications

Table 9: DC Specifications

Symbol

Description

Test Condition

Min

Typ

Max

Unit

V_RX-DIFFp-p

SDVO Receiver Differential

Input Peak to Peak Voltage

V_RX-DIFFp-p= 2 *

V_RX-D+- V_RX-D-

0.175

1.200

120

60

V



Z_RX-DIFF-DC

SDVO Receiver DC

80

100

50

Ω

Differential Input Impedance

Z_RX-COM-DC

SDVO Receiver DC Common

Mode Input Impedance

40

Z_RX-COM-

SDVO Receiver Initial DC

Common Mode Input

Impedance

Impedance allowed

when receiver

5

50

60

INITIAL-DC

terminations are first

turned on

SDVO INT Differential Output

Peak to Peak Voltage

V_INT-DIFFp-p

0.8

1.2

V

1

V_SPOL

Serial Port

I

= 2.0 mA

0.4

OL

Output Low Voltage

2

V_SPIH

Serial Port

VDD25 + 0.5

V

Input High Voltage

2.0

2

V_SPIL

Serial Port

Input Low Voltage

GND-0.5

0.4

2

V_HYS

Serial Port

V

Input Hysteresis

0.25

4.0

V_DDCIH

DDC Serial Port

VDD5 + 0.5

Input High Voltage

V_DDCIL

DDC Serial Port

Input Low Voltage

GND-0.5

4.0

0.4

V_PROMIH

V_PROMIL

PROM Serial Port

Input High Voltage

VDD5 + 0.5

PROM Serial Port

Input Low Voltage

GND-0.5

0.4

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CHRONTEL

CH7315B

Symbol

Description

Test Condition

Min

Typ

Max

Unit

3

Input is V_INLat

SD_DDC or

SD_PROM.

V_{SD_DDCOL}

SPD (serial port data) Output

Low Voltage from SD_DDC

(or SD_PROM)

0.9*V_INL+ 0.25

V

2.2kΩ pull-up to 2.5V.

4

Input is V_INLat SPC

and SPD.

V_DDCOL

SC_DDC and SD_DDC

Output Low Voltage

0.933*V_INL+ 0.35

V

1.8kΩ pull-up to 5.0V.

5

Input is V_INLat SPC

and SPD.

V_PROMOL

SC_PROM and SD_PROM

Output Low Voltage

5.6kΩ pull-up to 2.5V.

6

RESET* Input High Voltage

RESET* Input Low Voltage

AS Input High Voltage

V_MISC1IH

2.7

GND-0.5

2.0

VDD33 + 0.5

0.5

V

6

V_MISC1IL

7

V_MISC2IH

VDD25 + 0.5

7

AS Input Low Voltage

V_MISC2IL

DVDD = 2.5V

GND-0.5

1.4

0.5

V

V_MISC3IH

V_MISC3IL

I_MISC1PU

HPDET0, HPDET1,

Input High Voltage

3.72

HPDET0, HPDET1,

Input Low Voltage

GND-0.5

10

0.5

40

V

RESET*

V_IN= 0V

uA

Pull Up Current

HPDET0, HPDET1

Pull Down Current

V_IN= 2.5V

I_MISC2PD

5

20

40

uA

10

AS

V_IN= 0V

I_MISC2PU

10

40

uA

V

Pull Up Current

8

Audio Interface input low

voltage

V_AUDIL

GND-0.5

0.35*VDDIO

VDDIO + 0.5

8

Audio Interface input high

voltage

V_AUDIH

0.65*VDDI

O

V

8

Audio interface output low

voltage

I_OUT= 1500 uA

I_OUT= -500 uA

V_AUDOL

GND-0.5

0.1*VDDIO

VDDIO + 0.5

TVDD + 0.01

V

8

Audio interface output high

voltage

V_AUDOH

0.9*VDDIO

HDMI Single Ended Output

High Voltage

TVDD = 3.3V 5%

V_H

TVDD –

0.01

R_TERM= 50Ω 1%

HDMI Single Ended Output

Low Voltage

R_SWING= 1200Ω 1%

V_L

TVDD – 0.6

400

TVDD – 0.4

600

V

mVp-p

V

HDMI Single Ended Output

Swing Voltage

V_SWING

V_OFF

HDMI Single Ended Standby

(off) Output Voltage

TVDD –

0.01

TVDD + 0.01

I_OFF

HDMI Single Ended Standby

(off) Output Current

10

uA

16

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CHRONTEL

CH7315B

Notes:

1. Refers to SPD. V_SPOLis the output low voltage from SPD when transmitting from internal registers not from DDC,

EPROM or system.

2. Refers to SPC and SPD.

V_{SD_DDCOL}is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_PROM is V_INL. Maximum output

3.

voltage has been calculated with the worst case of pull-up of 2.2kΩ to 2.5V on SPD. There are two DDC SPP interface,

SC_DDC0/1 and SD_DDC0/1.

4. V_DDCOLis the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is V_INL. Maximum

output voltage has been calculated with 1.8k pull-up to 5V on SC_DDC and SD_DDC.

5.

V

_PROMOLis the output low voltage at the SC_PROM and SD_PROM pins when the voltage at SPC and SPD is V_INL

Maximum output voltage has been calculated with 5.6kΩ pull-up to 2.5V on SC_PROM and SD_PROM.

6. V_MISC1refers to RESET* input which is 3.3V compliant.

7. _MISC2refers to AS. AS is 2.5V compliant.

.

V

8. V_AUDrefers to SDI, SDO, AUDSYNC, AUDRST* and BCLK which are 1.5V and 3.3V compliant. Only SDI can be output.

VDDIO is the audio interface power supply voltage, it can be 1.5V or 3.3V.

201-0000-079

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CHRONTEL

CH7315B

4.5 AC Specifications

Table 10: AC Specifications

Symbol

Description

Test Condition

Min

Typ

Max

Unit

UI_DATA

SDVO Receiver Unit Interval

for Data Channels

Typ. –

1/[Data

Transfer

Rate]

Typ. +

ps

300ppm

f_{SDVO_CLK}

f_PIXEL

SDVO CLK Input Frequency

HDMI Transmitter Pixel Rate

100

25

1

200

165

2

MHz

GHz

f_SYMBOL

SDVO Receiver Symbol

Frequency

t_RX-EYE

SDVO Receiver Minimum Eye

Width

0.4

UI

t_{RX-EYE-JITTER}

SDVO Receiver maximum

time between jitter median

and maximum deviation from

median

0.3

V_RX-CM-Acp

SDVO Receiver AC Peak

150

mV

Common Mode Input Voltage

RL_RX-DIFF

RL_RX-CM

t_SKEW

Differential Return Loss

50MHz – 1.25GHz

Across all lanes

15

6

dB

ns

Common Mode Return Loss

SDVO Receiver Total Lane to

Lane Skew of Inputs

2

T_HDMIR

HMDI Output Rise Time

(20% - 80%)

f_XCLK= 165MHz

75

242

ps

T_HDMIF

HDMI Output Fall Time

(20% - 80%)

t_SKDIFF

t_SKCC

T_HDMIJIT

HDMI Output intra-pair skew

f_XCLK= 165MHz

90

1.2

150

3

ps

ns

HDMI Output inter-pair skew

HDMI Output Clock Jitter

ps

T_rf1

Rise/fall time of Audio output

signal SDI with VDDIO = 3.3V

1

V/ns

T_rf2

Rise/fall time of Audio output

signal SDI with VDDIO = 1.5V

0.5

1.5

24

V/ns

MHz

Freq

Frequency of AC rating

waveform as applied to

AUDIO input (SDI and SDO)

input buffers

I_oh1

Current drive ability of AUDIO

Output signal SDI (pull-up)

Vout = 0.9VCC with

VDDIO = 3.3V

-500

uA

I_ol1

Current drive ability of AUDIO

Output signal SDI (pull-down)

Vout = 0.1VCC with

VDDIO = 3.3V

1500

18

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Rev. 1.9,

1/7/2014

CHRONTEL

CH7315B

Symbol

Description

Test Condition

Min

Typ

Max

Unit

I_oh2

Current drive ability of AUDIO

Output signal SDI (pull-up)

Vout = 0.9VCC with

VDDIO = 1.5V

-500

uA

I_ol2

Current drive ability of AUDIO

Output signal SDI (pull-down)

Vout = 0.1VCC with

VDDIO = 1.5V

1500

3

uA

ns

T_tco

Time after rising edge of

BCLK that output SDI become

valid at the Codec

11

T_su

T_h

Setup for ADUIO Input SDO

at both rising and falling edge

of BCLK

5

ns

Hold for SDO at both rising

and falling edge of BCLK

201-0000-079

Rev. 1.9,

1/7/2014

19

CHRONTEL

CH7315B

5.0 PACKAGE

DIMENSIONS

TOP VIEW

BOTTOM VIEW

A

B

K

48

33

32

49

B

A

K

64

17

1

16

EXPOSED PAD

C

D

4

3X

1X

5

F

E

I

.008"

J

H

G

Figure 5: 64 Pin LQFP (Exposed Pad) Package

Table of Dimensions

No. of Leads

SYMBOL

A

B

C

D

E

F

G

H

I

J

K

64 (10 X 10 mm)

Milli-

meters

MIN

0.17

0.27

1.35

1.45

0.05

0.15

0.45

0.75

0.09

0.20

0°

7°

5.85

7

12

10

0.50

1.00

MAX

Notes:

1. Conforms to JEDEC standard JESD-30 MS-026D.

2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.

3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.

4. (1X) Corner in quadrant with Pin1 identifier (dot) is always chamfered. Exact shape of chamfer is optional.

5. (3X) Corners in quadrants without Pin1 identifier (dot) may be square or chamfered. Exact shape of corner

or chamfer is optional.

20

201-0000-079

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CHRONTEL

CH7315B

6.0 REVISION

HISTORY

Table 11: Revisions

Rev. #

1.0

1.1

Date

Section

All

1.0

Description

3/14/07

3/16/07

8/2/07

Initial release

General Description update.

1.2

1.3

4.4

Change HPDET0, HPDET1 input high voltage spec.

Update Pin 9, Pin 10, Pin 12 and Pin 13 in Table 1 and Table 9.

Update Pin 44, Figure 1 and Figure 2.

Update operating temperature.

9/7/07

1/7/08

1.2, 4.4

1.1, 1.2

4.2, 4.3.

2.5

1.4

1.5

12/19/2008

10/9/2009

4/5/2011

5/24/2012

1.6

1.7

Update Features and Table.4.

Update operating temperatures.

4.1, 4.2

1.1, 1.2, 4.1, 4.2, 4.3, Update ambient operating temperature into Commercial /

1.8

5.0

Automotive Grade 4 and Industrial / Automotive Grade 3.

Modify the description of pin 12 and pin 42 and some

“Absolute Maximum Ratings”.

Modify “Package Diagram”.

Add some notes for “Package Dimensions”.

Pins 46/47 (SDVO_INT+/-) and 58/59 (SDVO_CLK+/-)

should be AC-coupled. Move TAMB from the table 6 table 7.

1.9

1/7/2014

1.2, 4.1, 4.2

201-0000-079

Rev. 1.9,

1/7/2014

21

CHRONTEL

CH7315B

Disclaimer

This document provides technical information for the user. Chrontel reserves the right to make changes at any time

without notice to improve and supply the best possible product and is not responsible and does not assume any

liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use

of our products and assume no liability for errors contained in this document. The customer should make sure that

they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the

products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not

infringe upon or assist others to infringe upon such rights.

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT

SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF

Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used

as directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Number

of Pins

Temperature Grade

Part Number

CH7315B-TEF

Package Type

Voltage Supply

2.5V & 3.3V

Lead Free LQFP with

exposed pad

Commercial /

Automotive Grade 4

64

Lead Free LQFP with

exposed pad

Industrial /

Automotive Grade 3

CH7315B-TEF-I

CH7315B-TEF-TR

CH7315B-TEF-I-TR

64

Lead Free LQFP with

exposed pad in Tape & Reel

Commercial /

Automotive Grade 4

Lead Free LQFP with

exposed pad in Tape & Reel

Industrial /

Automotive Grade 3

Chrontel

2210 O’Toole Avenue, Suite 100,

San Jose, CA 95131-1326

Tel: (408) 383-9328

Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

Printed in the U.S.A.

22

201-0000-079

Rev. 1.9,

1/7/2014


型号：	CH7315B-TEF-I-TR
厂家：	CHRONTEL, INC
描述：	Consumer Circuit, CMOS, PQFP64, 10 X 10 MM, LEAD FREE, MS-026D, LQFP-64 商用集成电路
文件：	总22页 (文件大小：175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CH7315B-TEF-I-TR [CHRONTEL]

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