CS4373 [CIRRUS]
Low-power, High-performance Delta-Sigma Test DAC; 低功耗，高性能的Σ-Δ DAC测试
| 型号： | CS4373 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Low-power, High-performance Delta-Sigma Test DAC |
| 文件： | 总20页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4373
Low-power, High-performance ∆Σ Test DAC
Features
Description
The CS4373 is a differential output digital-to-
analog converter intended for high-resolution,
low-frequency measurement systems. It is de-
signed to work with the CS5376A and CS5378
digital filters, the CS3301 and CS3302 high-pre-
cision amplifiers, and the CS5371 or CS5372
high-performance ∆Σ modulators.
• Digital ∆Σ Input, Differential Analog Output
• Selectable Differential Outputs (OUT , BUF )
• Selectable Output Attenuation
- 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
• User-programmable Test Modes
- Differential
- Common mode
The CS4373 includes a set of multiplexed out-
puts which provide a precision output (OUT±) for
testing the electronics channel and a buffered
output (BUF±) for in-circuit sensor tests. It is driv-
en by a ∆Σ bitstream and the maximum analog
output is differential 5 volts peak-to-peak. Distor-
tion performance of the DAC is typically -118 dB
THD from the precision output, and -100 dB THD
from the buffered output. Noise performance is
114 dB SNR over a 430 Hz bandwidth.
• Output Voltage: 5 V
Differential
P-P
• Outstanding Noise Performance
- 114 dB SNR @ 430 Hz bandwidth
• Low Total Harmonic Distortion
- OUT±: -118 dB THD typical, -112 dB THD max
- BUF±: -100 dB THD typical, -95 dB THD max
• Low Power Consumption
- Normal mode: 7.8 mA
- Low power mode: 5.0 mA
- Power down: 400 µA
- Sleep mode: 2 µA
The CS4373 has very low power consumption. In
normal mode (LPWR=0; MCLK=2.048 MHz),
power consumption is 40 mW; while in Low Pow-
er mode (LPWR=1; MCLK=1.024 MHz), power
consumption is 25 mW.
• Power Supply Options
- VA+ = +5 V;
VA- = 0 V;
VD = +3.3 V to +5 V
- VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V
ORDERING INFORMATION
See page 19.
VA+
MODE(0, 1, 2)
ATT(0, 1, 2)
Attenuator
VD
OUT+
OUT-
TDATA
LPWR
BUF+
BUF-
24-bit ∆Σ
DAC
CAP+
CAP-
Clock
Generator
MCLK
SYNC
VA-
VREF+
VREF-
DGND
Copyright © Cirrus Logic, Inc. 2005
SEP ‘05
DS577F1
http://www.cirrus.com
(All Rights Reserved)
CS4373
TABLE OF CONTENTS
1. CHARACTERISTICS & SPECIFICATIONS ............................................................................. 4
2. TERMINOLOGY ........................................................................................................................ 9
3. GENERAL DESCRIPTION ..................................................................................................... 10
4. ANALOG OUTPUTS ............................................................................................................... 10
4.1 CAP+ / CAP- .................................................................................................................... 10
4.2 OUT+ / OUT- ................................................................................................................... 10
4.3 BUF+ / BUF- .................................................................................................................... 10
5. DIGITAL FILTER INTERFACE ............................................................................................... 10
5.1 Signal Bitstream Input - TDATA ....................................................................................... 10
5.2 Master Clock - MCLK ....................................................................................................... 10
5.3 Clock Sync Input - SYNC ................................................................................................. 11
6. VOLTAGE REFERENCE ........................................................................................................ 11
6.1 Voltage Reference Inputs ................................................................................................ 11
6.2 Voltage Reference Configurations ................................................................................... 11
6.3 VREF Input Impedance .................................................................................................... 11
6.4 Gain Accuracy .................................................................................................................. 12
6.5 Gain Drift .......................................................................................................................... 12
7. TEST MODES ......................................................................................................................... 13
7.1 Test Mode 0: Reserved .................................................................................................... 13
7.2 Test Mode 1: Sensor Test Mode ...................................................................................... 13
7.3 Test Mode 2: Electronics Test Mode ............................................................................... 14
7.4 Test Mode 3: Sensor Test Mode ...................................................................................... 14
7.5 Test Mode 4: Common Mode .......................................................................................... 14
7.6 Test Mode 5: High Voltage/High Current Mode ............................................................... 14
7.7 Test Mode 6: Reserved .................................................................................................... 14
7.8 Test Mode 7: Sleep Mode ................................................................................................ 14
8. ATTENUATION SETTINGS .................................................................................................... 15
9. POWER MODES ..................................................................................................................... 15
9.1 Normal Power Mode ........................................................................................................ 15
9.2 Low Power Mode ............................................................................................................. 15
9.3 Sleep Mode ...................................................................................................................... 15
9.4 Power Down ..................................................................................................................... 15
10. POWER SUPPLY ................................................................................................................ 15
10.1 Power Supply Bypassing .............................................................................................. 15
10.2 SCR Latch-up Considerations ...................................................................................... 15
10.3 DC-DC Converter Considerations ................................................................................. 16
10.4 Power Supply Rejection ................................................................................................ 16
11. PIN DESCRIPTION ............................................................................................................... 17
12. ORDERING INFORMATION ................................................................................................ 19
13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 19
14. REVISION HISTORY ........................................................................................................... 19
15. PACKAGE DIMENSIONS ..................................................................................................... 20
2
DS577F1
CS4373
LIST OF FIGURES
Figure 2. Timing .............................................................................................................................. 7
Figure 1. Rise and Fall Times ......................................................................................................... 7
Figure 4. CS4373 System Connections.......................................................................................... 8
Figure 5. 2.5 Voltage Reference Circuit........................................................................................ 11
Figure 6. Test Mode 1................................................................................................................... 13
Figure 7. Test Mode 4................................................................................................................... 13
Figure 8. Test Mode 5................................................................................................................... 14
LIST OF TABLES
Table 1. Test Modes ..................................................................................................................... 13
Table 2. Attenuator Selection........................................................................................................ 15
Table 3. Attenuator Selection........................................................................................................ 18
Table 4. Mode Selection ............................................................................................................... 18
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVIC-
ES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN
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CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS
FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
DS577F1
3
CS4373
1. CHARACTERISTICS & SPECIFICATIONS
•
•
•
•
•
Min / Max characteristics and specifications are guaranteed over all Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and T = 25°C.
A
DGND = 0 V. All voltages with respect to 0 V.
Devices are connected as shown in Figure 4 on page 8 unless otherwise noted.
Tests performed using the TBS bitstream at TBSGAIN = 0x4B8F2, unless otherwise noted.
RECOMMENDED OPERATING CONDITIONS
Parameter
Positive Digital Power Supply
Symbol
Min
Typ
Max
Unit
VD
3.135
3.3
5.25
V
Positive Analog Power Supply
Negative Analog Power Supply
Voltage Reference
Single Supply
Dual Supplies
VA+
4.75
2.375
5
2.5
5.25
2.625
V
V
Single Supply
Dual Supplies
VA-
-0.25
-2.625
0
-2.5
0.25
-2.375
V
V
Single Supply
Dual Supply
VREF
-
-
2.5
2.5
-
-
V
V
Specified Temperature Range
ANALOG CHARACTERISTICS
T
-40
-
+85
°C
A
Parameter
Dynamic Performance
Symbol
Min
Typ
Max
Unit
SNR
110
114
-
dB
Dynamic Range (OUT±)
Unloaded
OUT
SNR
100
100
106
106
-
-
dB
dB
Dynamic Range (BUF±)
Unloaded
1 kΩ load
BUF
THD
-
-118
-112
dB
Total Harmonic Distortion (OUT±)
Total Harmonic Distortion (BUF±)
Unloaded
OUT
THD
-
-
-100
-90
-95
-85
dB
dB
Unloaded
1 kΩ load
BUF
Input Characteristics
Bit Rate (TDATA)
f
-
-
MCLK/8
-
-
bits/sec
Hz
TDATA
Full Scale Bandwidth
BW
200
-20
-
FS
Wideband Max Amplitude
One’s Density Input Range
(Note 1)
(Note 2)
A
-
-
dBFS
%
WB
IR
25
75
OD
Notes: 1. Max amplitude for operation above 200 Hz is TBSGAIN = 0x0078E5.
2. Specification guaranteed by design. These are the negative and positive full scale limits for the TDATA
bitstream.
4
DS577F1
CS4373
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Symbol
Min
Typ
Max
Unit
Analog Outputs
Differential Output Level
Absolute Accuracy
Relative Accuracy
Offset Error
V
-
-
-
-
-
-
-
±1
±0.2
-
5
V
P-P
DIF
ABS
REL
VOS
FSD
VOD
±2
±1.8
%FS
%FS
1
%FS
Full Scale Drift
(Note 3)
(Note 3)
5
-
ppm/°C
µV/°C
Offset Drift
1
-
R
1
-
-
-
-
kΩ
pF
Analog Output Load at BUF±
Load Resistance
Load Capacitance
L
100
C
L
Voltage Reference Input
VREF
(Note 4, 5) VREF
-
-
2.5
-
-
V
V
VREF Current
VREF
120
µA
I
Power Supplies
Power Supply Rejection
DC Power Supply Currents
(Note 6)
PSRR
90
-
-
dB
(Note 7 and 8)
Normal Power Mode
LPWR = 0; MCLK = 2.048 MHz
Analog
Digital
VA
VD
-
-
7.8
100
-
-
mA
µA
Low Power Mode
LPWR = 1; MCLK = 1.024 MHz
Analog
Digital
VA
VD
-
-
5.0
100
-
-
mA
µA
Power Down Mode
Sleep Mode
Analog
Digital
VA
VD
-
-
400
100
-
-
µA
µA
Analog
Digital
VA
VD
-
-
2
2
-
-
µA
µA
3. Specification is for the parameter over the specified temperature range and is for the CS4373 only and
does not include the effects of external components.
4. A 2.5 V voltage reference results in the highest dynamic range and best signal-to-noise performance,
though smaller reference voltages may be used.
5. VREF is defined as {(VREF+) - (VREF-)} and Inputs must satisfy: VA- < VREF- < VREF+ < VA+
6. Power Supply Rejection is tested by applying a 100 mV
50 Hz signal to each supply.
P-P
7. All outputs unloaded. All digital inputs forced to VD or GND respectively. VA+ = 5 V; VA- = 0;
VD+ = 3.3 V.
8. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
signal bandwidth by a factor of 2.
DS577F1
5
CS4373
DIGITAL CHARACTERISTICS
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Symbol
Min
0.6 * VD
0.0
Typ
Max
Unit
V
V
-
-
VD
0.8
±10
IH
V
V
IL
Input Leakage Current
I
-
±1
µA
in
ABSOLUTE MAXIMUM RATINGS
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Parameter
DC Power Supplies (Note 9, 10)
Symbol
Min
Max
Unit
Positive Digital
Positive Analog
Negative Analog
VD
VA+
VA-
-0.3
-0.3
-3.3
+6.8
+6.8
+0.3
V
V
V
Input Current, Any Pin Except Supplies
Input Current, Supplies
Output Current
(Note 11, 12)
(Note 12)
I
I
-
±10
±50
mA
mA
mA
mW
V
IN
IN
-
I
-
±25
OUT
Power Dissipation
(Note 13)
All Analog Pins
All Digital Pins
PDS
-
(VA-) - 0.5
-0.5
500
Analog Input Voltage
V
V
(VA+) + 0.5
(VD) + 0.5
85
INA
IND
Digital Input Voltage
V
Ambient Operating Temperature
Storage Temperature
T
-40
°C
A
T
-65
150
°C
stg
9. VA+ and VA- must satisfy {(VA+) - (VA-)} < +6.8 V.
10. VD and VA- must satisfy {(VD) - (VA-)} < +7.6 V.
11. Includes continuous over-voltage conditions at the analog input (AIN) pins.
12. Transient current of up to 100 mA can be safely tolerated without SCR latch-up.
13. Total power dissipation, including all input and output currents.
6
DS577F1
CS4373
SWITCHING CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
MCLK Frequency
(Note 14)
Normal Power Mode
Low Power Mode
f
-
-
2.048
1.024
-
-
MHz
MHz
c
MCLK Duty Cycle
DC
40
-
-
-
-
-
-
-
-
60
300
1
%
ps
ns
ns
ns
ns
ns
CLK
MCLK Jitter (In-band or aliased in-band)
MCLK Jitter (Out-of-band)
CKJ
IB
CKJ
-
OB
Rise Times:
Any Digital Input
Any Digital Input
t
-
50
50
-
rise
Fall Times:
t
-
fall
SYNC Setup Time to MCLK falling
SYNC Hold Time after MCLK falling
(Note 15)
t
20
20
mss
msh
t
-
Notes: 14. If MCLK is removed, the CS4373 enters a sleep mode state.
15. SYNC latched on MCLK falling edge, data output on next MCLK rising edge.
t
t
fall
rise
0.9*VD
0.1*VD
Figure 1. Rise and Fall Times
MCLK
(2.048 MHz)
MSYNC
t
0
TDATA
(256 kHz)
tmclk
tmss
tmsh
tmsync
ttdat
Figure 2. Timing
DS577F1
7
CS4373
INA-
INA+
MCLK
MCLK
OUTR+
OUTF+
INR1+
INF1+
MSYNC
MSYNC
INB-
Differential
Sensor
0.02µF
COG
0.02µF
COG
CS3301/
CS3302
INB+
MDATA1
MFLAG1
MDATA1
MFLAG1
OUTF-
INF1-
INR1-
LPWR
OUTR+
GAIN0
GAIN1
GAIN2
CS5372
INA-
INA+
OUTR+
OUTF+
INR2+
INF2+
MDATA2
MFLAG2
MDATA2
MFLAG2
INB-
Differential
Sensor
0.02µF
COG
0.02µF
COG
CS3301/
CS3302
INB+
OUTF-
INF2-
INR2-
LPWR
OUTR+
GAIN0
GAIN1
GAIN2
LPWR
CS5376A
INA-
INA+
MCLK
OUTR+
OUTF+
INR1+
INF1+
MSYNC
INB-
Differential
Sensor
0.02µF
COG
0.02µF
COG
CS3301/
CS3302
INB+
MDATA1
MFLAG1
MDATA3
MFLAG3
OUTF-
INF1-
INR1-
LPWR
OUTR+
GAIN0
GAIN1
GAIN2
CS5372
INA-
INA+
OUTR+
OUTF+
INR2+
INF2+
MDATA2
MFLAG2
MDATA4
MFLAG4
INB-
Differential
Sensor
0.02µF
COG
0.02µF
COG
CS3301/
CS3302
INB+
OUTF-
INF2-
INR2-
LPWR
OUTR+
GAIN0
GAIN1
GAIN2
LPWR
VA+
VD
0.01µF
0.01µF
VA-
VD
MCLK
10nF
COG
CAP+
SYNC
TDATA
LPWR
CAP-
BUF+
Switch
Control
BUF-
CS4373
MODE0
MODE1
MODE2
OUT+
OUT-
VA+
VA-
10 Ω
VREF+
VREF-
ATT0
ATT1
ATT2
VREF
VA-
DGND
100µF
0.01µF
VA-
0.01µF
Figure 4. CS4373 System Connections
8
DS577F1
CS4373
2. TERMINOLOGY
•
Dynamic Range (Signal-to-Noise Ratio) - Ratio of the rms magnitude of the theoretical full
scale signal to the integrated rms noise from DC to 400 Hz. The following formula is used to
calculate this value:
(
rms magnitude of full scale signal
SNR = 20log
(
rms magnitude of noise floor
•
Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the
powers of all harmonic frequencies from DC to 400 Hz. The following formula is used to cal-
culate this value:
(
sum of the powers of the harmonic frequencies
THD = 10log
(
power of the fundamental frequency
•
•
•
•
Full Scale Bandwidth - The bandwidth in which the converter can generate a full scale signal
while maintaining all performance specifications.
Wideband Max Amplitude - The maximum amplitude of the output signal beyond the full scale
band-width.
Differential Output Level - The peak-to-peak voltage between the analog output pins of the
converter.
Absolute Accuracy - Variation in the measured output voltage from the theoretical output volt-
age at each of the attenuation ranges. The following formula is used to calculate this value:
|
( |
measured attenuated voltage - theoretical attenuated voltage
theoretical attenuated voltage
•100%
absolute accuracy =
(
•
Relative Accuracy - Variation in the measured output voltage from the theoretical output volt-
age (relative to measured full scale signal with no attenuation) at each of the attenuation
ranges. The following formula is used to calculate this value:
|
( |
measured attenuated voltage - theoretical attenuated voltage
theoretical attenuated voltage (relative to the measured full scale voltage)
•100%
relative accuracy =
(
•
Offset Error - Variation from the theoretical common mode voltage generated by the convert-
er. The following formula is used to calculate this value:
|
( |
measured offset
theoretical full scale voltage
•100%
offset error =
(
•
•
Full Scale Drift - The variation of the measured full scale voltage across the specified temper-
ature range.
Offset Drift - The variation in the measured offset voltage across the specified temperature
range.
DS577F1
9
CS4373
and CS3302 for multiple test modes (See
Figure 4 on page 8 for typical connection).
These outputs can be attenuated to match the
gain ranges of the CS3301/3302 using ATT0,
ATT1, and ATT2.
3. GENERAL DESCRIPTION
The CS4373 DAC is designed to fully verify the
performance of the acquisition channel. Also,
the input switching arrangements allows for
verification of sensor source impedance and,
in the case a moving-coil geophone, basic pa-
rameters of the electro-mechanical transfer
function.
4.3 BUF+ / BUF-
BUF± are buffered differential outputs used to
test external sensors such as hydrophones or
geophones. These outputs are also attenuat-
ed internally with the ATT0, ATT1 and ATT2
pins to match the gain ranges of the CS3301
and CS3302 (See Figure 4 on page 8 for typi-
cal connection).
Test signals are typically generated by the
CS5376A or CS5378 digital filter. The
CS5376A/78 supplies TDATA with a ∆Σ bit-
stream at a rate of MCLK/8. The DAC recon-
structs the digital bitstream to analog.
The full scale output voltage of the DAC
matches the maximum input signal rating of
the CS3301 and the CS3302 amplifier. A pas-
sive, programmable attenuator provides out-
put levels that matches all gain settings of
CS3301 and CS3302 while preserving the S/N
of the DAC.
5. DIGITAL FILTER INTERFACE
The CS4373 is designed to operate with the
CS5376A or CS5378 digital filter. The
CS5376A/78 generates the master clock
(MCLK), the ∆Σ test bitstream (TDATA) and
the synchronization signal input (SYNC). Each
of these can be configured within the digital fil-
ter to fit the application requirements.
The DAC can be operated at full scale for sig-
nal frequencies up to 200 Hz. For frequencies
above 200 Hz the amplitude must be reduced
to -20 dB with respect to full scale.
5.1 Signal Bitstream Input - TDATA
TDATA is the test bitstream input for the
CS4373. It is a ∆Σ one’s density bitstream in-
put at a rate of MCLK/8. The digital filter has a
bitstream available on its TBSDATA pin. When
used with the CS5376A/78, TDATA can be
connected directly to TBSDATA for it’s bit-
stream generation.
4. ANALOG OUTPUTS
4.1 CAP+ / CAP-
The CS4373 DAC needs an anti-alias filter to
function properly. The filter is constructed with
resistors internal to the CS4373 and a capaci-
tor connected the CAP+ and CAP- pins. This
filter will eliminate out of band signals from the
OUT± and BUF± outputs.
5.2 Master Clock - MCLK
For proper operation, the CS4373 must be
provided with a CMOS compatible clock on the
MCLK pin. MCLK must have less than 300 ps
of in-band jitter to maintain full performance
specifications.
A 10 nF COG capacitor is required across
CAP±; other types of capacitors, such as X7R,
do not have the stability required. Using the
10 nF COG sets the -3 dB corner of the output
anti-alias filter to 40 kHz.
When used with the CS5376A/78 digital filters,
MCLK is automatically generated and is typi-
cally 2.048 MHz or 1.024 MHz.
4.2 OUT+ / OUT-
The OUT± pins are high precision, high output
impedance differential outputs designed to
test external electronics within the chip set.
These outputs directly interface to the CS3301
10
DS577F1
CS4373
5.3 Clock Sync Input - SYNC
defined relative to the VA- supply (see
Figure 5).
To synchronize the timing of the digital input
bitstream, the CS4373 uses a SYNC signal.
When using the CS5376A/78 digital filters,
SYNC is automatically generated from a
SYNC signal input from the external system.
The selected voltage reference should pro-
duce less than 1 µVrms of noise in the mea-
surement bandwidth on the VREF+ pin. The
digital filter output word rate selection deter-
mines the bandwidth over which voltage refer-
ence noise affects the CS4373 dynamic
range.
The CS4373 SYNC input is rising edge trig-
gered and resets the internal MCLK counter-
divider.
6.2 Voltage Reference Configurations
6. VOLTAGE REFERENCE
For a 2.5 V reference, the Linear Technology
LT1019-2.5 voltage reference yields low
enough noise if the output is filtered with a low
pass RC filter as shown in Figure 5.
6.1 Voltage Reference Inputs
The CS4373 is designed to operate with a
2.5 V voltage reference applied across the
VREF+ and VREF- pins.
6.3 VREF Input Impedance
In a single supply power configuration the
VREF+ pin should be connected to the voltage
reference output, and the VREF- pin connect-
ed to ground. In a dual supply power configu-
ration the voltage reference should be
powered from the VA+ and VA- supplies, with
the VREF+ pin connected to the voltage refer-
ence output and the VREF- pin connected to
VA-. Because most 2.5 V voltage references
require a power supply voltage greater than
3 V to operate, when powering the voltage ref-
erence from dual ±2.5 V supplies the refer-
ence voltage into the VREF+ pin should be
The switched-capacitor input architecture of
the VREF+ pin causes the input current re-
quired from the voltage reference to change
any time MCLK is changed. The input imped-
ance of the voltage reference input is calculat-
ed similar to the analog signal input
impedance as [1 / (f * C)] where f is the master
clock frequency, MCLK, and C is the internal
sampling capacitor. A 2.048 MHz MCLK yields
a voltage reference input impedance of ap-
proximately [1 / (2.048 MHz)*(20 pF)], or
about 24 kΩ.
VA+
µ
F
0.1
Ω
10
LT1019-2.5
2.5V REF
To VREF+
µ
µ
F
0.1
F
100
+
To VREF-
VA-
µ
F
0.1
Figure 5. 2.5 Voltage Reference Circuit
DS577F1
11
CS4373
6.4 Gain Accuracy
be changed, the voltage reference should be
buffered to have a low output impedance to
minimize the effect of the resistive
voltage divider.
Gain accuracy of the CS4373 is affected by
variations of the voltage reference input. A
change in the voltage reference input imped-
ance due to a change in MCLK could affect
gain accuracy when using the higher source
impedance configuration of Figure 5. The
VREF+ pin input impedance and the external
low-pass filter resistor create a voltage divider
for the output reference voltage, reducing the
effective voltage reference input. If gain error
is to be minimized, especially when MCLK is to
6.5 Gain Drift
Gain drift of the CS4373 due to temperature
does not include the temperature drift charac-
teristics of the external voltage reference. Gain
drift is not affected by the sample rate or by
power supply variations.
12
DS577F1
CS4373
7.1 Test Mode 0: Reserved
7. TEST MODES
7.2 Test Mode 1: Sensor Test Mode
The CS4373 has 7 test modes. The MODE0,
MODE1, and MODE2 pins define which mode
the part will operate. Table 1 lists the test
mode options and corresponding MODE pin
settings.
This mode is used to test an external sensor
such as a hydrophone or geophone. Both the
BUF± and OUT± are active outputs; and im-
pulse response, linearity, and sensor imped-
ance can be measured in the Sensor Test
Mode. See Figure 6 for a typical connection di-
The following subsections explain the CS4373
Test Mode Options:
agram.
.
MODE2 MODE1 MODE0
Test Mode 0
Test Mode 1
Test Mode 2
Test Mode 3
Test Mode 4
Test Mode 5
Test Mode 6
Test Mode 7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Sensor Test Mode (OUT± AND BUF±)
Electronics Test (OUT± ONLY)
Sensor Test (BUF± ONLY)
Common Mode
High Voltage/High Current Mode
Reserved
Sleep Mode
Table 1. Test Modes
C S 4 3 7 3
C S 4 3 7 3
CAP+
CAP-
CAP+
CAP-
10nF
COG
10nF
COG
R
R
BUF+
BUF-
R
R
BUF+
BUF-
Hydrophone
or
Geophone
Hydrophone
or
Geophone
OUT+
OUT-
OUT+
OUT-
C S 3 3 0 1 /
C S 3 3 0 2
C S 3 3 0 1 /
C S 3 3 0 2
INA+
INA-
INA+
INA-
INB+
INB-
INB+
INB-
Figure 7. Test Mode 4
Figure 6. Test Mode 1
DS577F1
13
CS4373
By placing known resistances on both BUF+
and BUF- (each side of the sensor) the voltage
at the buffered outputs (BUF+ and BUF-) can
be measured through the CS3301 or CS3302
and compared to the voltage on the precision
outputs (OUT+ and OUT-). From these mea-
surements the leakage current of the sensor
can be determined
7.6 Test Mode 5: High Voltage/High
Current Mode
This mode allows connection of the OUT± pins
to high voltage or high current electronics.
Figure 8 shows a typical connection diagram
for this operational mode. The CS3301 and
CS3302 amplifiers can be used in the configu-
ration as the precision buffers. When using the
circuit in Figure 8, the gain of the circuit is de-
fined as:
Linearity can also be measured from the out-
put of OUT±. And when connected to the digi-
tal filter, a digital impulse bitstream can be fed
directly to the CS4373 to test the impulse re-
sponse of the system.
V2
V1
2R1
R2
AV =
= 1+
(
)
7.3 Test Mode 2: Electronics Test Mode
In this test mode, outputs BUF± are high-Z and
only OUT± is available. BUF± become high im-
pedance to protect any external sensors still
connected. This mode can be used to test oth-
er system electronics on the board. It should
be noted that since only OUT± can be used in
this mode, and OUT± are unbuffered outputs,
OUT± can only be connected to a high imped-
ance load, such as the CS3301 and CS3302
amplifiers.
CAP+
CAP-
10nF
COG
CS4373
BUF+
BUF-
+
-
R1
R2
7.4 Test Mode 3: Sensor Test Mode
OUT+
OUT-
High Current/
High Voltage
Electronics
As opposed to Test Mode 1, in this mode
BUF± are the only available outputs. This
mode offers another option to test external cir-
cuitry. While operating in Test Mode 3, OUT±
are high impedance to ensure no interference.
V2
V1
R1
-
+
7.5 Test Mode 4: Common Mode
Figure 8. Test Mode 5
In this mode the system can be tested using a
common mode output from both BUF± and
OUT±. Figure 7 shows BUF± and OUT± con-
nections internal to the CS4373. Again, since
the OUT± pins are unbuffered, they must only
be connected to a high impedance load, such
as the CS3301 and CS3302.
7.7 Test Mode 6: Reserved
7.8 Test Mode 7: Sleep Mode
In this mode the chip is put into a low power
sleep mode (See Section 9, "Power Modes"
on page 15 for more).
14
DS577F1
CS4373
high impedance state.
8. ATTENUATION SETTINGS
The DAC outputs can be attenuated to match
the gain ranges of the CS3301 and CS3302
amplifiers. Using pins ATT0, ATT1 and ATT2,
the outputs of the DAC can be set to one of
7 attenuation options. Table 2 shows each at-
tenuation option.
9.4 Power Down
The CS4373 is automatically placed into pow-
er down if MCLK is disabled. It is equipped
with loss of clock detection circuitry to force
power down if MCLK is removed. In power
down the DAC is inactive and the analog out-
puts are placed in a high impedance state.
When used with the CS5376A or CS5378 the
CS4373 will be in this state upon power-up
since MCLK is disabled by default.
Attenuation
Selection
ATT2
ATT1
ATT0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/2
1/4
10. POWER SUPPLY
1/8
The CS4373 has one positive analog power
supply pin, VA+, one negative analog power
supply pin, VA-, one digital power supply pin,
VD, and one digital ground pin, DGND. The
analog and digital circuitry are separated inter-
nally to enhance performance, therefore pow-
er must be supplied to all three supply pins.
The digital ground pin must be connected to
system ground.
1/16
1/32
1/64
Reserved
Table 2. Attenuator Selection
9. POWER MODES
Five power modes are available when using
the CS4373. Normal, low power modes are
operational modes; power down and sleep
mode are non-operational standby modes.
When used with the CS5376A or CS5378 dig-
ital filter the maximum voltage differential be-
tween the CS4373 digital supply, VD, and the
I/O supplies, (VDD1, VDD2, VDDPAD) must
be 0.3 V or less.
9.1 Normal Power Mode
The normal operational mode for the CS4373,
LPWR=0 and MCLK=2.048 MHz, provides the
best performance with low power consump-
tion. This power mode is recommended when
maximum performance is required.
10.1 Power Supply Bypassing
The analog supply pins, VA+, VA-, should be
decoupled to system ground with a 0.1 µF ca-
pacitor; while the digital supply pin, VD, should
be decoupled to system ground with a 0.01 µF
capacitor. Bypass capacitors can be X7R, tan-
talum, or any other dielectric types.
9.2 Low Power Mode
The CS4373 has a low-power operational
mode, LPWR = 1 and MCLK = 1.024 MHz,
that reduces power consumption at the ex-
pense of 3 dB SNR. This operational mode is
recommended when minimizing power is more
important than maximizing SNR.
10.2 SCR Latch-up Considerations
The VA- pin is tied to the CS4373 CMOS sub-
strate and should always be connected to the
most negative supply voltage to ensure SCR
latch-up does not occur. In general, latch-up
may occur when any pin voltage (including the
analog inputs) is 0.7 V or more below VA-, or
7.6 V or more above VA-.
9.3 Sleep Mode
When selecting Test Mode 7, the CS4373 will
be put in a sleep mode in which the DAC is in-
active. Each analog output is placed into a
DS577F1
15
CS4373
When using dual analog power supplies, it is
recommended to connect the VA- power
supply pin to system ground (DGND) using a
reversed biased Schottky diode. This configu-
ration clamps the VA- voltage a maximum of
0.3 V above ground to ensure SCR latch-up
does not occur during power up. If the VA+
power supply ramps before the VA- supply,
the VA- voltage could be pulled above ground
through the CS4373. If the VA- supply is unin-
tentionally pulled 0.7 V above the DGND pin,
SCR latch-up can occur.
frequencies” to appear in the measurement
bandwidth. However this requires the source
clock to remain jitter-free within the DC-DC
converter circuitry. If clock jitter can occur with-
in the DC-DC converter (as in a PLL-based ar-
chitecture), it’s better to use a non-
synchronous DC-DC converter whose switch-
ing frequency is rejected by the digital filter.
During PCB layout, do not place high-current
DC-DC converters near sensitive analog com-
ponents. Carefully routing a separate DC-DC
“star” ground will help isolate noisy switching
currents away from the sensitive analog com-
ponents.
10.3 DC-DC Converter Considerations
Many low-frequency measurement systems
are battery powered and utilize DC-DC con-
verters to efficiently generate power supply
voltages. To minimize interference effects, op-
erate the DC-DC converter at a frequency
which is rejected by the digital filter, or operate
it synchronous to the MCLK rate.
10.4 Power Supply Rejection
Power supply rejection of the CS4373 is fre-
quency dependent. The digital filter rejects
power supply noise for frequencies above the
filter corner frequency at 130 dB or greater.
For frequencies between DC and the digital fil-
ter corner frequency, power supply rejection is
nearly constant at 90 dB.
A synchronous DC-DC converter whose oper-
ating frequency is derived from MCLK will the-
oretically minimize the potential for “beat
16
DS577F1
CS4373
11.PIN DESCRIPTION
Positive Capacitor Output
Negative Capacitor Output
Positive Buffered Output
CAP+
CAP-
BUF+
BUF-
OUT+
OUT-
VA+
LPWR
MODE0
MODE1
MODE2
ATT0
Low Power Mode Enable
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Mode Select
2
Mode Select
3
Negative Buffered Output
Mode Select
4
Positive High Precision Output
Negative High Precision Output
Positive Analog Power Supply
Negative Analog Power Supply
Attenuation Range Select
Attenuation Range Select
Attenuation Range Select
Signal Bitstream Input
Positive Digital Power Supply
Digital Ground
5
ATT1
6
ATT2
7
VA-
TDATA
VD
8
Negative Voltage Reference VREF-
Positive Voltage Reference VREF+
9
DGND
MCLK
SYNC
DNC
10
11
12
13
14
No Connect
No Connect
No Connect
No Connect
NC
NC
NC
NC
Master Clock Input
Clock Sync Input
Do Not Connect
DNC
Do Not Connect
Pin Name
Pin # I/O
Pin Description
CAP+, CAP- 1, 2
BUF+, BUF- 3, 4
OUT+, OUT- 5, 6
O
O
O
I
External Capacitor Connection for Test DAC anti-alias filter
Buffered Output from the Test DAC
High precision output from the Test DAC
VA+, VA-
7, 8
Power supply for the analog section. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
VREF-,
VREF+
9, 10
I
Voltage reference for the internal sampling circuits. Refer to the Recommended Operating Condi-
tions for appropriate voltages.
SYNC
MCLK
DGND
VD
17
18
19
20
I
I
I
I
Clock Sync Input - A low to high transition resets the internal clock phasing of the DAC.
Master Clock Input - a CMOS compatible clock input for the DAC internal master clock.
Digital Ground - Ground reference for the digital section.
Power supply for the digital section. Refer to the Recommended Operating Conditions for appropri-
ate voltages.
LPWR
TDATA
28
24
I
I
Low Power Mode Select - When set high the CS4373 enters into a Low Power Mode. (See Section
Section 9, "Power Modes" on page 15 for more on Power Modes)
Test DAC Signal Bitstream Input.
DS577F1
17
CS4373
Pin Name
Pin # I/O
I
Pin Description
ATT2, ATT1, 21,
Attenuation Range Select - Selects the internal attenuation range as detailed in Table 3.
ATT0
22, 23
Attenuation
Selection
ATT2
ATT1
ATT0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/2
1/4
1/8
1/16
1/32
1/64
reserved
Table 3. Attenuator Selection
Mode Selection - Determines the operational mode (0 - 7) of the device as detailed in Table 4.
MODE2,
MODE1,
MODE0
25,
26, 27
I
Mode Selection
Test Mode 0
Test Mode 1
Test Mode 2
Test Mode 3
Test Mode 4
Test Mode 5
Reserved
Mode
Reserved
MODE2
MODE1
MODE0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sensor Test
OUT±
BUF±
Common Mode
High Voltage
Reserved
Test Mode 7
Chip Power Down
Table 4. Mode Selection
18
DS577F1
CS4373
12.ORDERING INFORMATION
Model
Temperature
Package
CS4373-IS
-40 to +85 °C
28-pin SSOP
13.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
CS4373-IS
Peak Reflow Temp
MSL Rating*
Max Floor Life
240 °C
2
365 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
14.REVISION HISTORY
Revision
PP1
Date
Changes
MAR 2003
SEP 2005
Initial preliminary release.
F1
Final version. MSL data added.
DS577F1
19
CS4373
15.PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
NOM
--
0.006
0.069
--
0.4015
0.307
0.209
0.026
0.0354
4°
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
--
MAX
0.084
0.010
0.074
0.015
0.413
0.323
0.220
0.030
0.041
8°
MIN
--
NOM
--
0.15
1.75
--
10.20
7.80
5.30
0.65
0.90
4°
MAX
2.13
0.25
1.88
0.38
10.50
8.20
5.60
0.75
1.03
8°
0.002
0.064
0.009
0.390
0.291
0.197
0.022
0.025
0°
0.05
1.62
0.22
9.90
7.40
5.00
0.55
0.63
0°
2,3
1
1
∝
JEDEC #: MO-150
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
20
DS577F1
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