CS495313-CVZ [CIRRUS]
32-bit Audio Decoder DSP Family with Dual DSP Engine Technology; 32位音频解码器DSP系列采用双DSP引擎技术
| 型号： | CS495313-CVZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 32-bit Audio Decoder DSP Family with Dual DSP Engine Technology |
| 文件： | 总38页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4953xx Data Sheet
FEATURES
32-bit Audio Decoder DSP Family
with Dual DSP Engine Technology
Multi-standard 32-bit Audio Decoding plus Post
Processing
The CS4953xx DSP family are the enhanced versions of the
CS495xx DSP family with higher overall performance and
lower system cost. The CS4953xx includes all mainstream
audio processing codes in on-chip ROM. This saves external
memory for code storage. In addition, the intensive decoding
tasks of Dolby Digital® Surround EX®, AAC multi-channel,
DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone
can be accomplished without the expense of external
SDRAM memory. With larger internal memories than the
CS495xx, the CS49531x is designed to support up to 150 ms
per channel of lip-sync delay. With 150 MHz internal clock
speed, the CS4953xx supports the most demanding post-
processing requirements. It is also designed for easy
upgrading. Customers currently using the CS495xx can
upgrade to the CS4953xx with minor hardware and software
changes.
Framework™ Applications Library in ROM
— Dolby Digital® EX, Dolby® Pro Logic® IIx, Dolby Headphone®,
Dolby® Virtual Speaker®
— DTS-ES 96/24™, DTS-ES™ Discrete 6.1, DTS-ES™ Matrix 6.1,
DTS:Neo6™
— AAC™ Multichannel 5.1
— SRS® CS2® and TSXT®
— THX® Ultra2™, THX® ReEQ™
— Cirrus Original Multi-Channel Surround (COMS)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processor including: 7.1Bass Manager, Tone
Control, 12- Band Parametric EQ, Delay, 1:2 Upsampler
— Microsoft® HDCD®
Framework™ Applications for Download
Ordering Information
— Thomson MP3 Surround
— Internal DSD-to-PCM Conversion
Up to 12 Channels of 32-bit Serial Audio Input
See page 31 for ordering information
6 Channel DSD Input
16 Ch x 32-bit PCM Out with either two 192 kHz S/PDIF
Tx (144-pin package) or one 192 kHz S/PDIF Tx (128-pin
package)
Two SPI™/I2C®, One Parallel and One UART Port
Customer Software Security Keys
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial/Parallel Flash Memory Support
Serial
Control 1
Serial
Control 2
Parallel
Control
UART
GPIO
Debug
12 Ch. Audio In /
6 Ch. SACD In
STC
TMR1
TMR2
D
M
A
32-bit
DSP A
32-bit
DSP B
S/PDIF S/PDIF
P
X
Y
P
X
Y
16 Ch PCM
Audio Out
PLL
Ext. Memory Controller
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
®Copyright 2008 Cirrus Logic, Inc.
JUNE ’08
DS705PP2
http://www.cirrus.com
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Table of Contents
1. Documentation Strategy ...........................................................................................................4
2. Overview ....................................................................................................................................4
2.1 Migrating from the CS495xx(2) to the CS4953xx .....................................................................................4
2.2 Licensing ..................................................................................................................................................4
3. Code Overlays ...........................................................................................................................5
4. Hardware Functional Description ...........................................................................................7
4.1 DSP Core .................................................................................................................................................7
4.1.1 DSP Memory ...............................................................................................................................7
4.1.2 DMA Controller ............................................................................................................................7
4.2 On-chip DSP Peripherals .........................................................................................................................8
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................8
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................8
4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™) .....................................................................................8
4.2.4 Parallel Control Port ....................................................................................................................8
4.2.5 External Memory Interface ..........................................................................................................8
4.2.6 GPIO ............................................................................................................................................8
4.2.7 PLL-based Clock Generator ........................................................................................................8
4.3 DSP I/O Description .................................................................................................................................9
4.3.1 Multiplexed Pins ..........................................................................................................................9
4.3.2 Termination Requirements ...........................................................................................................9
4.3.3 Pads ............................................................................................................................................9
4.4 Application Code Security ........................................................................................................................9
5. Characteristics and Specifications .......................................................................................10
5.1 Absolute Maximum Ratings ....................................................................................................................10
5.2 Recommended Operating Conditions ....................................................................................................10
5.3 Digital DC Characteristics ......................................................................................................................10
5.4 Power Supply Characteristics ................................................................................................................ 11
5.5 Thermal Data (144 LQFP) ...................................................................................................................... 11
5.6 Thermal Data (128 LQFP) ...................................................................................................................... 11
5.7 Switching Characteristics— RESET ....................................................................................................... 11
5.8 Switching Characteristics — XTI ............................................................................................................12
5.9 Switching Characteristics — Internal Clock ............................................................................................13
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode. ....................................................14
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ...................................................15
5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode ......................................................16
5.13 Switching Characteristics — Serial Control Port - I2C Master Mode ....................................................17
5.14 Switching Characteristics — Parallel Control Port - Intel® Slave Mode ..............................................18
5.15 Switching Characteristics — Parallel Control Port - Motorola® Slave Mode .......................................20
5.16 Switching Characteristics — UART ......................................................................................................22
5.17 Switching Characteristics — Digital Audio Slave Input Port .................................................................23
5.18 Switching Characteristics — DSD Slave Input Port ............................................................................24
5.19 Switching Characteristics — Digital Audio Output Port ........................................................................24
5.20 Switching Characteristics — External Memory Interface - Flash Mode ...............................................26
5.21 Switching Characteristics — SDRAM Interface ....................................................................................28
6. Ordering Information ..............................................................................................................31
7. Environmental, Manufacturing, & Handling Information ....................................................31
8. Device Pinout Diagrams .........................................................................................................32
8.1 128-Pin LQFP Pinout Diagram ...............................................................................................................32
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®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
8.2 144-Pin LQFP Pinout Diagram ...............................................................................................................33
9. Package Mechanical Drawings ..............................................................................................34
9.1 128-pin LQFP Package Drawing ............................................................................................................34
9.2 144-Pin LQFP Package ..........................................................................................................................35
10. Revision History ....................................................................................................................36
List of Figures
Figure 1. RESET Timing ........................................................................................................................................12
Figure 2. XTI Timing ..............................................................................................................................................12
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15
Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16
Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17
Figure 7. Parallel Control Port - Intel® Mode Read Cycle ......................................................................................19
Figure 8. Parallel Control Port - Intel Mode Write Cycle ........................................................................................19
Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing ...................................................................21
Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing ...................................................................21
Figure 11. UART Timing ........................................................................................................................................22
Figure 12. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................23
Figure 13. Direct Stream Digital - Serial Audio Input Timing ..................................................................................24
Figure 14. Digital Audio Port Timing, MCLK Master Mode ....................................................................................25
Figure 15. External Memory Interface - Flash Write Cycle Timing .........................................................................27
Figure 16. External Memory Interface - Flash Read Cycle Timing ........................................................................27
Figure 17. External Memory Interface - SDRAM Burst Read Cycle .......................................................................29
Figure 18. External Memory Interface - SDRAM Burst Write Cycle .......................................................................29
Figure 19. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................30
Figure 20. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................30
Figure 21. 128-Pin LQFP Pin-Out Drawing ............................................................................................................32
Figure 22. 144-Pin LQFP Pin-Out Drawing ............................................................................................................33
Figure 23. 128-Pin LQFP Package Drawing .........................................................................................................34
Figure 24. 144-Pin LQFP Package Drawing .........................................................................................................35
List of Tables
Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. CS495303 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. CS495313 DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Environmental, Manufacturing, & Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. 128-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. 144-Pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
3
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
1. Documentation Strategy
The CS4953xx Datasheet describes the CS4953xx family of multichannel audio decoders. This document
should be used in conjunction with the following documents when evaluating or designing a system around the
CS4953xx family of processors.
Table 1. CS4953xx Related Documentation
Document Name
Description
CS4953xx Datasheet
This document
Includes detailed system design information including
Typical Connection Diagrams, Boot-Procedures, Pin
Descriptions, Etc.
CS4953xx Hardware User’s Manual
Includes detailed firmware design information
including signal processing flow diagrams and control
API information
AN288 - CS4953xx Firmware User’s Manual
The scope of the CS4953xx Datasheet is primarily the hardware specifications of the CS4953xx family of
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS4953xx Data Sheet is the system PCB designer, mcu programmer, and the
quality control engineer.
2. Overview
The CS4953xx DSP Family, together with Cirrus Logic’s comprehensive library of audio processing algorithms,
enables the development of next-generation audio solutions. Cirrus Logic also provides a broad array of digital
interface products, audio converters, and ARM® Processors to meet your audio system-level design
requirements.
There are two devices in the CS4953xx DSP family. The CS495303 and CS495313 are differentiated by
internal memory size and DSP Firmware. The CS495303 is available in a 128-pin QFP package and the
CS495313 is available in either a 128-pin or 144-pin QFP package. The audio processing features of the
CS495313 are a superset of audio features available in the CS495303. Please refer to Table 2 on page 6 for
the speed and firmware features of each device.
2.1 Migrating from the CS495xx(2) to the CS4953xx
The CS4953xx was designed to provide an easy upgrade path from the CS495xx(2). Although 144-pin
versions of the two devices are virtually identical with respect to external system connection, there are some
small differences the hardware designer should be aware of:
• The PLL supply voltage on the CS4953xx is 3.3V vs. 1.8V on the CS495xx(2).
• The PLL filter topology is simpler when using the CS4953xx rather than the CS495xx(2).
• The CS4953xx adds support for 6-channel DSD input.
• The CS4953xx adds support for TDM mode on both audio input and output ports.
• The CS4953xx does not support external SRAM operation.
• The CS4953xx external SDRAM bus speed is fixed at 150 MHz vs. the 120 MHz max bus speed for the
CS495xx(2). Some firmware modules also support a 75 MHz CS4953xx SDRAM bus speed. Please refer
to AN288 for details.
• The CS4953xx CLKOUT pin can output XTALI or XTALI/2. The CS495xx(2) can only output XTALI.
2.2 Licensing
Licenses are required for all of the 3rd party audio decoding/processing algorithms listed below, including the
application notes. Please contact your local Cirrus Sales representative for more information.
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®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
3. Code Overlays
The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of
overlays. The overlays have been divided into three main groups called Decoders, Mid-processors, and Post-
processors. All software components are defined below:
1. OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,
processing host messages, calling audio-processing subroutines, error concealment, etc.
2. Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3®, DTS, PCM, etc. All the
decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed, compressed data
via I2S- or LJ-formatted digital audio to the CS4953xx.
3. Mid-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-
processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer
through processes like Virtualization (nÖ2 channels) or Matrix Decoding (2Ön channels). Examples are Dolby
ProLogic IIx and DTS Neo:6.
4. Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Mid-Processors.
Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-specific Effects, Dolby
Headphone/Virtual Speaker, etc.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For example,
when a new decoder is selected, the OS, mid-, and post-processors do not need to be reloaded — only the
new decoder (the same is true for the other overlays).
Table 2 below lists the firmware available based on device selection. Please refer AN288 CS4953xx Firmware
User’s Manual for the latest listing of application codes and Cirrus Framework™ modules available.
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
5
Table 2. Device and Firmware Selection Guide1
Pre-
Process
Device
Decode Processor A
Mid-processor A
Mid-processor B
Post-processor B
Dolby PLIIx
Stereo PCM
®
Circle Surround II
Dolby Headphone
Dolby Virtual Speaker
SRSTruSurround XT
THX Select
Multi-Channel PCM
(2:1 Down-sampling Option)
(Stereo In)
CS495303
APP
Cirrus Original Multi-
Channel Surround (Effects
/ Reverb Processor)
N/A
(Advanced Post-processing)
300 MIPS
Dolby Digital
AAC
–Tone Control
–Re-EQ
–PEQ (up to 11 Bands)
–Delay
–7.1 Bass Manager
–Audio Manager
MP3
HDCD
Down-mix
(Simultaneous Process)
CS495313
(Superset of
CS495303)
Same as CS495303 +
DTS
Same as CS495303 +
1:2 Up-sampling
Lip Sync
Delay
Same as CS495303 +
THX Ultra2
DTS Neo:6
(Stereo In)
DTS-ES
DTS 96/24
300 MIPS
1.This feature list is a snapshot of features available as of the publication date of this revision of the data sheet. More features may
now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS495303
and CS495313 products.
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
4. Hardware Functional Description
4.1 DSP Core
The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a
high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two memory
access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-
data registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core
memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP
core, leaving more MIPS available for signal processing instructions.
CS4953xx functionality is controlled by application codes that are stored in on-board ROM or downloaded to
the CS4953xx from a host mcu or external FLASH/EEPROM. Users can choose to use standard audio
decoder and post-processor modules which are available from Cirrus Logic.
The CS4953xx is suitable for Audio Decoder, Audio Post-processor, Audio Encoder, DVD Audio/Video Player,
and Digital Broadcast Decoder applications.
4.1.1 DSP Memory
Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory
for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES
96/24, and THX Ultra2.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
Table 3. CS495303 DSP Memory Sizes
Memory
DSP A
DSP B
Type
X
Y
P
16k SRAM, 16k ROM
16k SRAM, 32k ROM
8k SRAM, 32k ROM
10k SRAM, 8k ROM
16k SRAM, 16k ROM
8k SRAM, 24k ROM
Table 4. CS495313 DSP Memory Sizes
Memory
Type
DSP A
DSP B
X
Y
P
16k SRAM, 16k ROM
24k SRAM, 32k ROM
8k SRAM, 32k ROM
10k SRAM, 8k ROM
16k SRAM, 16k ROM
8k SRAM, 24k ROM
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource has its
own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and the
peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and increment
controls. The service interval for each DMA channel as well as up to 6 interrupt events, is programmable.
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6 line) DAI port supports a wide variety of data input formats. The port is capable of accepting
PCM, IEC61937, or DSD. Up to 32-bit word lengths are supported. Up to 6 channels of DSD are supported and
internally converted to PCM before processing.
The port has two independent slave-only clock domains. Each data input can be independently assigned to a
clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which
off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input
data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
There are two DAO ports. Each port can output 8 channels of up to 32-bit PCM data. The port supports data
rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave mode, or
the ratio of the two clocks can be set to even multiples of each other in master mode. The two ports can also be
ganged together into a single clock domain. Each port has one serial audio pin that can be configured as a 192
kHz S/PDIF transmitter (data with embedded clock on a single line).
Note: Only one S/PDIF transmitter pin is available in the 128-pin package.
4.2.3 Serial Control Port 1 & 2 (I2C® or SPI™)
There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI
modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external
clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed
enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for
booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the
SCP2_BSY# pin in the 128-pin package.
4.2.4 Parallel Control Port
The CS4953xx parallel port supports both Motorola® and Intel® interfaces. It can be used for both control and
data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin
package.
4.2.5 External Memory Interface
The external memory interface controller supports up to 128 Mbits of SDRAM, using a 16-bit data bus. The
memory controller supports up to 1 MB of Flash memory in 8-bit data bus-width mode or 2 MB in 16-bit data
bus-width mode.
4.2.6 GPIO
Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,
an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,
active-low, or active-high.
4.2.7 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit
with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or
2:1.
8
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4953xx pins are multi-functional. For details on pin functionality please refer to the CS4953xx
Hardware User’s Manual.
4.3.2 Termination Requirements
Open-drain pins on the CS4953xx must be pulled high for proper operation. Please refer to the CS4953xx
Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for
proper operation.
Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4953xx Hardware User’s Manual.
4.3.3 Pads
The CS4953xx I/O operates from the 3.3 V supply and is 5V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
9
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5. Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and
temperature. All data sheet typical parameters are measured under the following conditions:
T = 25 °C, CL = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
-
2.0
3.6
3.6
0.3
V
V
V
V
|VDDA – VDDIO|
Input pin current, any pin except supplies
Input voltage on PLL_REF_RES
Input voltage on I/O pins
Iin
-
+/- 10
3.6
mA
V
Vfilt
Vinio
Tstg
-0.3
-0.3
–65
5.0
V
Storage temperature
150
°C
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
|VDDA – VDDIO|
Ambient operating temperature
TA
-
°C
0
- 40
+ 70
+ 85
- CQ
- DQ
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
Parameter
High-level input voltage
Symbol
VIH
Min
Typ
Max
-
Unit
V
2.0
-
-
Low-level input voltage, except XTI
Low-level input voltage, XTI
Input Hysteresis
VIL
-
-
0.8
0.6
V
VILXTI
Vhys
-
V
0.4
-
V
High-level output voltage (IO = -4mA), except XTI,
SDRAM pins
VOH
VDDIO * 0.9
-
-
V
Low-level output voltage (IO = 4mA), except XTI, SDRAM
pins
VOL
-
VDDIO * 0.1
V
SDRAM High-level output voltage (IO = -8mA)
SDRAM Low-level output voltage (IO = 8mA)
VOH
VOL
IIN
VDDIO * 0.9
-
-
-
-
V
V
-
-
VDDIO * 0.1
5
Input leakage current (all digital pins with internal pull-up
resistors disabled)
μA
Input leakage current (all digital pins with internal pull-up
resistors enabled, and XTI)
IIN-PU
-
-
50
μA
10
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.4 Power Supply Characteristics
(measurements performed under operating conditions)
Parameter
Min
Typ
Max
Unit
Power supply current:
Core and I/O operating: VDD1
PLL operating: VDDA
With external memory and most ports operating: VDDIO
-
-
-
500
3.5
120
-
-
-
mA
mA
mA
1. Dependent on application firmware and DSP clock speed.
5.5 Thermal Data (144 LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
Two-layer Board1
θja
°C / Watt
-
-
48
40
-
-
Four-layer Board2
Thermal Resistance (Junction to Top of Package)
Two-layer Board1
ψjt
°C / Watt
-
-
.39
.33
-
-
Four-layer Board2
5.6 Thermal Data (128 LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
Two-layer Board1
θja
°C / Watt
-
-
53
44
-
-
Four-layer Board2
Thermal Resistance (Junction to Top of Package)
Two-layer Board1
ψjt
°C / Watt
-
-
.45
.39
-
-
Four-layer Board2
Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 %
of the top & bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 %
of the top & bottom layers and 0.5-oz copper covering 90 % of the internal power plane and ground plane layers.
3. To calculate the die temperature for a given power dissipation
4. Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]
5. To calculate the case temperature for a given power dissipation
6. Τc = Τj - [ (Power Dissipation in Watts) * ψ jt ]
5.7 Switching Characteristics— RESET
Parameter
RESET# minimum pulse width low
Symbol
Trstl
Min
1
Max
Unit
μs
-
All bidirectional pins high-Z after RESET# low
Configuration pins setup before RESET# high
Configuration pins hold after RESET# high
Trst2z
-
100
ns
Trstsu
50
20
-
-
ns
Trsthld
ns
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
11
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
RESET#
HS[3:0]
All Bidirectional
Pins
Trstsu
Trsthld
Trst2z
Trstl
Figure 1. RESET Timing
5.8 Switching Characteristics — XTI
Parameter
External Crystal operating frequency1
XTI period
Symbol
Fxtal
Min
11.2896
33.3
Max
27
100
-
Unit
MHz
ns
Tclki
XTI high time
Tclkih
Tclkil
13.3
ns
XTI low time
13.3
-
ns
External Crystal Load Capacitance (parallel resonant)2
CL
10
18
50
pF
External Crystal Equivalent Series Resistance
ESR
W
1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z.
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside
this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s
recommendation for load capacitor selection.
XTI
tclkih
tclkil
Tclki
Figure 2. XTI Timing
12
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.9 Switching Characteristics — Internal Clock
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DQZ
CS49531x-DVZ
Fdclk
-
MHz
Fxtal
Fxtal
Fxtal
Fxtal
Fxtal
Fxtal
150
150
150
TBD
TBD
TBD
Internal DCLK period1
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DQZ
CS49531x-DVZ
DCLKP
-
ns
6.7
6.7
6.7
TBD
TBD
TBD
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1/Fxtal
1. After initial power-on reset, Fdclk = Fxtal. After initial kickstart commands, the PLL is locked to max Fdclk and remains
locked until the next power-on reset.
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
13
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode.
Parameter
SCP_CLK frequency1
Symbol
fspisck
tspicss
tspickl
Min
-
Typical
Max
Units
MHz
ns
25
-
SCP_CS# falling to SCP_CLK rising
SCP_CLK low time
24
20
20
5
-
ns
SCP_CLK high time
tspickh
tspidsu
tspidh
-
ns
Setup time SCP_MOSI input
-
ns
Hold time SCP_MOSI input
5
-
ns
SCP_CLK low to SCP_MISO output valid
SCP_CLK falling to SCP_IRQ# rising
SCP_CS# rising to SCP_IRQ# falling
SCP_CLK low to SCP_CS# rising
SCP_CS# rising to SCP_MISO output high-Z
SCP_CLK rising to SCP_BSY# falling
tspidov
tspiirqh
tspiirql
-
11
20
ns
-
ns
0
ns
tspicsh
tspicsdz
tspicbsyl
24
-
-
ns
20
ns
-
3 DCLKP+20
ns
*
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control using
the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed
is Fxtal/3.
tspicss
SCP_CS#
tspickl
tspicsh
1
2
6
7
0
7
0
5
6
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
SCP_BSY#
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspicsdz
tspiirqh
tspiirql
tspibsyl
Figure 3. Serial Control Port - SPI Slave Mode Timing
14
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1
SCP_CS# falling to SCP_CLK rising 3
Symbol Min
Typical
Max
Fxtal/22
-
Units
MHz
ns
fspisck
tspicss
-
-
11*DCLKP +
(SCP_CLK PERIOD)/2
SCP_CLK low time
tspickl
tspickh
tspidsu
tspidh
18
18
11
5
-
-
ns
ns
ns
ns
ns
ns
ns
SCP_CLK high time
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
SCP_CLK low to SCP_CS# falling
SCP_CLK low to SCP_CS# rising
-
-
tspidov
tspicsl
tspicsh
-
11
-
7
-
11*DCLKP +
-
(SCP_CLK PERIOD)/2
Bus free time between active SCP_CS#
tspicsx
tspidz
3*DCLKP
-
ns
ns
SCP_CLK falling to SCP_MOSI output high-Z
-
20
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.8.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a
tested parameter
.
tspicsx
tspicss
EE_CS#
tspickl
tspicsh
tspicsl
1
2
6
7
0
7
0
5
6
SCP_CLK
SCP_MISO
SCP_MOSI
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspidz
Figure 4. Serial Control Port - SPI Master Mode Timing
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
15
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
2
5.12 Switching Characteristics — Serial Control Port - I C Slave Mode
Parameter
Symbol Min
Typical
Max
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
fiicck
tiicckl
tiicckh
-
400
1.25
1.25
1.25
-
-
µs
SCP_SCK rising to SCP_SDA rising or falling for START or tiicckcmd
STOP condition
µs
START condition to SCP_CLK falling
tiicstscl
tiicstp
tiicbft
1.25
2.5
3
-
-
-
µs
µs
µs
ns
ns
ns
ns
ns
ns
SCP_CLK falling to STOP condition
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
tiicsu
100
20
-
tiich
-
tiicdov
tiicirqh
tiicirql
tiicbsyl
18
SCP_CLK falling to SCP_IRQ# rising
NAK condition to SCP_IRQ# low
-
3 DCLKP + 40
*
3 DCLKP + 20
*
SCP_CLK rising to SCB_BSY# low
-
3 DCLKP + 20
*
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control
using the SCP_BSY# pin should be implemented to prevent overflow of the input data buffer.
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
SCP_IRQ#
SCP_BSY#
tiicstp
tiicstscl
tiicckh
tiicdov
R/W
fiicck
tiicbft
A6
A0
ACK
MSB
ACK
LSB
tiicirqh
tiicirql
tiicsu
tiich
tiiccbsyl
Figure 5. Serial Control Port - I2C Slave Mode Timing
16
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
2
5.13 Switching Characteristics — Serial Control Port - I C Master Mode
Parameter
Symbol
fiicck
Min
-
Max
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
400
tiicckl
1.25
1.25
1.25
-
-
tiicckh
µs
SCP_SCK rising to SCP_SDA rising or falling for START or STOP
condition
tiicckcmd
µs
START condition to SCP_CLK falling
tiicstscl
tiicstp
tiicbft
tiicsu
tiich
1.25
2.5
3
-
-
-
µs
µs
µs
ns
ns
ns
SCP_CLK falling to STOP condition
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
100
20
-
-
tiicdov
18
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
tiicstp
tiicstscl
tiicckh
tiicdov
R/W
fiicck
tiicbft
A6
A0
ACK
MSB
ACK
LSB
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
17
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
®
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode
Parameter
Symbol Min
Typical
Max Unit
Address setup before PCP_CS# and PCP_RD# low or PCP_CS#
and PCP_WR# low
tias
5
-
ns
Address hold time after PCP_CS# and PCP_RD# low or PCP_CS#
and PCP_WR# high
tiah
5
-
ns
Read
Delay between PCP_RD# then PCP_CS# low or PCP_CS# then
PCP_RD# low
ticdr
0
-
ns
Data valid after PCP_CS# and PCP_RD# low
PCP_CS# and PCP_RD# low for read
tidd
tirpw
tidhr
tidis
tird
-
24
8
18
-
ns
ns
ns
ns
ns
Data hold time after PCP_CS# or PCP_RD# high
Data high-Z after PCP_CS# or PCP_RD# high
-
-
18
-
PCP_CS# or PCP_RD# high to PCP_CS# and PCP_RD# low for
next read1
30
PCP_CS# or PCP_RD# high to PCP_CS# and PCP_WR# low for
next write1
tirdtw
30
-
-
ns
ns
PCP_RD# rising to PCP_IRQ# rising
tirdirqhl
12
Write
Delay between PCP_WR# then PCP_CS# low or PCP_CS# then
PCP_WR# low
ticdw
0
-
ns
Data setup before PCP_CS# or PCP_WR# high
PCP_CS# and PCP_WR# low for write
tidsu
tiwpw
tidhw
tiwtrd
8
24
8
-
-
-
-
ns
ns
ns
ns
Data hold after PCP_CS# or PCP_WR# high
PCP_CS# or PCP_WR# high to PCP_CS# and PCP_RD# low for
next read1
30
PCP_CS# or PCP_WR# high to PCP_CS# and PCP_WR# low for
next write1
tiwd
30
-
ns
PCP_WR# rising to PCP_BSY# falling
tiwrbsyl
-
2*DCLKP + 20
-
ns
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent
overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware
speed limitations.
18
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
PCP_A[3:0]
PCP_D[7:0]
PCP_CS#
PCP_WR#
PCP_RD#
PCP_IRQ#
tiah
LSP
tidhr
MSP
tias
tidd
ticdr
tidis
tirpw
tird
tirdtw
tirdirqh
Figure 7. Parallel Control Port - Intel® Mode Read Cycle
PCP_A[3:0]
PCP_D[7:0]
PCP_CS#
PCP_RD#
PCP_WR#
PCP_BSY#
tiah
LSP
MSP
tias
tidhw
ticdw
tidsu
tiwpw
tiwd
tiwtrd
tiwrbsyl
Figure 8. Parallel Control Port - Intel Mode Write Cycle
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
19
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
®
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Parameter
Symbol Min
Max
Unit
ns
Address setup before PCP_CS# and PCP_DS# low
Address hold time after PCP_CS# and PCP_DS# low
tmas
tmah
5
5
-
-
ns
Read
Delay between PCP_DS# then PCP_CS# low or PCP_CS# then
PCP_DS# low
tmcdr
0
-
ns
Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high
PCP_CS# and PCP_DS# low for read
tmdd
tmrpw
tmdhr
tmdis
tmrd
-
24
8
19
-
ns
ns
ns
ns
ns
Data hold time after PCP_CS# or PCP_DS# high after read
Data high-Z after PCP_CS# or PCP_DS# high after read
-
-
18
-
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for
next read1
30
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for
next write1
tmrdtw
30
-
-
ns
ns
PCP_RW# rising to PCP_IRQ# falling
tmrwirqh
12
Write
Delay between PCP_DS# then PCP_CS# low or PCP_CS# then
PCP_DS# low
tmcdw
0
-
ns
Data setup before PCP_CS# or PCP_DS# high
PCP_CS# and PCP_DS# low for write
tmdsu
tmwpw
tmrwsu
tmrwhld
tmdhw
tmwtrd
8
24
24
8
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
PCP_R/W# setup before PCP_CS# AND PCP_DS# low
PCP_R/W# hold time after PCP_CS# or PCP_DS# high
Data hold after PCP_CS# or PCP_DS# high
8
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with
PCP_R/W# high for next read1
30
PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for
next write1
tmwd
30
-
ns
PCP_RW# rising to PCP_BSY# falling
tmrwbsyl
-
2*DCLKP + 20
-
ns
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent
overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware
speed limitations.
20
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
HADDR[3:0]
HDATA[7:0]
HEN
tmas
tmah
LSP
tmdhr
MSP
tmdd
tmrwsu
tmcdr
tmdis
tmrwhld
HR/W
tmrdtw
tmrpw
tmrd
HDS
tmrwirqh
HREQ
Figure 9. Parallel Control Port - Motorola® Mode Read Cycle Timing
HADDR[3:0]
tmas
tmah
LSP
tmdsu
MSP
HDATA[7:0]
HEN
tmdhw
tmrwhld
tmwpw
tmcdw
HR/W
tmrwsu
tmwd
tmwtrd
HDS
tmrwirql
HREQ
Figure 10. Parallel Control Port - Motorola Mode Write Cycle Timing
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
21
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.16 Switching Characteristics — UART
Parameter
UART_CLK period1
Symbol
tuclki
Min
266
40
5
Max
Unit
ns
-
60
-
UART_CLK duty cycle
-
%
Setup time for UART_RXD
tuckrxsu
tuckrxdv
tucktxdv
ttxen
Hold time for UART_RXD
5
-
ns
ns
ns
ns
Delay from CLK transition to TXD transition
-
29
?
?
ttxhz
?
?
1. The minimum clock period is limited to DCLKP/32 or the minimum value, whichever is larger.
UART_CLK
tucktxdv
ttxen
ttxhz
UART_TXD
tuckrxsu
tuckrxdv
UART_RXD
UART_TX_EN
Figure 11. UART Timing
22
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.17 Switching Characteristics — Digital Audio Slave Input Port
Parameter
Symbol
Tdaiclkp
-
Min
40
45
10
5
Max
Unit
ns
DAI_SCLK period
-
55
-
DAI_SCLK duty cycle
Setup time DAI_DATAn
Hold time DAI_DATAn
%
tdaidsu
tdaidh
ns
-
ns
DAI_SCLK
tdaidsu
tdaidh
DAI_DATAn
Figure 12. Digital Audio Input (DAI) Port Timing Diagram
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
23
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.18 Switching Characteristics — DSD Slave Input Port
Parameter
DSD_SCLK Pulse Width Low
Symbol
tsclkl
tsclkh
-
Min
78
Typ
Max
-
-
Unit
ns
-
-
-
-
-
-
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
78
ns
(64x Oversampled)
1.024
20
3.2
-
MHz
ns
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
DSD clock to data transition (Phase Modulation mode)
tsdlrs
tsdh
20
-
ns
tdpm
-20
20
ns
Figure 13. Direct Stream Digital - Serial Audio Input Timing
5.19 Switching Characteristics — Digital Audio Output Port
Parameter
Symbol
Min
40
Max
Unit
DAO_MCLK period1
DAO_MCLK duty cycle1
Tdaomclk
-
ns
%
ns
%
-
40
60
-
DAO_SCLK period for Master or Slave mode2
DAO_SCLK duty cycle for Master or Slave mode2
Master Mode (Output A1 Mode)2,3
Tdaosclk
-
40
40
60
DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an
input
tdaomsck
-
19
ns
DAO_LRCLK delay from DAO_SCLK transition, respectively4
DAO_DATA[3:0] delay from DAO_SCLK transition4
Slave Mode (Output A0 Mode)5
tdaomstlr
tdaomdv
-
-
8
ns
ns
10
DAO_DATA[3..0] delay from DAO_SCLK transition4
tdaosdv
15
ns
1. CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports
share a common MCLK but have independent SCLKs and LRCLKs.
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is
divided to produce DAO_SCLK, DAO_LRCLK.
4. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
point at which the data is valid.
5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
24
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Tdaomclk
DAO_MCLK
DAO_SCLK
DAO_DATAn
tdaomsck
tdaomdv , tdaosdv
tdaomstlr
tdaomstlr
DAO_LRCLK
Figure 14. Digital Audio Port Timing, MCLK Master Mode
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
25
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.20 Switching Characteristics — External Memory Interface - Flash Mode
Parameter
Symbol
Min
Max Unit
Write Cycle
ns
ns
ns
ns
ns
ns
txmwasu
txmcswe
txmcswa
1.2 * DCLKP
Address Setup time to EXT_WE# falling
EXT_CS# falling to EXT_WE# falling1
EXT_CS# falling to EXT_WE# rising1
(Flash_WEN_CYCLE + 1.2) * DCLKP
(Flash_WR_CYCLE + 2.2) * DCLKP
2.2 * DCLKP
EXT_WE# low time
txmwp
txmwdh
0.9 * DCLKP
Data Hold after EXT_WE# or EXT_CS# high
Address Hold from end of write
EXT_WE# falling to data valid
EXT_CS# high time2
txmwah
0.8 * DCLKP
txmwedv
txmcsh
-
0
ns
ns
TBD
Read Cycle
Single Word Read Cycle1
(Flash_RD_CYCLE + 1) * DCLKP
ns
ns
ns
ns
ns
txmrdc
txmcsoe
txmrdh
EXT_CS# falling to EXT_OE# falling1
Data Hold after EXT_OE# or EXT_CS# high
Data Input Setup Time
Flash_OEN_CYCLE * DCLKP + 1
4
7
txmrdsu
Bus Turnaround Cycle Delay, Read to Write Cycle or Static
to Dynamic1, 3
(Flash_TURN_CYCLE + 1) * DCLKP
txmturn
1. The following parameters are set by communication with the application firmware. Please refer to AN288 or
CS4953xx Firmware Users Manual for more information.
0 < Flash_WEN_CYCLE < 15
0 < Flash_WR_CYCLE < 31
1 < Flash_RD_CYCLE < 31
0 < Flash_OEN_CYCLE < 15
4 < Flash_TURN_CYCLE < 15
2. A data write transaction is either a burst of two 16-bit half words or four 8-bit bytes with EXT_CS# toggling between
address phases.
3. A data read transaction is either a burst of two 16-bit half words (as shown) or four 8-bit bytes with EXT_CS#
remaining asserted between address phases.
26
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
EXT_A[19:0]
Valid
txmcsh
txmcswa
EXT_CS1#
EXT_CS2#
txmwah
txmcswe
txmwp
EXT_WE#
txmwasu
txmwdh
EXT_D[15:0]
txmwedv
Figure 15. External Memory Interface - Flash Write Cycle Timing
EXT_A[19:0]
Valid
txmrdc
Valid
txmrdc
txmturn
EXT_CS1#
EXT_CS2#
txmcsoe
EXT_OE#
txmrdh
txmrdsu
EXT_D[15:0]
LSP
MSP
Figure 16. External Memory Interface - Flash Read Cycle Timing
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
27
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.21 Switching Characteristics — SDRAM Interface
Refer to Figure 17 through Figure 20.
(SD_CLKOUT = SD_CLKIN)
Parameter
Symbol
Min
2.3
2.3
-
Typical
Max
Unit
ns
SD_CLKIN high time
SD_CLKIN low time
t
-
-
sdclkh
t
ns
sdclkl
SD_CLKOUT rise/fall time
t
1
ns
sdclkrf
SD_CLKOUT Frequency
150
MHz
%
SD_CLKOUT duty cycle
-
45
-
55
SD_CLKOUT rising edge to signal valid
Signal hold from SD_CLKOUT rising edge
SD_CLKOUT rising edge to SD_DQMn valid
SD_DQMn hold from SD_CLKOUT rising edge
SD_DATA valid setup to SD_CLKIN rising edge
SD_DATA valid hold to SD_CLKIN rising edge
SD_CLKOUT rising edge to ADDRn valid
t
3.8
ns
sdcmdv
t
1.1
3.8
-
-
-
-
-
-
ns
sdcmdh
t
-
ns
sddqv
t
1.38
1.3
1.38
-
ns
sddqh
t
ns
sddsu
t
ns
sddh
t
3.8
ns
sdav
28
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
SD_CLKOUT
SD_CS#
tsdclkrf
tsdcmdv
tsdcmdh
SD_RAS#
SD_CAS#
SD_WE#
tsddqh
tsddqv
SD_DQMn
11
00
SD_An
tsdav
tsddsu
tsddh
CAS=2
LSP1
MSP1
LSP2
MSP2
SD_Dn
LSP0
MSP0
LSP3
MSP3
SD_CLKIN
tsdclkl
tsdclkh
Figure 17. External Memory Interface - SDRAM Burst Read Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS#
SD_RAS#
SD_CAS#
SD_WE#
LSP0
MSP0
LSP1
MSP1
LSP2
MSP2
LSP3
MSP3
SD_Dn
SD_An
tsdav
SD_DQMn
00
11
tsddqv
tsddqh
Figure 18. External Memory Interface - SDRAM Burst Write Cycle
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
SD_CLKOUT
tsdcmdv
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
SD_DATAn
Figure 19. External Memory Interface - SDRAM Auto Refresh Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_ADDRn
SD_DATAn
OPCODE
Figure 20. External Memory Interface - SDRAM Load Mode Register Cycle
30
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
6. Ordering Information
The CS4953xx family part number is described as follows:
CS495NNI-XYZ
where
NN - Product Number Variant
I - ROM ID Number
X - Product Grade
Y - Package Type
Z - Lead (Pb) Free
Table 5. Ordering Information
Grade Temp. Range
Part No.
Package
CS495303-CVZ
CS495303-DVZ
CS495313-CQZ
CS495313-DQZ
CS495313-CVZ
CS495313-DVZ
Commercial
Automotive
Commercial
Automotive
Commercial
Automotive
0 to +70 °C
-40 to +85 °C
0 to +70 °C
128-pin LQFP
144-pin LQFP
128-pin LQFP
-40 to +85 °C
0 to +70 °C
-40 to +85 °C
Note: Please contact the factory for availability of the -D (automotive grade) package.
7. Environmental, Manufacturing, & Handling Information
Table 6. Environmental, Manufacturing, & Handling Information
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS495303-CVZ
CS495303-DVZ
CS495313-CQZ
CS495313-DQZ
CS495313-CVZ
CS495313-DVZ
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
31
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
8. Device Pinout Diagrams
8.1 128-Pin LQFP Pinout Diagram
1
5
SD_A0, EXT_A0
SD_A1, EXT_A1
GPIO38, PCP_WR# / DS#, SCP2_CLK
GPIO11, PCP_A3, AS#, SCP2_MISO / SDA
100
GPIO10, PCP_A2 / A10, SCP2_MOSI
VDDIO5
SD_A2, EXT_A2
GPOI9, SCP1_IRQ#
GND4
GPIO8, PCP_IRQ#, SCP2_IRQ#
SD_A3, EXT_A3
SD_A4, EXT_A4
GPIO7, SCP1_CS#, IOWAIT
GPIO6, PCP_CS#, SCP2_CS#
95 VDD4
EXT_CS2#
VDDIO7
GNDIO7
SD_A5, EXT_A5
GNDIO4
10
15
20
25
30
35
GPIO3, DDAC
GPIO2, UART_TXD
SD_A6, EXT_A6
90 SD_A7, EXT_A7
VDDIO4
VDD7
GPIO1, UART_RXD
GPIO0, UART_CLK
SD_A8, EXT_A8
SD_A9, EXT_A9
GND3
GND7
XTAL_OUT
XTI
85 SD_A11, EXT_A11
SD_A12, EXT_A12
VDD3
XTO
GNDA
128-Pin LQFP
PLL_REF_RES
SD_CLKEN
VDDA (3.3V)
SD_CLKIN
VDD8
80 SD_CLKOUT
SD_DQM1
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8
SD_D8, EXT_D8
SD_D9, EXT_D9
GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0
VDDIO8
75 SD_D10, EXT_D10
SD_D11, EXT_D11
VDDIO3
DAI1_SCLK, DSD-CLK
DAI1_LRCLK, DSD4
SD_D12, EXT_D12
SD_D13, EXT_D13
70 SD_D14, EXT_D14
SD_D15, EXT_D15
SD_D0, EXT_D0
GNDIO8
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO26, DAO2_DATA3 / XMTB/UART_TX_EN
GNDIO2
DBDA
DBCK
EXT_WE#
65 SD_D1, EXT_D1
GPIO20, DAO2_DATA2, EE_CS#
Figure 21. 128-Pin LQFP Pin-Out Drawing
32
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
8.2 144-Pin LQFP Pinout Diagram
109
110
72 SD_A0, EXT_A0
SD_A1, EXT_A1
GPIO9, PCP_A1 / A9
GPIO8, PCP_A0 / A8
GPIO7, PCP_AD7 / D7
GPIO6, PCP_AD6 / D6
VDDIO7
70 SD_A2, EXT_A2
GND4
69
SD_A3, EXT_A3
SD_A4, EXT_A4
VDD4
113
GPIO5, PCP_AD5 / D5
GPIO4, PCP_AD4 / D4
GNDIO7
115
116
66
65
EXT_CS2#
SD_A5, EXT_A5
GNDIO4
GPIO3, PCP_AD3 / D3
GPIO2, PCP_AD2 / D2
VDD7
63
60
57
SD_A6, EXT_A6
SD_A7, EXT_A7
VDDIO4
119
120
GPIO1, PCP_AD1 / D1
GPIO0, PCP_AD0 / D0
GND7
SD_A8, EXT_A8
SD_A9, EXT_A9
GND3
122
XTAL_OUT
XTI
SD_A11, EXT_A11
SD_A12, EXT_A12
125
XTO
GNDA 126
NC
55
54
144-Pin LQFP
VDD3
SD_CLKEN
PLL_REF_RES
SD_CLKIN
VDDA (3.3V) 129
VDD8 130
SD_CLKOUT
SD_DQM1
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8 133
50
47
SD_D8, EXT_D8
SD_D9, EXT_D9
GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0
135
SD_D10, EXT_D10
SD_D11, EXT_D11
VDDIO3
VDDIO8 136
DAI1_SCLK, DSD-CLK
DAI1_LRCLK, DSD4
GNDIO8 139
140
45
44
SD_D12, EXT_D12
SD_D13, EXT_D13
SD_D14, EXT_D14
GPIO42, BDI_REQ# , DAI2_LRCLK, PCP_IRQ# / BSY#
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO27
40 SD_D15, EXT_D15
SD_D0, EXT_D0
EXT_WE#
GPIO26 144
37 SD_D1, EXT_D1
Figure 22. 144-Pin LQFP Pin-Out Drawing
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
33
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9. Package Mechanical Drawings
9.1 128-pin LQFP Package Drawing
D
D1
E1
E
1
e
b
∝
A
A1
L
Figure 23. 128-Pin LQFP Package Drawing
Table 7. 128-Pin LQFP Package Characteristics
MILLIMETERS
INCHES
NOM
DIM
MIN
NOM
MAX
MIN
MAX
A
A1
b
---
---
1.60
0.15
0.27
---
---
.063”
.006”
.011”
0.05
0.17
---
.002”
.007”
---
0.22
.009”
.866”
.787”
.630”
.551”
.020”
3.5
D
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
3.5
D1
E
E1
e
q
0°
7°
0°
7°
L
0.45
0.60
0.75
.018”
.024”
.030”
L1
1.00 REF
.039” REF
TOLERANCES OF FORM AND POSITION
ddd
0.08
.003”
34
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9.2 144-Pin LQFP Package
E
E1
D D1
Notes:
SEATING PLANE
B
e
b
ddd
B
1. Controlling dimension is millimeter.
2. Dimensioning and tolerancing per ASME Y14.5M-
1994.
L1
θ
A
A1
L
Figure 24. 144-Pin LQFP Package Drawing
Table 8. 144-Pin LQFP Package Characteristics
MILLIMETERS
INCHES
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
A1
b
---
---
1.60
0.15
0.27
---
---
---
.063”
.006”
.011”
0.05
0.17
---
.002”
.007”
0.22
.009”
.866”
.787”
.866”
.787”
.020”
---
D
22.00 BSC
20.00 BSC
22.00 BSC
20.00 BSC
0.50 BSC
---
D1
E
E1
e
q
0°
7°
0°
7°
L
0.45
0.60
0.75
.018”
.024”
.039” REF
.030”
L1
1.00 REF
TOLERANCES OF FORM AND POSITION
ddd
0.08
.003”
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
35
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
10. Revision History
Revision
Date
FEB 2006
Changes
A1
A2
Advance release.
JUN 2006
Updated part numbers for ordering (Tables 5 & 6), Updated V and V specification to
OH
OL
include the current load used for testing
A3
JUL 2006
Updated part numbers for ordering (Tables 5 &6). Updated text in sections 3 and 4.
Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh, and
Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS#. Added footnote to
XTI table. Removed SCLK/LRCLK relative timing from DAI port timing. Removed
SCLK/LRCLK slave relative timing from DAO port timing.
A4
OCT 2007
Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI. This
applies to both SPI ports.
PP1
PP2
May 28, 2008
June 20, 2008
Updated product feature list in Table 2. Updated Figure 21 and Figure 22.
Added typical crystal frequency values in Table Footnote 1 and Max and Min values of
F
in Section 5.8. Removed DSD Phase Modulation Mode from Section 5.18.
xtal
Removed reference to MCLK in Section 5.18. Redefined Master mode clock
speed for SCP_CLK in Section 5.11.. Redefined DC leakage characterization
data in Section 5.3, correcting units of measurement. Modified Footnote 1 under
Section 5.10.
36
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its sub-
sidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and
is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowl-
edgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, includ-
ing use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property
of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the informa-
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER-
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PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS
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Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
Dolby, Dolby Digital, Dolby Headphone, Dolby Virtual Speaker, Dolby Headphone, Pro Logic, AC-3, and Surround EX are registered trademarks of Dolby Laboratories,
Inc. AAC is a trademark of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a right under any patent,
or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use final product. It is hereby
notified that a license for such use is required from Dolby Laboratories.
DTS and DTS Digital Surround are registered trademarks of the Digital Theater Systems, Inc. DTS Neo:6, DTS-ES 96/24, DTS-ES, DTS 6.1, and DTS 96/24 are
trademarks of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to distribute software of DTS in any finished end-user
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THX Technology by Lucasarts Entertainment Company Corporation. THX is a registered trademark of Lucasarts Entertainment Company Corporation. Re-equaliza-
tion and Ultra 2 are trademarks of Lucasfilm Ltd.
SRS, Circle Surround and Trusurround XT are registered trademarks of SRS Labs, Inc. Circle Surround II is a trademark of SRS Labs, Inc. The CIRCLE SURROUND
TECHNOLOGY rights incorporated in the Cirrus Logic chip are owned by SRS Labs, Inc. and by Valence Technology Ltd., and licensed to Cirrus Logic, Inc.
Users of any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY (i.e., CIRCLE SURROUND® LICENSEES) must first sign a license to pur-
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of performance verification tests performed by SRS Labs, Inc., or Valence Technology Ltd. E-mail requests for performance specifications and testing rate schedule
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All equipment manufactured using any Cirrus Logic chip containing enabled CIRCLE SURROUND® TECHNOLOGY must carry the Circle Surround® logo on the front
panel in a manner approved in writing by SRS Labs, Inc., or Valence Technology Ltd. If the Circle Surround logo is printed in users manuals, service manuals or
advertisements, it must appear in a form approved in writing by SRS Labs, Inc., or Valence Technology, Ltd. The rear panel of Circle Surround® products, users
manuals, service manuals, and all advertising must all carry the legends as described in LICENSOR'S most current version of the CIRCLE SURROUND Trademark
Usage Manual.
Microsoft and Windows Media are registered trademarks of Microsoft Corporation. The product includes technology owned by Microsoft Corporation and cannot be
used or distributed without a license from Microsoft Licensing, Inc.
, HDCD, High Definition Compatible Digital and Pacific Microsonics Inc. are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries. HDCD technology provided under license from Microsoft Corporation. The product's design (and/or software) is covered by one or more
of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending.
Supply of this product does not convey a license under the relevant intellectual property of Thomson multimedia and/or Fraunhofer Gesellschaft nor imply any right to
use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit
http://www.mp3licensing.com.
Motorola and SPI are trademarks of Motorola, Inc.
Intel is a registered trademark of Intel Corporation.
2
I C is a registered trademark of Philips Semiconductor.
ARM is a registered trademark of ARM Limited.
Logic7 is a registered trademark of Harmon International Industries, Inc.
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
37
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
38
®Copyright 2008 Cirrus Logic, Inc.
DS705PP2
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