CS495314-CVZ2 [CIRRUS]
Micro Peripheral IC,;
| 型号： | CS495314-CVZ2 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Micro Peripheral IC, |
| 文件： | 总35页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4953xx Data Sheet
FEATURES
Audio Decoder DSP Family with
Dual 32-bit DSP Engine Technology
Multi-standard 32-bit Audio Decoding plus Post
processing
16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx
Two SPI™/I2C™ Ports
Supports legacy audio formats and a wide array of post-
processing
— Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1,
Dolby Headphone 2®, Dolby Virtual Speaker 2®,
Dolby Volume® (original), Dolby Volume 258 (lite),
Audistry®
Customer Software Security Keys
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial Flash Memory Support
— DTS-ES 96/24™ Discrete 7.1, DTS-ES™ Discrete 7.1,
DTS-ES™ Matrix 6.1, DTS Neo:6®, DTS Neural
Surround™ DTS Surround Sensation Speaker
— MPEG-2 AAC™ LC 5.1
— SRS® Circle Surround II®, SRS Circle Surround Auto,
SRS Circle Surround Decoder Optimized, SRS
The CS4953xx DSP family are the enhanced versions of the
CS495xx DSP family with higher overall performance and
lower system cost. The CS4953xx includes all mainstream
audio processing codes in on-chip ROM. This saves external
memory for code storage. In addition, the intensive decoding
tasks of Dolby Digital Surround EX®, AAC multi-channel,
DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone
can be accomplished without the expense of external
SDRAM memory.
TruVolume™ 7.1 (V 2.1.0.0), SRS TruSurround
HD/HD4®, SRS WOW HD™, SRS CS Headphone™,
SRS Circle Cinema 3D™, SRS Studio Sound HD™
— THX® Ultra2™, THX Select2™
Cirrus Logic’s Applications Library
With larger internal memories than the CS495xx, the
CS49531x is designed to support up to 150 ms per channel
of lip-sync delay. With 150 MHz internal clock speed, the
CS4953xx supports the most demanding post-processing
requirements. It is also designed for easy upgrading.
Customers currently using the CS495xx can upgrade to the
CS4953xx with minor hardware and software changes.
— Cirrus Original Multi-Channel Surround 2 (COMS2),
Cirrus Band XpandeR™, Cirrus Virtualization
Technology (CVT), Cirrus Intelligent Room Calibration
2 (IRC2), Cirrus Bass Enhancement (CBE)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processors including: 7.1 Bass
Manager Quadruple Crossover, Tone Control, 11-
Band Parametric EQ, Delay, 2:1/4:1 Decimator,
1:2/1:4 Upsampler
Ordering Information
See page 27 for ordering information.
Up to 12 Channels of 32-bit Serial Audio Input
Serial
Control1
Serial
Control2
Parallel
Control
GPIO
Debug
12 Ch PCM
Audio In
STC
D
M
A
Coyote 32-bit
Coyote 32-bit
DSP B
TMR1
TMR2
DSP A
S/PDIF S/PDIF
P
X
Y
P
X
Y
16 Ch PCM
Audio Out
PLL
Ext. Memory Controller
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright © 2011 Cirrus Logic, Inc.
All Rights Reserved
April 2011
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http://www.cirrus.com
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Table of Contents
1 Documentation Strategy ............................................................................................................4
2 Overview .....................................................................................................................................4
2.1 Migrating from CS495xx(2) to CS4970x4 .................................................................................................5
2.2 Licensing ..................................................................................................................................................5
3 Code Overlays ............................................................................................................................6
4 Hardware Functional Description ............................................................................................6
4.1 Coyote DSP Core .....................................................................................................................................6
4.1.1 DSP Memory ...............................................................................................................................6
4.1.2 DMA Controller ............................................................................................................................7
4.2 On-chip DSP Peripherals .........................................................................................................................7
4.2.1 Digital Audio Input Port (DAI) .......................................................................................................7
4.2.2 Digital Audio Output Port (DAO) ..................................................................................................7
2
4.2.3 Serial Control Port 1 & 2 (I C™ or SPI™) ...................................................................................7
4.2.4 Parallel Control Port ....................................................................................................................7
4.2.5 External Memory Interface ..........................................................................................................7
4.2.6 General Purpose Input/Output (GPIO) ........................................................................................7
4.2.7 Phase-locked Loop (PLL)-based Clock Generator ......................................................................8
4.3 DSP I/O Description .................................................................................................................................8
4.3.1 Multiplexed Pins ..........................................................................................................................8
4.3.2 Termination Requirements ...........................................................................................................8
4.3.3 Pads ............................................................................................................................................8
4.4 Application Code Security ........................................................................................................................8
5 Characteristics and Specifications ..........................................................................................8
5.1 Absolute Maximum Ratings ......................................................................................................................8
5.2 Recommended Operating Conditions ......................................................................................................9
5.3 Digital DC Characteristics ........................................................................................................................9
5.4 Power Supply Characteristics ..................................................................................................................9
5.5 Thermal Data (144-Pin LQFP) ...............................................................................................................10
5.6 Thermal Data (128-pin LQFP) ................................................................................................................10
5.7 Switching Characteristics—RESET ......................................................................................................... 11
5.8 Switching Characteristics — XTI ............................................................................................................ 11
5.9 Switching Characteristics — Internal Clock ............................................................................................12
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode .....................................................12
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode ...................................................13
2
5.12 Switching Characteristics — Serial Control Port - I C Slave Mode ......................................................14
2
5.13 Switching Characteristics — Serial Control Port - I C Master Mode ....................................................15
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode .................................................16
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode .........................................18
5.16 Switching Characteristics — Digital Audio Slave Input Port .................................................................20
5.17 Switching Characteristics — Digital Audio Output Port ........................................................................21
5.18 Switching Characteristics — SDRAM Interface ....................................................................................22
6 Ordering Information ...............................................................................................................25
7 Environmental, Manufacturing, and Handling Information .................................................26
8 Device Pin-Out Diagram ..........................................................................................................27
8.1 128-Pin LQFP Pin-Out Diagram .............................................................................................................27
8.2 144-Pin LQFP Pin-Out Diagram ............................................................................................................28
9 Package Mechanical Drawings ...............................................................................................29
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9.1 128-Pin LQFP Package Drawing ...........................................................................................................29
9.2 144-Pin LQFP Package Drawing ...........................................................................................................30
10 Revision History .....................................................................................................................31
List of Figures
Figure 1. RESET Timing ........................................................................................................................................12
Figure 2. XTI Timing ..............................................................................................................................................12
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................14
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................15
Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................16
Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................17
Figure 7. Parallel Control Port - Intel® Slave Mode Read Cycle ...........................................................................19
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................19
Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing ........................................................21
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing .........................................................21
Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................22
Figure 12. DAI Slave Timing Diagram ...................................................................................................................22
Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................23
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK) ...........................................24
Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................25
Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................25
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................26
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................26
Figure 19. 128-pin LQFP Pin-Out Drawing (CS495303/CS495313) ......................................................................29
Figure 20. 128-pin LQFP Pin-Out Drawing (CS495304/CS495314) ......................................................................30
Figure 21. 144-pin LQFP Pin-Out Drawing (CS495313) ........................................................................................31
Figure 22. 128-pin LQFP Package Drawing .........................................................................................................32
Figure 23. 144-pin LQFP Package Drawing .........................................................................................................33
List of Tables
Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. CS49530x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. CS49531x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Environmental, Manufacturing, and Handling Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. 128-pin LQFP Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. 144-pin LQFP Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
1 Documentation Strategy
The CS4953xx data sheet describes the CS4953xx family of multichannel audio decoders. This document
should be used in conjunction with the following documents when evaluating or designing a system around the
CS4953xx family of processors.
Table 1. CS4953xx Related Documentation
Document Name
Description
This document, which contains the hardware
specifications for the CS4953xx family
CS4953xx Data Sheet
Includes detailed system design information for
CS4953x3 product family, including Typical
Connection Diagrams, Boot-Procedures, Pin
Descriptions, etc.
CS4953xx Hardware User’s Manual
A new consolidated documentation set for the
CS4953x4 product family that includes:
• Detailed system design information including typical
connection diagrams, boot procedures, pin
descriptions, etc. Also describes use of DSP
condenser tool
CS495314/CS4970x4 System Designer’s Guide
• Detailed firmware design information including
signal processing flow diagrams and control API
information
Includes detailed firmware design information
including signal processing flow diagrams and control
API information
AN288 - CS4953xx/CS4970x4 Firmware User’s Manual
The scope of the CS4953xx data sheet is primarily the hardware specifications of the CS4953xx family of
devices. This includes hardware functionality, characteristic data, pinout, and packaging information.
The intended audience for the CS4953xx data sheet is the system PCB designer, MCU programmer, and the
quality control engineer.
2 Overview
The CS4953xx DSP Family, together with Cirrus Logic’s comprehensive library of audio processing algorithms
enables the development of next-generation audio solutions. There are two classes of devices in the
CS4953xx DSP family:
• CS4953x3 Class (ROM ID 3), comprising the CS495303 and the CS495313
• CS4953x4 Class (ROM ID 4), comprising the CS495304 and the CS495314
The primary difference between the CS4953x3 and the CS4953x4 classes is the support of the DSP
Condenser application on the CS4953x4 class of products only. The DSP Condenser is a tool set that enables
the DSP to automatically boot and configure itself from an external serial FLASH, thus reducing the traditional
heavy loading on the part of the system microcontroller. Because of the design time savings, enhanced tools
support, and better performance associated with the CS4953x4 product set, Cirrus Logic recommends that the
CS4953x4 family be used for all new designs. More information on the DSP Condenser can be found in the
CS4953x4/CS497xx System Designer’s Guide.
Within each ROM ID class (3, 4), the breakdown into two devices per class (CS49530x and CS49531x) is
based on the differences between the internal memory size and DSP firmware supported. Essentially, the
audio processing features of the CS49531x are a superset of audio features available in the CS49530x.
Table 2, “Device and Firmware Selection Guide,” on page 6 provides details of the differences between the two
product classes.
Note: The CS495303/04/14 is available in a 128-pin LQFP package and the CS495313 is available in a 128-pin
or 144-pin LQFP package.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
2.1 Migrating from CS4953x3 to CS4953x4
• The recommended way to boot the DSP for normal operation is “master boot”. Refer to Chapter 1 of the
CS4953x4/CS4970x4 System Designer’s Guide. CS4953x4 supports slave boot mode as well (used for
programming the serial flash with the DSP code, through the SCP2 port).
• CS4953x4 DSPs are only available in 128 pin package.
• The serial flash chip select pin used is pin 14 (GPIO0) for master boot. Cirrus Logic recommends that at
least an 8-Mb serial flash device be used. Refer to CS4953x4/CS4970x4 System Designer’s Guide for a
list of flash types that are currently supported.
• CS4953x4 DSP family supports DSP Condenser and DSP Manager API for runtime control/host
communication. Refer to CS4953x4/CS4970x4 System Designer’s Guide for details.
2.2 Licensing
Licenses are required for all third party audio decoding/processing algorithms, including the application notes.
contact your local Cirrus Sales representative for more information.
3 Code Overlays
The suite of software available for the CS4953xx family consists of an operating system (OS) and a library of
overlays. The overlays have been divided into three main groups called Decoders, Matrix-processors, and
Post-processors. All software components are defined below:
• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external memory,
processing host messages, calling audio-processing subroutines, error concealment, etc.
™
• Decoders - Any Module that initially writes data into the audio I/O buffers, e.g. AC-3 , DTS, PCM, etc. All
the decoding/processing algorithms listed below require delivery of PCM or IEC61937-packed,
2
compressed data via I S- or LJ-formatted digital audio to the CS4953xx.
• Matrix-processors - Any module that processes audio I/O buffer PCM data in-place before the Post-
processors. Generally speaking, these modules alter the number of valid channels in the audio I/O buffer
through processes like Virtualization (n2 channels) or Matrix Decoding (2n channels). Examples are
Dolby ProLogic II, IIx, IIz and DTS Neo:6.
• Post-processors - Any module that processes audio I/O buffer PCM data in-place after the Matrix-
Processors. Examples are Bass Management, Audio Manager, Tone Control, EQ, Delay, Customer-
specific Effects, Dolby Headphone® 2 and Dolby Virtual Speaker® 2, etc.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is
requested. Each overlay can be reloaded independently without disturbing the other overlays. For example,
when a new decoder is selected, the OS, matrix-, and post-processors do not need to be reloaded — only the
new decoder (the same is true for the other overlays).
Table 2 below lists the firmware available based on device selection. Refer to AN288, CS4953xx/CS497xxx
™
Firmware User’s Manual for the latest listing of application codes and Cirrus Framework modules available.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
1
Table 2. Device and Firmware Selection Guide
Virtualizer-
processor
(DSP-B)2
Decode Processor
(DSP-A)2
Matrix-processor
(DSP-A)2
Post-processor
(DSP-B)2
Pre-
Process
Device
Dolby Pro Logic II/IIx/IIz
7.1
Stereo PCM
Circle Surround® II
(Stereo In)
Dolby Headphone
Dolby Virtual Speaker
SRS TruSurround XT
THX Select
Multi-Channel PCM
(2:1 Down-sampling
Option)
CS49530x
300 M ACS
APP
(Advanced Post-
processing)
–Tone Control
–Select 2
N/A
Cirrus Original Multi-
Channel Surround
(Effects / Reverb
Processor)
Dolby Digital
AAC
MP3
HDCD
–PEQ (up to 11 Bands)
–Delay
–7.1 Bass Manager
–Audio Manager
Down-mix
(Simultaneous Process)
CS49531x
(Superset of
CS49530x)
1:2 Up-sampling
Same as CS49530x +
DTS
Same as CS49530x +
DTS Neo:6, DTS Neural Same as CS49530x +
Lip Sync
Delay
DTS-ES
DTS 96/24
Sound
(Stereo In)
THX Ultra2
300 M ACS
1.This feature list is a snapshot of features available as of the publication date of this revision of the data sheet. More features may
now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS49530x
and CS49531x products.
2. Additional processing (MPMA, MPMB, VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic
FAE for concurrency matrix.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
4 Hardware Functional Description
4.1 Coyote 32-bit DSP Core
The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a
high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply
accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data
registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core
memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP
core, leaving more MIPS available for signal processing instructions.
CS4953xx functionality is controlled by application codes that are stored in on-board ROM or downloaded to
the CS4953xx from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio
decoder and post-processor modules which are available from Cirrus Logic.
The CS4953xx is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player,
and digital broadcast decoder applications.
4.1.1 DSP Memory
Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory
for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES
96/24, and THX Ultra2.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
Table 3. CS49530x DSP Memory Sizes
Memory
DSP A
DSP B
Type
X
Y
P
16K SRAM, 16K ROM
16K SRAM, 32K ROM
8K SRAM, 32K ROM
10K SRAM, 8K ROM
16K SRAM, 16K ROM
8K SRAM, 24K ROM
Table 4. CS49531x DSP Memory Sizes
Memory
Type
DSP A
DSP B
X
Y
P
16K SRAM, 16K ROM
24K SRAM, 32K ROM
8K SRAM, 32K ROM
10K SRAM, 8K ROM
16K SRAM, 16K ROM
8K SRAM, 24K ROM
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between eight on-chip resources. Each resource has
its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and
the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and
increment controls. The service interval for each DMA channel as well as up to six interrupt events, is
programmable.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
The 12-channel (6-line) DAI port supports a wide variety of data input formats. The port is capable of accepting
PCM or IEC61937. Up to 32-bit word lengths are supported.
The port has two independent slave-only clock domains. Each data input can be independently assigned to a
clock domain. The sample rate of the input clock domains can be determined automatically by the DSP, which
off-loads the task of monitoring the S/PDIF receiver from the host. A time-stamping feature allows the input
data to be sample-rate converted via software.
4.2.2 Digital Audio Output Port (DAO)
Note:
There are two DAO ports. Each port can output eight channels of up to 32-bit PCM data. The port supports
data rates from 32 kHz to 192 kHz. Each port can be configured as an independent clock domain in slave
mode, or the ratio of the two clocks can be set to even multiples of each other in master mode. The two
ports can also be ganged together into a single clock domain. Each port has one serial audio pin that can
be configured as a 192 kHz S/PDIF transmitter (data with embedded clock on a single line).
Note: Only one S/PDIF transmitter pin is available in the 128-pin package.
2
™
™
4.2.3 Serial Control Port 1 & 2 (I C or SPI )
There are two on-chip serial control ports that are capable of operating as master or slave in either I2C or SPI
modes. SCP1 defaults to slave operation. It is dedicated for external host-control and supports an external
clock up to 50 MHz in SPI mode. It is present in both the 144- and 128-pin packages. This high clock speed
enables very fast code download, control or data delivery. SCP2 defaults to master mode and is dedicated for
booting from external serial Flash memory or for audio sub-system control. SCP2 does not include the
SCP2_BSY# pin in the 128-pin package.
4.2.4 Parallel Control Port
®
®
The CS4953xx parallel port supports both Motorola and Intel interfaces. It can be used for both control and
data delivery. The parallel port pins are multiplexed with serial control port 2 and are available in the 144-pin
package.
4.2.5 External Memory Interface
The external memory interface controller supports up to 128 Mb of SDRAM, using a 16-bit data bus.
4.2.6 General Purpose Input/Output (GPIO)
Many of the CS4953xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output,
an input, or an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge,
active-low, or active-high.
4.2.7 Phase-Locked Loop (PLL)-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4953xx defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
through master boot from an external serial FLASH or through host control. A built-in crystal oscillator circuit
with a buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or
2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4953xx pins are multi-functional. For details on pin functionality, refer to the CS4953xx
Hardware User’s Manual.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
4.3.2 Termination Requirements
Open-drain pins on the CS4953xx must be pulled high for proper operation. Refer to the CS4953xx Hardware
User’s Manual to identify which pins are open-drain and what value of pull-up resistor is required for proper
operation.
Mode select pins on the CS4953xx are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4953xx Hardware User’s Manual.
4.3.3 Pads
The CS4953xx I/O operates from the 3.3 V supply and is 5 V tolerant.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
5 Characteristics and Specifications
Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and
temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,
C = 20 pF, VDD = VDDA = 1.8 V, VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
L
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
–0.3
–0.3
–0.3
-
2.0
3.6
3.6
0.3
V
V
V
V
|VDDA – VDDIO|
Input pin current, any pin except supplies
Input voltage on PLL_REF_RES
Input voltage on I/O pins
I
—
+/- 10
3.6
mA
V
in
V
-0.3
-0.3
–65
filt
V
5.0
V
inio
Storage temperature
T
150
°C
stg
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
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CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.2 Recommended Operating Conditions
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
VDD
VDDA
VDDIO
1.71
3.13
3.13
1.8
3.3
3.3
0
1.89
3.46
3.46
V
V
V
V
|VDDA – VDDIO|
Ambient operating temperature
T
A
Commercial Grade (CQZ/CVZ)
Automotive Grade (DQZ/DVZ)
0
- 40
+25
+25
+ 70
+ 85
°C
ºC
Commercial
Automotive
T
0
-40
—
+125
+125
j
Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.
5.3 Digital DC Characteristics
(Measurements performed under static conditions.)
Parameter
High-level input voltage
Symbol
Min
Typ
—
Max
—
Unit
V
V
2.0
IH
Low-level input voltage, except XTI
Low-level input voltage, XTI
Input Hysteresis
V
—
—
0.8
0.6
—
V
IL
V
—
—
—
V
ILXTI
V
0.4
—
V
hys
OH
High-level output voltage (IO = -4mA), except XTI,
SDRAM pins
V
VDDIO * 0.9
—
V
Low-level output voltage (IO = 4mA), except XTI, SDRAM
pins
V
—
—
VDDIO * 0.1
V
OL
SDRAM High-level output voltage (IO = -8mA)
SDRAM Low-level output voltage (IO = 8mA)
V
VDDIO * 0.9
—
—
—
—
V
V
OH
V
I
—
—
VDDIO * 0.1
5
OL
Input leakage current (all digital pins with internal pull-up
resistors disabled)
μA
IN
Input leakage current (all digital pins with internal pull-up
resistors enabled, and XTI)
I
—
—
70
μA
IN-PU
5.4 Power Supply Characteristics
(measurements performed under operating conditions)
Parameter
Min
Typ
Max
Unit
Power supply current:
Core and I/O operating: VDD1
PLL operating: VDDA
With external memory and most ports operating: VDDIO
—
—
—
350
3.5
120
—
—
—
mA
mA
mA
1. Dependent on application firmware and DSP clock speed.
DS705PP8
10
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.5 Thermal Data (144-pin LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
θja
°C / Watt
1
2
Two-layer Board
Four-layer Board
—
—
48
40
—
—
Thermal Resistance (Junction to Top of Package)
Two-layer Board
ψjt
°C / Watt
1
2
—
—
.39
.33
—
—
Four-layer Board
5.6 Thermal Data (128-pin LQFP)
Parameter
Symbol
Min
Typ
Max
Unit
Thermal Resistance (Junction to Ambient)
θja
°C / Watt
1
2
Two-layer Board
Four-layer Board
—
—
53
44
—
—
Thermal Resistance (Junction to Top of Package)
Two-layer Board
Four-layer Board
ψjt
°C / Watt
1
2
—
—
.45
.39
—
—
Notes: 1. Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz copper covering 20 %
of the top & bottom layers.
2. Four-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-ounce copper covering
20 % of the top & bottom layers and 0.5-ounce copper covering 90 % of the internal power plane and ground plane
layers.
3. To calculate the die temperature for a given power dissipation
Τj = Ambient Temperature + [ (Power Dissipation in Watts) * θja ]
4. To calculate the case temperature for a given power dissipation
Τc = Τj - [ (Power Dissipation in Watts) * ψjt ]
DS705PP8
11
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.7 Switching Characteristics—RESET
Parameter
RESET minimum pulse width low
Symbol
Min
1
Max
—
Unit
μs
T
rstl
T
/m
50
20
100
—
ns
All bidirectional pins high-Z after RESET low
Configuration pins setup before RESET high
Configuration pins hold after RESET high
rst2z
T
ns
rstsu
T
—
ns
rsthld
RESET#
HS[3:0]
All Bidirectional
Pins
Trstsu
Trsthld
Trst2z
Trstl
Figure 1. RESET Timing
5.8 Switching Characteristics — XTI
Parameter
External Crystal operating frequency1
XTI period
Symbol
Min
Max
24.576
81.4
/m
Unit
MHz
ns
F
12.288
41
xtal
T
clki
XTI high time
T
16.4
16.4
10
ns
clkih
XTI low time
T
—
ns
clkil
External Crystal Load Capacitance (parallel resonant)2
C
18
pF
L
External Crystal Equivalent Series Resistance
ESR
—
50
Ω
1. Part characterized with the following crystal frequency values: 12.288 and 24.576
2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside
this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s
recommendation for load capacitor selection.
XTI
tclkih
t clkil
Tclki
Figure 2. XTI Timing
DS705PP8
12
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.9 Switching Characteristics — Internal Clock
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
F
—
—
MHz
dclk
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DVZ
—
F
F
F
F
F
150
150
150
TBD
TBD
—
xtal
xtal
xtal
xtal
xtal
Internal DCLK period1
DCLKP
—
—
—
ns
—
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DVZ
6.7
6.7
6.7
TBD
TBD
1/F
1/F
1/F
1/F
1/F
xtal
xtal
xtal
xtal
xtal
1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains
locked until the next power-on reset.
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode
Parameter
SCP_CLK frequency1
Symbol
Min
—
24
20
20
5
Typical
—
Max
25
—
—
—
—
—
11
20
—
—
—
—
Units
MHz
ns
f
t
spisck
spicss
SCP_CS falling to SCP_CLK rising
SCP_CLK low time
—
t
—
ns
spickl
spickh
spidsu
SCP_CLK high time
t
—
ns
Setup time SCP_MOSI input
Hold time SCP_MOSI input
SCP_CLK low to SCP_MISO output valid
t
—
ns
t
5
—
ns
spidh
t
—
—
0
—
ns
spidov
spiirqh
t
t
—
ns
SCP_CLK falling to SCP_IRQ rising
SCP_CS rising to SCP_IRQ falling
SCP_CLK low to SCP_CS rising
t
—
ns
spiirql
24
—
—
—
ns
spicsh
t
20
ns
SCP_CS rising to SCP_MISO output high-Z
SCP_CLK rising to SCP_BSY falling
spicsdz
t
3 DCLKP+20
*
ns
spicbsyl
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control using
the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed
is Fxtal/3.
DS705PP8
13
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
tspicss
SCP_CS
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ
SCP_BSY
tspickl
tspicsh
1
2
6
7
0
7
0
5
6
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
tspidsu
tspidh
tspidov
tspicsdz
LSB
tspiirqh
tspiirql
tspibsyl
Figure 3. Serial Control Port - SPI Slave Mode Timing
DS705PP8
14
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency1,2
Symbol Min
Typical
Max
Units
f
t
—
—
—
F
/2 MHz
ns
spisck
spicss
xtal
SCP_CS falling to SCP_CLK rising 3
11*DCLKP +
—
(SCP_CLK PERIOD)/2
SCP_CLK low time
t
18
18
11
5
—
—
—
—
—
—
—
—
—
—
11
—
—
ns
ns
ns
ns
ns
ns
ns
spickl
spickh
spidsu
SCP_CLK high time
t
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
t
t
spidh
t
—
7
spidov
t
SCP_CLK low to SCP_CS falling
SCP_CLK low to SCP_CS rising
spicsl
t
—
11*DCLKP +
spicsh
(SCP_CLK PERIOD)/2
t
—
—
3*DCLKP
—
—
ns
ns
Bus free time between active SCP_CS
spicsx
SCP_CLK falling to SCP_MOSI output high-Z
t
20
spidz
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application.
2. See Section 5.8.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a
tested parameter
tspicsx
tspicss
EE_CS
tspickl
tspicsh
tspicsl
0
1
2
6
7
0
5
6
7
SCP_CLK
SCP_MISO
SCP_MOSI
fspisck
tspickh
A6
A5
A0
R/W
MSB
MSB
LSB
LSB
tspidsu
tspidh
tspidov
tspidz
Figure 4. Serial Control Port - SPI Master Mode Timing
DS705PP8
15
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
2
5.12 Switching Characteristics — Serial Control Port - I C Slave Mode
Parameter
Symbol Min
Typical
—
Max
400
—
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
f
—
iicck
t
1.25
1.25
1.25
—
iicckl
t
—
—
µs
iicckh
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
t
—
—
µs
iicckcmd
START condition to SCP_CLK falling
t
1.25
2.5
3
—
—
—
—
—
—
—
—
—
—
—
—
18
µs
µs
µs
ns
ns
ns
ns
ns
ns
iicstscl
SCP_CLK falling to STOP condition
t
iicstp
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
t
iicbft
t
100
20
—
iicsu
t
iich
t
t
iicdov
—
3 DCLKP + 40
*
SCP_CLK falling to SCP_IRQ rising
NAK condition to SCP_IRQ low
SCP_CLK rising to SCB_BSY low
iicirqh
t
—
3 DCLKP + 20
*
3 DCLKP + 20
—
iicirql
t
—
—
iicbsyl
*
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control
using the SCP_BSY pin should be implemented to prevent overflow of the input data buffer.
tiicckcmd
tiicckl
tiicr
tiicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
SCP_IRQ
SCP_BSY
tiicstp
tiicstscl
tiicckh
tiicdov
R/W
f
tiicbft
iicck
A6
A0
ACK MSB
ACK
LSB
tiicirqh
tiicirql
tiicsu
tiich
t
iiccbsyl
Figure 5. Serial Control Port - I2C Slave Mode Timing
DS705PP8
16
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
2
5.13 Switching Characteristics — Serial Control Port - I C Master Mode
Parameter
Symbol
Min
—
Max
400
—
Units
kHz
µs
SCP_CLK frequency1
SCP_CLK low time
SCP_CLK high time
f
iicck
t
1.25
1.25
1.25
iicckl
t
—
µs
iicckh
SCP_SCK rising to SCP_SDA rising or falling for START or STOP
condition
t
—
µs
iicckcmd
START condition to SCP_CLK falling
t
1.25
2.5
3
—
—
—
—
—
36
µs
µs
µs
ns
ns
ns
iicstscl
SCP_CLK falling to STOP condition
t
iicstp
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
t
iicbft
t
100
20
iicsu
t
iich
t
—
iicdov
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application.
tiicckcmd
tiicckl
tiicr
t
iicf
tiicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
SCP_SDA
t
iicstp
tiicstscl
t
tiicdov
R/W
f
tiicbft
iicckh
iicck
A6
A0
ACK MSB
ACK
LSB
tiicsu
tiich
Figure 6. Serial Control Port - I2C Master Mode Timing
DS705PP8
17
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
®
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode
Parameter
Symbol Min
Typical
Max Unit
t
5
—
—
ns
Address setup before PCP_CS and PCP_RD low or PCP_CS and
PCP_WR low
ias
t
5
—
—
ns
Address hold time after PCP_CS and PCP_RD low or PCP_CS and
PCP_WR high
iah
Read
t
0
—
—
ns
Delay between PCP_RD then PCP_CS low or PCP_CS then
PCP_RD low
icdr
t
—
24
8
—
—
—
—
—
18
—
—
18
—
ns
ns
ns
ns
ns
Data valid after PCP_CS and PCP_RD low
PCP_CS and PCP_RD low for read
idd
t
irpw
t
Data hold time after PCP_CS or PCP_RD high
Data high-Z after PCP_CS or PCP_RD high
idhr
t
—
30
idis
t
PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next
read1
ird
t
30
—
—
—
—
ns
ns
PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next
write1
irdtw
t
12
PCP_RD rising to PCP_IRQ rising
irdirqhl
Write
t
0
—
—
ns
Delay between PCP_WR then PCP_CS low or PCP_CS then
PCP_WR low
icdw
t
8
24
8
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Data setup before PCP_CS or PCP_WR high
PCP_CS and PCP_WR low for write
idsu
t
iwpw
t
Data hold after PCP_CS or PCP_WR high
idhw
t
30
PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next
read1
iwtrd
t
30
—
—
ns
PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next
write1
iwd
t
—
2*DCLKP + 20
—
ns
PCP_WR rising to PCP_BSY falling
iwrbsyl
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent
overflowing the input data buffer. AN288 CS4953xx /CS497xxx Firmware User’s Manual should be consulted for
the firmware speed limitations.
DS705PP8
18
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
PCP_A[3:0]
PCP_D[7:0]
PCP_CS
tiah
LSP
tidhr
MSP
tias
tidd
ticdr
tidis
PCP_WR
PCP_RD
tirpw
tird
tirdtw
tirdirqh
PCP_IRQ
Figure 7. Parallel Control Port - Intel® Slave Mode Read Cycle
PCP_A[3:0]
PCP_D[7:0]
PCP_CS
tiah
LSP
MSP
tias
tidhw
ticdw
tidsu
PCP_RD
tiwpw
tiwd
tiwtrd
PCP_WR
PCP_BSY
tiwrbsyl
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle
DS705PP8
19
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
®
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Parameter
Address setup before PCP_CS and PCP_DS low
Address hold time after PCP_CS and PCP_DS low
Read
Symbol Min
Typical
—
Max
—
Unit
ns
t
t
5
5
mas
—
—
ns
mah
t
0
—
—
ns
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS# low
mcdr
t
—
24
8
—
—
—
—
—
19
—
—
18
—
ns
ns
ns
ns
ns
Data valid after PCP_CS and PCP_DS low with PCP_R/W high
PCP_CS and PCP_DS low for read
mdd
t
mrpw
t
Data hold time after PCP_CS or PCP_DS high after read
Data high-Z after PCP_CS or PCP_DS high after read
mdhr
t
—
30
mdis
t
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
read1
mrd
t
30
—
—
—
—
ns
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1
mrdtw
t
12
PCP_RW rising to PCP_IRQ falling
mrwirqh
Write
t
0
—
—
ns
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
mcdw
t
8
24
24
8
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Data setup before PCP_CS or PCP_DS high
PCP_CS and PCP_DS low for write
mdsu
t
mwpw
t
PCP_R/W setup before PCP_CS AND PCP_DS low
PCP_R/W hold time after PCP_CS or PCP_DS high
Data hold after PCP_CS or PCP_DS high
mrwsu
t
mrwhld
t
t
8
mdhw
30
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next read1
mwtrd
t
30
—
—
—
—
ns
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1
mwd
t
2*DCLKP + 20
PCP_RW rising to PCP_BSY falling
mrwbsyl
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing
the input data buffer. AN288 CS4953xx/CS497xxx Firmware User’s Manual should be consulted for the firmware
speed limitations.
DS705PP8
20
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
PCP_A[3:0]
PCP_AD[7:0]
PCP_CS
tmas
tmah
LSP
tmdhr
MSP
tmdd
tmrwsu
tmcdr
tmdis
tmrwhld
PCP_WR
tmrdtw
tmrpw
tmrd
PCP_DS
tmrwirqh
PCP_IRQ
Figure 9. Parallel Control Port - Motorola® Slave Mode Read Cycle Timing
PCP_A[3:0]
tmas
t
mah
LSP
tmdsu
MSP
PCP_AD[7:0]
PCP_CS
tmdhw
tmrwhld
tmwpw
tmcdw
PCP_WR
PCP_DS
tmrwsu
tmwd
tmwtrd
tmrwirql
PCP_IRQ
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing
DS705PP8
21
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.16 Switching Characteristics — Digital Audio Slave Input Port
Parameter
Symbol
Min
40
45
10
10
10
5
Max
—
Unit
ns
%
DAI_SCLK period
T
daiclkp
DAI_SCLK duty cycle
—
55
—
DAI_LRCLK transition from DAI_SCLK active edge
DAI_SCLK active edge from DAI_LRCLK transition
Setup time DAI_DATAn
t
t
ns
ns
ns
ns
daisstlr
daislrts
—
t
—
daidsu
Hold time DAI_DATAn
t
—
daidh
Note: In these diagrams, falling edge is the inactive edge of DAI_SCLK.
DAI_SCLK
tdaidsu
tdaidh
DAI_DATAn
Figure 11. Digital Audio Input (DAI) Port Timing Diagram
Tdaiclkp
tdaislrts
DAI_LRCLK
DAI_LRCLK
DAI_SCLK
DAI_SCLK
Tdaiclkp
tdaisstlr
DAIn_DATAn
DAIn_DATAn
Figure 12. DAI Slave Timing Diagram
DS705PP8
22
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.17 Switching Characteristics — Digital Audio Output Port
Parameter
Symbol
Min
40
Max
—
Unit
ns
DAO_MCLK period
T
daomclk
DAO_MCLK duty cycle
—
45
55
%
DAO_SCLK period for Master or Slave mode1
DAO_SCLK duty cycle for Master or Slave mode1
T
40
—
ns
daosclk
—
40
60
%
1,2
Master Mode (Output A1 Mode)
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input
t
t
—
19
ns
daomsck
3
DAO_SCLK delay from DAO_LRCLK transition
t
—
—
—
8
8
ns
ns
ns
daomlrts
3
DAO_LRCLK delay from DAO_SCLK transition
daomstlr
DAO1_DATA[3..0], DAO2_DATA[1..0]
t
10
daomdv
3
delay from DAO_SCLK transition
4
Slave Mode (Output A0 Mode)
DAO_SCLK active edge to DAO_LRCLK transition
DAO_LRCLK transition to DAO_SCLK active edge
DAO_Dx delay from DAO_SCLK inactive edge
t
10
10
—
—
—
11
ns
ns
ns
daosstlr
t
daoslrts
t
daosdv
1. Master mode timing specifications are characterized, not production tested.
2. Master mode is defined as the CS4953xx driving both DAO_SCLK and DAO_LRCLK. When MCLK is an input, it is
divided to produce DAO_SCLK, DAO_LRCLK.
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
point at which the data is valid.
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
tdaomlclk
tdaomclk
DAO_MCLK
DAO_SCLK
DAO_MCLK
DAO_SCLK
tdaomsck
tdaomsck
tdaomdv
DAOn_DATAn
DAO_LRCLK
DAOn_DATAn
tdaomlrts
tdaomstlr
DAO_LRCLK
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 13. Digital Audio Port Output Timing Master Mode
DS705PP8
23
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
tdaosclk
DAO_LRCLK
DAO_SCLK
DAO_LRCLK
DAO_SCLK
tdaoslrts
tdaosclk
tdaosstlr
tdaosdv
DAO_Dx
DAO_Dx
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK
Figure 14. Digital Audio Output Timing, Slave Mode (Relationship LRCLK to SCLK)
5.18 Switching Characteristics — SDRAM Interface
Refer to Figure 15 through Figure 18.
(SD_CLKOUT = SD_CLKIN)
Parameter
Symbol
Min
2.3
2.3
—
Typical
—
Max
—
—
1
Unit
ns
SD_CLKIN high time
SD_CLKIN low time
t
sdclkh
t
—
ns
sdclkl
SD_CLKOUT rise/fall time
t
—
ns
sdclkrf
SD_CLKOUT Frequency
—
—
150
—
—
55
3.8
—
—
—
—
—
—
MHz
%
SD_CLKOUT duty cycle
—
45
SD_CLKOUT rising edge to signal valid
Signal hold from SD_CLKOUT rising edge
SD_CLKOUT rising edge to SD_DQMn valid
SD_DQMn hold from SD_CLKOUT rising edge
SD_DATA valid setup to SD_CLKIN rising edge
SD_DATA valid hold to SD_CLKIN rising edge
SD_CLKOUT rising edge to ADDRn valid
t
—
—
ns
sdcmdv
sdcmdh
t
—
1.1
3.8
—
ns
t
—
ns
sddqv
t
1.38
1.3
1.38
—
ns
sddqh
t
—
ns
sddsu
t
—
ns
sddh
t
3.8
ns
sdav
DS705PP8
24
SD_CLKOUT
SD_CS
tsdclkrf
tsdcmdv
tsdcmdh
SD_RAS
SD_CAS
SD_WE
tsddqh
tsddqv
SD_DQMn
11
00
SD_An
tsdav
tsddsu
tsddh
CAS=2
LSP1
MSP1
LSP2
MSP2
SD_Dn
LSP0
MSP0
LSP3
MSP3
SD_CLKIN
tsdclkl
tsdclkh
Figure 15. External Memory Interface - SDRAM Burst Read Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
LSP0
MSP0
LSP1
MSP1
LSP2
MSP2
LSP3
MSP3
SD_Dn
SD_An
tsdav
SD_DQMn
00
11
tsddqv
tsddqh
Figure 16. External Memory Interface - SDRAM Burst Write Cycle
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
SD_CLKOUT
tsdcmdv
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_An
SD_Dn
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle
SD_CLKOUT
tsdcmdv
tsdcmdh
SD_CS
SD_RAS
SD_CAS
SD_WE
SD_DQMn
SD_An
OPCODE
SD_Dn
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle
DS705PP8
26
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
6 Ordering Information
The CS4953xx family part number is described as follows:
CS495NNI-XYZ
where
NN - Product Number Variant
I - ROM ID Number
X - Product Grade
Y - Package Type
Z - Lead (Pb) Free
Table 5. Ordering Information
Part No.
Status
Grade
Temp. Range
Package
Status
CS495303-CVZ
NRND
NRND
EOL
—
—
—
—
—
—
—
—
—
—
—
128-pin LQFP
144-pin LQFP
128-pin LQFP
CS495303-CVZR1
CS495303-CQZ
CS495304-CVZ
Commercial
0 to +70 °C
EOL
CS495304-CVZR1
CS495304-DVZ
EOL
EOL
Automotive
Commercial
Commercial
-40 to +85 °C
0 to +70 °C
0 to +70 °C
128-pin LQFP
144-pin LQFP
128-pin LQFP
128-pin LQFP
CS495304-DVZR1
CS495313-CQZ
EOL
EOL
CS495313-CQZR1
CS495313-CVZ
EOL
NRND
NRND
CS495313-CVZR1
CS495314-CVZ2
Active
—
CS495314-CVZR1,2
CS495314-CQZ
CS495314-DVZ
Active
EOL
—
—
—
—
Commercial
Automotive
0 to +70 °C
144-pin LQFP
128-pin LQFP
128-pin LQFP
Active
CS495314-DVZR1
Note 3
-40 to +85 °C
1. R = Tape and Reel
2. Recommended for new designs. See Section 2 for details about Cirrus Logic design recommendations.
3. Contact the factory for availability of the -D (automotive grade) package
.
DS705PP8
27
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
7 Environmental, Manufacturing, and Handling Information
Table 6. Environmental, Manufacturing, and Handling Information
Model Number
Peak Reflow Temp
MSL Rating*
Max Floor Life
CS495303-CVZ
CS495303-CVZR
CS495304-CVZ
CS495304-CVZR
CS495304-DVZ
CS495304-DVZR
CS495313-CQZ
CS495313-CQZR
CS495313-CVZ
CS495313-CVZR
CS495314-CVZ
CS495314-CVZR
CS495314-DVZ
CS495314-DVZR
260 °C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
DS705PP8
28
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
8 Device Pinout Diagrams
8.1 128-pin LQFP Pinout Diagrams (CS495303/CS495313)
The CS495303/CS495313 DSP with a 128-pin package is not recommended for new designs. See
Section 2 for details about this Cirrus Logic recommendation.
1
5
SD_A0, EXT_A0
SD_A1, EXT_A1
GPIO38, PCP_WR, PCP_DS, SCP2_CLK
GPIO11, PCP_A3, PCP_AS, SCP2_MISO, SCP2_SDA
100
GPIO10, PCP_A2, PCP_A10, SCP2_MOSI
VDDIO5
SD_A2, EXT_A2
GPOI9, SCP1_IRQ
GND4
GPIO8, PCP_IRQ, SCP2_IRQ
SD_A3, EXT_A3
SD_A4, EXT_A4
GPIO7, SCP1_CS, IOWAIT
GPIO6, PCP_CS, SCP2_CS
95 VDD4
EXT_CS2
VDDIO7
GNDIO7
GPIO3, DDAC
GPIO2
SD_A5, EXT_A5
GNDIO4
10
SD_A6, EXT_A6
90 SD_A7, EXT_A7
VDDIO4
VDD7
GPIO1
GPIO0
SD_A8, EXT_A8
SD_A9, EXT_A9
GND3
GND7 15
XTAL_OUT
XTI
85 SD_A11, EXT_A11
SD_A12, EXT_A12
VDD3
XTO
GNDA
128-pin LQFP
(CS495303/CS49513)
20
25
30
35
PLL_REF_RES
SD_CLKEN
VDDA (3.3V)
SD_CLKIN
VDD8
80 SD_CLKOUT
SD_DQM1
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8
SD_D8, EXT_D8
SD_D9, EXT_D9
GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0
VDDIO8
75 SD_D10, EXT_D10
SD_D11, EXT_D11
VDDIO3
DAI1_SCLK, DSD_CLK
DAI1_LRCLK, DSD4
SD_D12, EXT_D12
SD_D13, EXT_D13
70 SD_D14, EXT_D14
SD_D15, EXT_D15
SD_D0, EXT_D0
GNDIO8
GPIO42, BDI_REQ, DAI2_LRCLK, PCP_IRQ, PCP_BSY
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO26, DAO2_DATA3, XMTB
GNDIO2
EXT_WE
DBDA
DBCK
65 SD_D1, EXT_D1
GPIO20, DAO2_DATA2, EE_CS
Figure 19. 128-pin LQFP Pin-Out Drawing (CS495303/CS495313)
DS705PP8
29
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
8.2 128-pin LQFP Pinout Diagrams (CS495304/CS495314)
The CS495304/CS495314 DSP with a 128-pin package is recommended for new designs. See Section 2 for
details about this Cirrus Logic recommendation.
1
5
SD_A0, EXT_A0
SD_A1, EXT_A1
GPIO38, PCP_WR, PCP_DS, SCP2_CLK
GPIO11, PCP_A3, PCP_AS, SCP2_MISO, SCP2_SDA
100
GPIO10, PCP_A2, PCP_A10, SCP2_MOSI
GPOI9, SCP1_IRQ
GPIO8, PCP_IRQ, SCP2_IRQ
GPIO7, SCP1_CS, IOWAIT
GPIO6, PCP_CS, SCP2_CS
VDDIO7
VDDIO5
SD_A2, EXT_A2
GND4
SD_A3, EXT_A3
SD_A4, EXT_A4
95 VDD4
EXT_CS2
GNDIO7
SD_A5, EXT_A5
GNDIO4
10
GPIO3, DDAC
GPIO2
SD_A6, EXT_A6
90 SD_A7, EXT_A7
VDDIO4
VDD7
GPIO1
GPIO0, UART_CLK, EE_CS
SD_A8, EXT_A8
SD_A9, EXT_A9
GND3
GND7 15
XTAL_OUT
XTI
85 SD_A11, EXT_A11
SD_A12, EXT_A12
VDD3
XTO
GNDA
128-pin LQFP
(CS495304/CS495314)
20
25
30
35
PLL_REF_RES
SD_CLKEN
VDDA (3.3V)
SD_CLKIN
VDD8
80 SD_CLKOUT
SD_DQM1
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8
SD_D8, EXT_D8
SD_D9, EXT_D9
GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0
VDDIO8
75 SD_D10, EXT_D10
SD_D11, EXT_D11
VDDIO3
DAI1_SCLK, DSD_CLK
DAI1_LRCLK, DSD4
SD_D12, EXT_D12
SD_D13, EXT_D13
70 SD_D14, EXT_D14
SD_D15, EXT_D15
SD_D0, EXT_D0
GNDIO8
GPIO42, BDI_REQ , DAI2_LRCLK, PCP_IRQ, PCP_IBSY
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO26, DAO2_DATA3, XMTB
GNDIO2
EXT_WE
DBDA
DBCK
65 SD_D1, EXT_D1
GPIO20, DAO2_DATA2
Figure 20. 128-pin LQFP Pin-Out Drawing (CS495304/CS495314)
DS705PP8
30
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
8.3 144-pin LQFP Pinout Diagrams (CS495313)
The CS495313 DSP with a 144-pin package is not recommended for new designs. See Section 2 for details
about this Cirrus Logic recommendation.
109
110
72 SD_A0, EXT_A0
SD_A1, EXT_A1
70 SD_A2, EXT_A2
69 GND4
GPIO9, PCP_A1, PCP_A9
GPIO8, PCP_A0, PCP_A8
GPIO7, PCP_AD7, PCP_D7
GPIO6, PCP_AD6, PCP_D6
VDDIO7
113
SD_A3, EXT_A3
SD_A4, EXT_A4
66 VDD4
GPIO5, PCP_AD5, PCP_D5
GPIO4, PCP_AD4, PCP_D4
GNDIO7
115
116
65 EXT_CS2
SD_A5, EXT_A5
63 GNDIO4
GPIO3, PCP_AD3, PCP_D3
GPIO2, PCP_AD2, PCP_D2
VDD7
119
SD_A6, EXT_A6
SD_A7, EXT_A7
60 VDDIO4
GPIO1, PCP_AD1, PCP_D1 120
GPIO0, PCP_AD0, PCP_D0
GND7 122
SD_A8, EXT_A8
SD_A9, EXT_A9
57 GND3
XTAL_OUT
XTI
125
SD_A11, EXT_A11
55 SD_A12, EXT_A12
XTO
144-pin LQFP
(CS495313)
GNDA 126
NC
54
VDD3
PLL_REF_RES
SD_CLKEN
SD_CLKIN
SD_CLKOUT
VDDA (3.3V) 129
VDD8 130
GPIO14, DAI1_DATA3, TM3, DSD3
GPIO13, DAI1_DATA2, TM2, DSD2
GND8 133
50 SD_DQM1
SD_D8, EXT_D8
SD_D9, EXT_D9
47 GNDIO3
GPIO12, DAI1_DATA1, TM1, DSD1
DAI1_DATA0, TM0, DSD0 135
VDDIO8 136
SD_D10, EXT_D10
45 SD_D11, EXT_D11
44 VDDIO3
DAI1_SCLK, DSD_CLK
DAI1_LRCLK, DSD4
SD_D12, EXT_D12
SD_D13, EXT_D13
SD_D14, EXT_D14
40 SD_D15, EXT_D15
SD_D0, EXT_D0
GNDIO8 139
PIO42, BDI_REQ , DAI2_LRCLK, PCP_IRQ, PCP_BSY 140
GPIO43, BDI_CLK, DAI2_SCLK
BDI_DATA, DAI2_DATA, DSD5
GPIO27
EXT_WE
GPIO26 144
37 SD_D1, EXT_D1
Figure 21. 144-pin LQFP Pin-Out Drawing (CS495313)
DS705PP8
31
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9 Package Mechanical Drawings
9.1 128-pin LQFP Package Drawing
D
D1
E1
E
1
e
b
∝
A
A1
L
Figure 22. 128-pin LQFP Package Drawing
Table 7. 128-pin LQFP Package Characteristics
MILLIMETERS
INCHES
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
A1
b
—
—
1.60
0.15
0.27
—
—
—
.063”
.006”
.011”
0.05
0.17
—
.002”
.007”
0.22
.009”
.866”
.787”
.630”
.551”
.020”
3.5
D
22.00 BSC
20.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
3.5
D1
E
E1
e
q
0°
7°
0°
7°
L
0.45
0.60
0.75
.018”
.024”
.039” REF
.030”
L1
1.00 REF
TOLERANCES OF FORM AND POSITION
ddd
0.08
.003”
DS705PP8
32
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9.2 144-pin LQFP Package Drawing
E
E1
D D1
Notes:
SEATING PLANE
B
e
b
ddd
B
1. Controlling dimension is millimeter.
2. Dimensioning and tolerancing per ASME
L1
Y14.5M-1994.
θ
A
A1
L
Figure 23. 144-pin LQFP Package Drawing
Table 8. 144-pin LQFP Package Characteristics
MILLIMETERS
INCHES
DIM
MIN
NOM
MAX
MIN
NOM
MAX
A
A1
b
—
—
1.60
0.15
0.27
—
—
—
.063”
.006”
.011”
0.05
0.17
—
.002”
.007”
0.22
.009”
.866”
.787”
.866”
.787”
.020”
—
D
22.00 BSC
20.00 BSC
22.00 BSC
20.00 BSC
0.50 BSC
—
D1
E
E1
e
q
0°
7°
0°
7°
L
0.45
0.60
0.75
.018”
.024”
.039” REF
.030”
L1
1.00 REF
TOLERANCES OF FORM AND POSITION
ddd
0.08
.003”
DS705PP8
33
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
10 Revision History
Revision
Date
FEB 2006
Changes
A1
A2
Advance release.
JUN 2006
Updated part numbers for ordering (Tables 5 & 6), Updated VOH and VOL
specification to include the current load used for testing
A3
JUL 2006
Updated part numbers for ordering (Tables 5 & 6). Updated text in sections 3 and 4.
Updated parameter descriptions in sections 5.1 and 5.3. Updated Tspickl, Tspickh,
and Tspidov timing. Corrected Figure SPI Master Timing to use EE_CS. Added foot-
note to XTI table. Removed SCLK/LRCLK relative timing from DAI port timing.
Removed SCLK/LRCLK slave relative timing from DAO port timing.
A4
OCT 2007
Updated the Tspidsu, Tspickl, and Tspickh timing parameters for master mode SPI.
This applies to both SPI ports.
PP1
PP2
May 28, 2008
June 20, 2008
Updated product feature list in Table 2. Updated Figure 19 and Figure 21.
Added typical crystal frequency values in Table Footnote 1 and minimum and
maximum values of Fxtalin Section 5.8. Redefined Master mode clock speed for
SCP_CLK in Section 5.11. Redefined DC leakage characterization data in
Section 5.3, correcting units of measurement. Modified Footnote 1 under
Section 5.10.
PP3
PP4
September 24, 2008 Removed references to External Parallel Flash / SRAM Interface.
June 9, 2009
Updated product number references in Section 5.9, Section 6, Section 7, Table
2,.Table 3, and Table 4. For all Active Low pins, changed Active Low pin
designation from “#” character after the pin name to a line over the pin name as in
“EE_CS”. Removed Active Low designation from the BDI_REQ pin in the 128-pin
pinout drawings in Figure 19 and Figure 20, and in the 144-pin pinout drawings in
Figure 21 and Figure 22. Updated the pin names referred to in the timing diagrams
in Figure 9, Figure 10, Figure 17, and Figure 18. Updated the parameters in Section
5.15.
PP5
PP6
July 29, 2009
Updated Figure 19, Figure 20, Figure 21. Removed CS495314-CQZ and
CS495314-CQZR from Table 5 and Table 6. Added recommendation that CS4953x4
family be used with new designs. Updated Section 2
November 11, 2009
Removed references to UART port. Removed references to 11.2896,
18.432, and 27 MHz frequency clocks in Note 1 in Section 5.8 “Switching
Characteristics — XTI” on page 12 and the minimum and maximum
External Crystal Operating Frequency values in that same section. Updated
Section 5.17 “Switching Characteristics — Digital Audio Output Port” on
page 23. In Figure 21, "144-pin LQFP Pin-Out Drawing (CS495313)", on
page 31, moved SCP2_SDA from Pin 106 to Pin 105, deleted duplicate
EE_CS from Pin 25, and designated Pin 140 BDI_REQ as active low.
Designated Pin 32, BDI_REQ as active low In Figure 19, "128-pin LQFP
Pin-Out Drawing (CS495303/CS495313)", on page 29 and in Figure 20,
"128-pin LQFP Pin-Out Drawing (CS495304/CS495314)", on page 30. In
Section 5.3, the parameter, “Input leakage current (all digital pins with
internal pull-up resistors enabled, and XTI)”, Max value changes from 50 μA
to 70 μA. In Section 5.13, the parameter SCP_CLK low to SCP_SDA out
valid with symbol “tiicdov” maximum value changes from 18 ns to 36 ns.
PP7
June 2, 2010
Updated Table 5 to show status of various parts.
DS705PP8
34
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Revision
PP8
Date
Changes
Added Tj conditions to Section 5.2.
April 19, 2011
Changed 500 ma to 350 ma in Section 5.4.
Removed references to DSD.
Updated legal statement.
Updated features list.
Updated Section 5.16 “Switching Characteristics — Digital Audio Slave
Input Port” on page 22
Updated Section 5.17 “Switching Characteristics — Digital Audio Output
Port” on page 23.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com.
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to
change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant infor-
mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the
use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties.
This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights,
trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER-
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NESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S
CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEM-
NIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS'
FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, Cirrus Logic logo designs, DSP Composer, DSP Condenser, and CLIDE are trademarks of Cirrus Logic, Inc.
THX is a registered trademark of THX, Ltd. THX Select 2 and THX Ultra 2 are trademarks of THX, Ltd.
AAC, AC-3, Audistry, Dolby, Dolby Digital, Dolby Digital Plus, Dolby TrueHD, Dolby Volume, Dolby Headphone 2, Dolby Virtual Speaker 2, Pro Logic, Surround EX,
are either trademarks or registered trademarks of Dolby Laboratories, Inc. Supply of an implementation of Dolby Technology does not convey a license nor imply a
right under any patent, or any other industrial or Intellectual Property Right of Dolby Laboratories, to use the Implementation in any finished end-user or ready-to-use
final product. It is hereby notified that a license for such use is required from Dolby Laboratories.
DTS, DTS Digital Surround, and DTS-HD are registered trademarks of the Digital Theater Systems, Inc. DTS Neo:6, DTS-ES 96/24, DTS-ES, DTS 6.1, DTS 96/24,
DTS Neural Surround, and DTS Express are trademarks of Digital Theater Systems, Inc. It is hereby notified that a third-party license from DTS is necessary to dis-
tribute software of DTS in any finished end-user or ready-to-use final product.
SRS, SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Head-
phone, SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS
TruSurround HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD are either trademarks or registered trademarks of SRS Labs, Inc. SRS,
SRS 3D, SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone,
SRS Headphone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSur-
round HD4, SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies are incorporated under license from SRS Labs, Inc. SRS, SRS 3D,
SRS CS Auto, SRS CS Headphone, SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Head-
phone 360, SRS HPF, SRS StudioSound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSurround HD4,
SRS TruVolume, SRS VIP+, SRS WOW, SRS WOW XT, SRS WOW HD technologies incorporated in the Cirrus Logic CS4953xx products are owned by SRS Labs,
a U.S. Corporation and licensed to Cirrus Logic, Inc. Purchaser of Cirrus Logic CS4953xx products must sign a license for use of the chip and display of the SRS Labs
trademarks. Any products incorporating the Cirrus Logic CS4953xx products must be sent to SRS Labs for review. SRS, SRS 3D, SRS CS Auto, SRS CS Headphone,
SRS Circle Cinema 3D, SRS Circle Surround, SRS Circle Surround II, SRS GEQ, SRS Hardlimiter, SRS Headphone, SRS Headphone 360, SRS HPF, SRS Studio-
Sound HD, SRS TruEQ, SRS TruMedia, SRS TruSurround, SRS TruSurround XT, SRS TruSurround HD, SRS TruSurround HD4, SRS TruVolume, SRS VIP+, SRS
WOW, SRS WOW XT, SRS WOW HD technologies are protected under US and foreign patents issued and/or pending. Neither the purchase of the Cirrus Logic
CS4953xx products, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercialized recordings made with any SRS technolo-
gy/solution. SRS Labs requires all set makers to comply with all rules and regulations as outlined in the SRS Trademark Usage Manual.
Microsoft and Windows Media are registered trademarks of Microsoft Corporation. The product includes technology owned by Microsoft Corporation and cannot be
used or distributed without a license from Microsoft Licensing, Inc.
Motorola and SPI are trademarks of Motorola, Inc.
Intel is a registered trademark of Intel Corporation.
I2C is a trademark of Philips Semiconductor.
All other brand and product names in this document may be trademarks or service marks of their respective owners.
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