CS4954_技术文档

CS4954

CS4955

NTSC/PAL Digital Video Encoder

Features

Description

The CS4954/5 provides full conversion from digital video

formats YCbCr or YUV into NTSC and PAL Composite,

Y/C (S-video) and RGB, or YUV analog video. Input for-

mats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU

R.BT656 with support for EAV/SAV codes. Video output

can be formatted to be compatible with NTSC-M, NTSC-

J, PAL-B,D,G,H,I,M,N, and Combination N systems.

Closed Caption is supported in NTSC. Teletext is sup-

ported for NTSC and PAL.

l Six DACs providing simultaneous composite,

S-video, and RGB or Component YUV

outputs

l Programmable DAC output currents for low

imped-ance (37.5 Ω) and high impedance

(150 Ω) loads.

l Multi-standard support for NTSC-M, NTSC-

JAPAN, PAL (B, D, G, H, I, M, N,

Combination N)

l ITU R.BT656 input mode supporting

EAV/SAV codes and CCIR601 Master/Slave

input modes

Six 10-bit DACs provide two channels for an S-Video

output port, one or two composite video outputs, and

three RGB or YUV outputs. Two-times oversampling re-

duces the output filter requirements and guarantees no

DAC-related modulation components within the speci-

fied bandwidth of any of the supported video standards.

l Programmable HSYNC and VSYNC timing

l Multistandard Teletext (Europe, NABTS,

WST) support

l VBI encoding support

l Wide-Screen Signaling (WSS) support, EIA-J

Parallel or high-speed I²C compatible control interfaces are

provided for flexibility in system design. The parallel interface

doubles as a general purpose I/O port when the CS4954/5 is

in I²C mode to help conserve valuable board area.

CPX1204

ORDERING INFORMATION

l NTSC closed caption encoder with interrupt

l CS4955 supports Macrovision copy

CS4954-CQ

CS4955-CQ

48-pin TQFP

protection Version 7

l Host interface configurable

for parallel or I C

compatible operation

l On-chip voltage reference

VAA

2

CLK

Output

Interpolate

LPF

10-Bit

DAC

I²C Interface

C

SCL

SDA

8

Control

Registers

10-Bit

Chroma Amplifier

Chroma Modulate

Burst Insert

Σ

PDAT[7:0]

RD

CVBS

DAC

Host

Parallel

generator

WR

10-Bit

DAC

Interface

Y

R

G

B

ADDR

l +3.3 V or +5 V operation,

CMOS, low-power modes,

tri-state DACs

XTAL_IN

XTAL_OUT

10-Bit

DAC

Color Sub-carrier Synthesizer

Chroma Interpolate

10-Bit

DAC

YCbCr to RBG

LPF

U,V

Teletext

Encoder

TTXDAT

TTXRQ

Color Space

Converter

10-Bit

DAC

8

Y

Video Formatter

VD[7:0]

Luma Interpolate

Luma Amplifier

HSYNC

VSYNC

FIELD

INT

Voltage

Reference

VREF

ISET

Video Timing

Generator

Current

Reference

Y

Sync Insert

RESET

RGB

DGND

TEST

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

Cirrus Logic, Inc.

APR ‘99

DS278PP4

Copyright Cirrus Logic, Inc. 1999

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

1

CS4954 CS4955

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................5

AC & DC PARAMETRIC SPECIFICATIONS ......................................................................5

RECOMMENDED OPERATING CONDITIONS .....................................................................5

DC CHARACTERISTICS ....................................................................................................5

AC CHARACTERISTIC .......................................................................................................7

TIMING CHARACTERISTICS .............................................................................................8

2. ADDITIONAL CS4954/5 FEATURES ...............................................................................10

3. CS4954 INTRODUCTION .................................................................................................10

4. FUNCTIONAL DESCRIPTION .........................................................................................10

4.1. Video Timing Generator .........................................................................................10

4.2. Video Input Formatter .............................................................................................11

4.3. Color Subcarrier Synthesizer ..................................................................................11

4.4. Chroma Path ..........................................................................................................11

4.5. Luma Path ..............................................................................................................12

4.6. RGB Path and Component YUV Path ....................................................................12

4.7. Digital to Analog Converters ...................................................................................12

4.8. Voltage Reference ..................................................................................................13

4.9. Current Reference ..................................................................................................13

4.10. Host Interface .........................................................................................................13

4.11. Closed Caption Services ........................................................................................13

4.12. Teletext Services ....................................................................................................14

4.13. Wide-Screen Signaling Support and CGMS ...........................................................14

4.14. VBI Encoding ..........................................................................................................14

4.15. Control Registers ....................................................................................................14

4.16. Testability ...............................................................................................................14

5. OPERATIONAL DESCRIPTION .......................................................................................14

5.1. Reset Hierarchy ......................................................................................................14

5.2. Video Timing ...........................................................................................................15

5.2.1. Slave Mode Input Interface ..........................................................................15

5.2.2. Master Mode Input Interface ........................................................................15

5.2.3. Vertical Timing .............................................................................................16

5.2.4. Horizontal Timing .........................................................................................16

5.2.5. NTSC Interlaced ..........................................................................................16

5.2.6. PAL Interlaced .............................................................................................16

5.2.7. Progressive Scan .........................................................................................17

5.2.8. NTSC Progressive Scan ..............................................................................17

5.2.9. PAL Progressive Scan .................................................................................18

5.3. ITU-R.BT656 ..........................................................................................................18

5.4. Digital Video Input Modes .......................................................................................21

5.5. Multi-standard Output Format Modes .....................................................................21

5.6. Subcarrier Generation ............................................................................................21

5.7. Subcarrier Compensation .......................................................................................21

5.8. Closed Caption Insertion ........................................................................................22

5.9. Programmable H-sync and V-sync .........................................................................22

5.10. Wide Screen Signaling (WSS) and CGMS .............................................................23

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-

mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information

contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights

of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of

this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or

otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no

part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,

photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture

or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing

in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-

marks and service marks can be found at http://www.cirrus.com.

2

DS278PP4

CS4954 CS4955

5.11. Teletext Support .....................................................................................................23

5.12. Color Bar Generator ...............................................................................................25

5.13. VBI encoding ..........................................................................................................25

5.14. Super White/Super Black support ..........................................................................26

5.15. Interrupts ................................................................................................................26

5.16. General Purpose I/O Port .......................................................................................26

6. FILTER RESPONSES ......................................................................................................27

7. ANALOG ..........................................................................................................................30

7.1. Analog Timing ........................................................................................................30

7.2. VREF ......................................................................................................................30

7.3. ISET .......................................................................................................................30

7.4. DACs ......................................................................................................................30

7.4.1. Luminance DAC ..........................................................................................30

7.4.2. Chrominance DAC ......................................................................................30

7.4.3. CVBS DAC ..................................................................................................31

7.4.4. Red DAC .....................................................................................................31

7.4.5. Green DAC ..................................................................................................31

7.4.6. Blue DAC .....................................................................................................31

8. PROGRAMMING ..............................................................................................................32

8.1. Host Control Interface ............................................................................................32

8.1.1. I²C Interface ................................................................................................32

8.1.2. 8-bit Parallel Interface .................................................................................33

8.2. Register Description ...............................................................................................34

8.2.1. Control Registers .........................................................................................34

9. BOARD DESIGN AND LAYOUT CONSIDERATIONS ....................................................50

9.1. Power and Ground Planes .....................................................................................50

9.2. Power Supply Decoupling ......................................................................................50

9.3. Digital Interconnect ................................................................................................50

9.4. Analog Interconnect ...............................................................................................50

9.5. Analog Output Protection .......................................................................................51

9.6. ESD Protection .......................................................................................................51

9.7. External DAC Output Filter .....................................................................................51

10. PIN DESCRIPTION .........................................................................................................53

11. PACKAGE DRAWING ......................................................................................................55

DS278PP4

3

CS4954 CS4955

TABLE OF FIGURES

1. Video Pixel Data and Control Port Timing .........................................................................7

2. I²C Host Port Timing ..........................................................................................................8

3. Reset Timing ......................................................................................................................9

4. ITU R.BT601 Input Slave Mode Horizontal Timing ..........................................................15

5. ITU R.BT601 Input Master Mode Horizontal Timing ........................................................15

6. Vertical Timing .................................................................................................................17

7. NTSC Video Interlaced Timing ........................................................................................18

8. PAL Video Interlaced Timing ...........................................................................................19

9. NTSC Video Non-Interlaced Progressive Scan Timing ...................................................20

10. PAL Video Non-Interlaced Progressive Scan Timing ......................................................20

11. CCIR656 Input Mode Timing ...........................................................................................21

12. Teletext Timing (Pulsation Mode) ....................................................................................24

13. Teletext Timing (Window Mode) ......................................................................................24

14. 1.3 Mhz Chrominance low-pass filter transfer characteristic ...........................................27

15. 1.3 Mhz Chrominance low-pass filter transfer characterstic (passband) .........................27

16. 650 kHz Chrominance low-pass filter transfer characteristic ...........................................27

17. 650 kHz Chrominance low-pass filter transfer characteristic (passband) ........................27

18. Chrominance output interpolation filter transfer characteristic (passband) ......................28

19. Luminance interpolation filter transfer characteristic .......................................................28

20. Luminance interpolation filter transfer characterstic (passband) .....................................28

21. Chrominance interpolation filter transfer characteristic for RGB datapath .......................28

22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) .............29

23. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) .............29

24. Chroma Interpolator for RGB Datapath when rgb_bw=0 -3 dB .......................................29

25. Chroma Interpolator for RGB Datapath when rgb_bw=0 (Full Scale) ..............................29

26. I²C Protocol .....................................................................................................................32

27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle ........................................33

28. 8-bit Parallel Host Port Timing: Address Read Cycle ......................................................33

29. 8-bit Parallel Host Port Timing: Address Write Cycle .......................................................34

30. External Low Pass Filter C₂should be chosen so that C₁= C₂+ C_cable.........................51

31. Typical Connection Diagram ............................................................................................52

4

DS278PP4

CS4954 CS4955

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

AC & DC PARAMETRIC SPECIFICATIONS _{(AGND,DGND = 0 V, all voltages with respect to 0 V}

)

Parameter

Symbol

Min

-0.3

-10

-50

-0.3

-55

-65

Max

6.0

Units

V

Power Supply

VAA/VDD

Input Current Per Pin (Except Supply Pins)

Output Current Per Pin (Except Supply Pins)

Analog Input Voltage

10

mA

V

+50

VAA + 0.3

VDD + 0.3

+ 125

+ 150

Digital Input Voltage

V

Ambient Temperature Power Applied

Storage Temperature

°C

WARNING: Operating beyond these limits can result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND,DGND = 0 V, all voltages with respect to 0 V.)

Parameter

Power Supplies: Digital Analog

Symbol

Min

Typ

Max

Units

VAA/VDD

3.15

4.75

3.3

5.0

3.45

5.25

V

Operating Ambient Temperature

Note: Operation outside the ranges is not recommended.

TA

0

+ 25

+ 70

°C

DC CHARACTERISTICS (T_A= 25° C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.)

Parameter

Symbol

Min

Typ

Max

Units

Digital Inputs

High level Input Voltage

V [7:0], PDAT [7:0], Hsync/Vsync/Field/CLKIN

High Level Input Voltage I²C

VIH

2.2

-

VDD+0.3

-

V

0.7 VDD

Low level Input Voltage All Inputs

Input Leakage Current

-

-0.3

-10

-

0.8

V

+10

µA

Digital Outputs

High Level Output Voltage lo = -4 mA

Low level Output Voltage lo = 4 mA

Low Level Output Voltage SDA pin only, lo = 6mA

Output Leakage Current High -Z Digital Outputs

VOH

VOL

-

2.4

-

VDD

0.4

V

-

0.4

V

-10

+ 10

µA

DS278PP4

5

CS4954 CS4955

DC CHARACTERISTICS (Continued)

Parameter

Analog Outputs

Symbol

Min

Typ

Max

Units

Full Scale Output Current CVBS/Y/C/R/G/B

LSB Current CVBS/Y/C/R/G/B

DAC-to DAC Matching

Output Compliance

(Notes 1, 2, 3)

(Notes 1, 2, 4)

(Notes 1, 2, 3)

(Notes 1, 2, 4)

(Note 1)

IO

32.9

34.7

8.68

33.9

8.48

2

36.5

9.13

35.7

8.92

-

mA

µA

%

8.22

IB

32.2

IB

8.04

MAT

VOC

-

0

-

(Note 1)

-

+ 1.4

-

V

Output Impedance

(Note 1) ROUT

(Note 1) COUT

(Note 1) ODEL

15

-

kΩ

pF

ns

Output Capacitance

-

30

DAC Output Delay

-

4

12

DAC Rise/Fall Time

(Note 1, 5)

TRF

-

2.5

5

ns

Voltage Reference

Reference Voltage Output

Reference Input Current

Power Supply

VOV

UVC

1.170 1.232

1.294

10

V

(Note 1)

-

uA

Supply Voltage

VAA, VDD 3.15

4.75

3.3

5.0

3.45

5.25

V

Digital Supply Current

IAA1

IAA2

-

70

100

60

-

mA

Analog Supply

Low-Z

High-Z

(Note 6)

(Note 7)

-

Analog Supply

IAA3

mA

Power Supply Rejection Ratio

Static Performance

DAC Resolution

PSRR

0.02

0.05

%/%

(Note 1)

-

10

+ 1

+ 2

Bits

LSB

Differential Non-Linearity

Integral Non-Linearity

Dynamic Performance

Differential Gain

DNL

INL

-1

- 2

+ 0.5

+ 1

(Note 1)

DG

DP

-

2

5

+ 2

2

%

°

Differential Phase

+ 0. 5

Hue Accuracy

HA

-

°

Signal to Noise Ratio

Saturation Accuracy

SNR

SAT

70

-

dB

%

(Note 1)

1

2

Notes: 1. Values are by characterization only

2. Output current levels with ISET = 4 KΩ , VREF = 1.232 V.

3. DACs are set to low impedance mode

4. DACs are set to high impedance mode

5. Times for black-to-white-level and white-to-black-level transitions.

6. Low-Z - 3 dacs on

7. High-Z - 6 dacs on

6

DS278PP4

CS4954 CS4955

AC CHARACTERISTIC

Parameter

Symbol

Min

Typ

Max

Units

Pixel Input and Control Port (Figure 1)

Clock Pulse High Time

Tch

Tcl

14.82 18.52 22.58

ns

Clock Pulse Low Time

Clock to Data Set-up Time

Clock to Data Hold Time

Tisu

Tih

6

0

-

Clock to Data Output Delay

Toa

17

CLK

T_isu

T_chT_cl

V[7:0]

T_ih

HSYNC/VSYNC

(Inputs)

T_oa

HSYNC/VSYNC

CB/FIELD/INT

(Outputs)

Figure 1. Video Pixel Data and Control Port Timing

DS278PP4

7

CS4954 CS4955

TIMING CHARACTERISTICS

Parameter

I²C Host Port Timing (Figure 2)

SCL Frequency

Symbol

Min

Typ

Max

Units

Fclk

Tsph

Tspl

Tsh

100

0.1

0.7

100

50

1000

KHz

µs

ns

Clock Pulse High Time

Clock Pulse Low Time

Hold Time (Start Cond.)

Setup Time (Start Cond.)

Data Setup Time

Tssu

Tsds

Tsr

Rise Time

1

µs

ns

Fall Time

Tsf

0.3

Setup Time (Stop Cond.)

Bus Free Time

Tss

100

0

Tbuf

Tdh

Tvdo

Data Hold Time

SCL Low to Data Out Valid

600

T_ds

T_sh

T_ss

T_dh

T_bu

SDA

T_sr

T_sph

T_vdo

SCL

T_spi

T_si

Figure 2. I²C Host Port Timing

T_ssu

8

DS278PP4

CS4954 CS4955

TIMING CHARACTERISTICS(Continued)

Parallel Host Port Timing (Figure 27, 28, 29)

Read Cycle Time

Trd

Trpw

Tas

60

30

3

-

ns

Read Pulse Width

Address Setup Time

-

Read Address Hold Time

Read Data Access Time

Read Data Hold Time

Trah

Trda

Trdh

Twr

10

-

40

50

-

10

60

40

8

Write Recovery Time

Write Pulse Width

Twpw

Twds

Twdh

Trec

Twac

-

Write Data Setup Time

Write Data Hold Time

-

3

-

Write-Read/Read-Write Recovery Time

Address from Write Hold Time

Reset Timing (Figure 3)

Reset Pulse Width

50

0

-

Tres

100

ns

RESET*

T_res

Figure 3. Reset Timing

DS278PP4

9

CS4954 CS4955

The CS4954/5 is completely configured and con-

trolled via an 8-bit host interface port or an I C

compatible serial interface. This host port provides

access and control of all CS4954/5 options and fea-

tures, such as closed caption insertion, interrupts,

etc.

2. ADDITIONAL CS4954/5 FEATURES

2

•

Five programmable DAC output combinations,

including YUV and second composite

•

Optional progressive scan @ MPEG2 field rates

Stable color subcarrier for MPEG2 systems

General purpose input and output pins

Individual DAC power-down capability

On-chip color bar generator

In order to lower overall system costs, the

CS4954/5 provides an internal voltage reference

that eliminates the requirement for an external, dis-

crete, three-pin voltage reference.

Supports RS170A and ITU R.BT601 compos-

ite output timing

In ISO MPEG-2 system configurations, the

CS4954/5 can be augmented with a common color-

burst crystal to provide a stable color subcarrier

given an unstable 27 MHz clock input. The use of

the crystal is optional, but the facility to connect

one is provided for MPEG-2 environments in

which the system clock frequency variability is too

wide for accurate color sub-carrier generation.

•

HSYNC and VSYNC output in ITU R.BT656

mode

Teletext encoding selectable on two composite

and S-video signals

Programmable saturation, SCH Phase, hue,

brightness and contrast

4. FUNCTIONAL DESCRIPTION

•

Device power-down capability

In the following subsections, the functions of the

CS4954/5 will be described. The descriptions refer

to the device elements shown in the block diagram

on the cover page.

Super White and Super Black support

3. CS4954 INTRODUCTION

The CS4954/5 is a complete multi-standard digital

video encoder implemented in current CMOS tech-

nology. The device can operate at 5 V as well as at

3.3 V. ITU R.BT601- or ITU R.BT656-compliant

digital video input is converted into NTSC-M,

NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I,

PAL-M, PAL-N, or PAL-N Argentina-compatible

analog video. The CS4954/5 is designed to con-

nect, without glue logic, to MPEG1 and MPEG2

digital video decoders.

4.1. Video Timing Generator

All timing generation is accomplished via a

27 MHz input applied to the CLK pin. The

CS4954/5 can also accept a signal from an optional

color burst crystal on the XTAL_IN &

XTAL_OUT pins. See the section, Color Subcarri-

er Synthesizer, for further details.

The Video Timing Generator is responsible for or-

chestrating most of the other modules in the device.

It operates in harmony with external sync input

timing, or it can provide external sync timing out-

puts. It automatically disables color burst on appro-

priate scan lines and automatically generates

serration and equalization pulses on appropriate

scan lines.

Two 10-bit DAC outputs provide high quality S-

Video analog output while another 10-bit DAC si-

multaneously generates composite analog video. In

addition, there are three more DACs to provide si-

multaneous analog RGB or analog YUV outputs.

The CS4954/5 will accept 8-bit YCbCr or 8-bit

YUV input data.

10

DS278PP4

CS4954 CS4955

The CS4954/5 is designed to function as a video

CLK input (27 MHz). Color burst accuracy and

timing master or video timing slave. In both Master stability are limited by the accuracy of the 27 MHz

and Slave Modes, all timing is sampled and assert-

ed with the rising edge of the CLK pin.

input. If the frequency varies, then the color burst

frequency will also vary accordingly.

In most cases, the CS4954/5 will serve as the video

timing master. HSYNC, VSYNC, and FIELD are

For environments in which the CLK input varies or

jitters unacceptably, a local crystal frequency refer-

configured as outputs in Master Mode. HSYNC or ence can be used on the XTAL_IN and

FIELD can also be defined as a composite blanking

output signal in Master Mode. In Master Mode, the

XTAL_OUT pins. In this instance, the input CLK is

continuously compared with the external crystal ref-

timing of HSYNC, VSYNC, FIELD and Compos- erence input and the internal timing of the CS4954/5

ite Blank (CB) signals is programmable. Exact hor- is automatically adjusted so that the color burst fre-

izontal and vertical display timing is addressed in quency remains within tolerance.

the Operational Description section.

Controls are provided for phase adjustment of the

In Slave Mode, HSYNC and VSYNC are typically burst to permit color adjustment and phase com-

configured as input pins and are used to initialize

independent vertical and horizontal timing genera- CS4954/5 via a 10-bit Hue Control Register

tors upon their respective falling edges. HSYNC (HUE_LSB and H_MSB). Burst amplitude control

and VSYNC timing must conform to the ITU- is also made available to the host via the 8-bit burst

pensation. Chroma hue control is provided by the

R BT.601 specifications.

amplitude register (SC_AMP).

The CS4954/5 also provides a ITU R.BT656 Slave

Mode in which the video input stream contains

EAV and SAV codes. In this case, proper HSYNC

and VSYNC timing are extracted automatically

without any inputs other than the V [7:0]. ITU

R.BT656 input data is sampled with the leading

edge of CLK.

4.4. Chroma Path

The Video Input Formatter delivers 4:2:2 YUV

outputs into separate chroma and luma data paths.

The chroma path will be discussed here.

The chroma output of the Video Input Formatter is

directed to a chroma low-pass 19-tap FIR filter.

The filter bandwidth is selected (or the filter can be

bypassed) via the CONTROL_1 Register. The

passband of the filter is either 650 KHz or 1.3 MHz

and the passband ripple is less than or equal to

0.05 dB. The stopband for the 1.3 MHz selection

begins at 3 MHz with an attenuation of greater than

35 dB. The stopband for the 650 KHz selection be-

gins around 1.1 MHz with an attenuation of greater

than 20 dB.

In addition, it is also possible to output HSYNC

and VSYNC signals during CCIR-656 Slave

Mode.

4.2. Video Input Formatter

The Video Input Formatter translates YCbCr input

data into YUV information, when necessary, and

splits the luma and chroma information for filter-

ing, scaling, and modulation.

The output of the chroma low-pass filter is connect-

ed to the chroma interpolation filter in which up-

sampling from 4:2:2 to 4:4:4 is accomplished.

Following the interpolation filter, the U and V

chroma signals pass through two independent vari-

able gain amplifiers in which the chroma amplitude

4.3. Color Subcarrier Synthesizer

The subcarrier synthesizer is a digital frequency

synthesizer that produces the appropriate subcarri-

er frequency for NTSC or PAL. The CS4954/5

generates the color burst frequency based on the

DS278PP4

11

CS4954 CS4955

can be varied via the U_AMP and V_AMP 8-bit

host addressable registers.

three pixel clocks. This variable delay is useful to

offset different propagation delays of the luma

baseband and modulated chroma signals. This ad-

justable luma delay is available only on the

CVBS_1 output.

The U and V chroma signals are fed to a quadrature

modulator in which they are combined with the

output from the subcarrier synthesizer to produce

the proper modulated chrominance signal.

4.6. RGB Path and Component YUV Path

The chroma then is interpolated by a factor of two

in order to operate the output DACs at twice the

pixel rate. The interpolated filters enable running

the DACs at twice the pixel rate and this helps re-

duce the sinx/x roll-off for higher frequencies and

reduces the complexity of the external analog low

pass filters.

The RGB datapath has the same latency as the luma

and chroma path. Therefore all six simultaneous

analog outputs are synchronized. The 4:2:2 YCbCr

data is first interpolated to 4:4:4 and then interpo-

lated to 27 MHz. The color space conversion is per-

formed at 27 MHz. The coefficients for the color

space conversion conform to the ITU R.BT601

specifications.

4.5. Luma Path

After color space conversion, the amplitude of each

component can be independently adjusted via the

R_AMP, G_AMP, and B_AMP 8-bit host address-

able registers. A synchronization signal can be add-

ed to either one, two or all of the RGB signals. The

synchronization signal conforms to NTSC or PAL

specifications.

Along with the chroma output path, the CS4954/5

Video Input Formatter initiates a parallel luma data

path by directing the luma data to a digital delay

line. The delay line is built as a digital FIFO in

which the depth of the FIFO replicates the clock

period delay associated with the more complex

chroma path. Brightness adjustment is also provid-

ed via the 8-bit BRIGHTNESS_OFFSET Register.

Some applications (e.g., projection TVs) require

analog component YUV signals. The chip provides

a programmable mode that outputs component

YUV data. Sync can be added to the luminance sig-

nal. Independent gain adjustment of the three com-

ponents is provided as well.

Following the luma delay, the data is passed

through an interpolation filter that has a program-

mable bandwidth, followed by a variable gain am-

plifier in which the luma DC values are modifiable

via the Y_AMP Register.

4.7. Digital to Analog Converters

The output of the luma amplifier connects to the

sync insertion block. Sync insertion is accom-

plished by multiplexing, into the luma data path,

the different sync DC values at the appropriate

times. The digital sync generator takes horizontal

sync and vertical sync timing signals and generates

the appropriate composite sync timing (including

vertical equalization and serration pulses), blank-

ing information, and burst flag. The sync edge rates

conform to RS-170A or ITU R.BT601 and ITU

R.BT470 specifications.

The CS4954/5 provides six discrete 27 MHz DACs

for analog video. The default configuration is one

10-bit DAC for S-video chrominance, one 10-bit

DAC for S-Video luminance, one 10-bit DAC for

composite output, and three 10-bit DACs for RGB

outputs. All six DACs are designed for driving ei-

ther low-impedance loads (double terminated

75 Ω) or high-impedance loads (double terminated

300 Ω). There are five different DAC configura-

tions to choose from (see Table 1, below).

It is also possible to delay the luminance signal,

with respect to the chrominance signal, by up to

The DACs can be put into tri-state mode via host-

addressable control register bits. Each of the six

12

DS278PP4

CS4954 CS4955

DAC

Pin #

48

Mode 1

Mode 2

Y

Mode 3

Mode 4

Mode 5

CVBS_2

-

Y

C

Y

CVBS_2

47

C

-

CVBS

R

44

CVBS_1

Cr (V)

Y

CVBS_1

Cr (V)

Y

39

R

G

B

-

R

G

B

G

40

CVBS_2

-

B

43

Cb (U)

Table 1. DAC configuration Modes

DACs has its own associated DAC enable bit. In

the Disable Mode, the 10-bit DACs source (or sink)

zero current.

output current modes are software selectable

through a register bit.

4.10. Host Interface

When running the DACs with a low-impedance

load, a minimum of three DACs must be powered

down. When running the DACs with a high-imped-

ance load, all the DACs can be enabled simulta-

neously.

The CS4954/5 provides a parallel 8-bit data inter-

face for overall configuration and control. The host

interface uses active-low read and write strobes,

along with an active-low address enable signal, to

provide microprocessor-compatible read and write

cycles. Indirect host addressing to the CS4954/5 in-

ternal registers is accomplished via an internal ad-

dress register that is uniquely accessible via bus

write cycles in which the host address enable signal

is asserted.

For lower power standby scenarios, the CS4954/5

also provides power shut-off control for the DACs.

Each DAC has an associated DAC shut-off bit.

4.8. Voltage Reference

The CS4954/5 is equipped with an on-board volt-

age reference generator (1.232 V) that is used by

the DACs. The internal reference voltage is accu-

rate enough to guarantee a maximum of 3% overall

gain error on the analog outputs. However, it is

possible to override the internal reference voltage

by applying an external voltage source to the VREF

pin.

The CS4954/5 also provides an I²C-compatible se-

rial interface for device configuration and control.

This port can operate in standard (100Kb/sec) or

2

fast (400 Kb/sec) modes. When in I C mode, the

parallel data interface pins, PDAT [7:0], can be

used as a general purpose I/O port controlled by the

2

I C interface.

4.11. Closed Caption Services

4.9. Current Reference

The CS4954/5 supports the generation of NTSC

Closed Caption services. Line 21 and Line 284 cap-

tioning can be generated and enabled independent-

ly via a set of control registers. When enabled,

clock run-in, start bit, and data bytes are automati-

cally inserted at the appropriate video lines. A con-

venient interrupt protocol simplifies the software

interface between the host processor and the

CS4954/5.

The DAC output current-per-bit is derived in the

current reference block. The current step is speci-

fied by the size of resistor placed between the ISET

current reference pin and electrical ground.

A 4 kΩ resistor needs to be connected between

ISET pin and GNDA. The DAC output currents are

optimized to either drive a doubly terminated load

of 75 Ω (low impedence mode) or a double termi-

nated load of 300 Ω (high impedence mode). The 2

DS278PP4

13

CS4954 CS4955

See the Programming section of this data sheet for

the individual register bit allocations, bit operation-

al descriptions, and initialization states.

4.12. Teletext Services

The CS4954/5 encodes the most common teletext

formats, such as European Teletext, World Stan-

dard Teletext (PAL and NTSC), and North Ameri-

can Teletext (NABTS).

4.16. Testability

The digital circuits are completely scanned by an

internal scan chain, thus providing close to 100%

fault coverage.

Teletext data can be inserted in any of the TV lines

(blanking lines as well as active lines). In addition

the blanking lines can be individually allocated for

Teletext instantiation.

5. OPERATIONAL DESCRIPTION

5.1. Reset Hierarchy

The input timing for teletext data is user program-

mable. See the section Teletext Services for further

details.

The CS4954/5 is equipped with an active low asyn-

chronous reset input pin, RESET. RESET is used to

initialize the internal registers and the internal state

machines for subsequent default operation. See the

electrical and timing specification section of this

data sheet for specific CS4954/5 device RESET

and power-on signal timing requirements and re-

strictions.

Teletext data can be independently inserted on ei-

ther one or all of the CVBS_1, CVBS_2, or S-video

signals.

4.13. Wide-Screen Signaling Support and

CGMS

Insertion of wide-screen signal encoding for PAL

and NTSC standards is supported and CGMS

(Copy Generation Management System) for NTSC

in Japan. Wide-screen signals are inserted in lines

23 and 336 for PAL, and lines 20 and 283 for

NTSC.

While the RESET pin is held low, the host interface

in the CS4954/5 is disabled and will not respond to

host-initiated bus cycles. All outputs are valid after

a time period following RESET pin low.

A device RESET initializes the CS4954/5 internal

registers to their default values as described by Ta-

ble 9, Control Registers. In the default state, the

CS4954/5 video DACs are disabled and the device

is internally configured to provide blue field video

data to the DACs (any input data present on the

V [7:0] pins is ignored at this time). Otherwise, the

CS4954/5 registers are configured for NTSC-M

ITU R.BT601 output operation. At a minimum, the

DAC Registers (0x04 and 0x05) must be written (to

enable the DACs) and the IN_MODE bit of the

4.14. VBI Encoding

This chip supports the transmission of control sig-

nals in the vertical blanking time interval according

to SMPTE RP 188 recommendations. VBI encoded

data can be independently inserted into either or all

of CVBS_1, CVBS_2 or S-video signals.

4.15. Control Registers

The control and configuration of the CS4954/5 is

accomplished primarily through the control regis- CONTROL_0 Register (0x01) must be set (to en-

ter block. All of the control registers are uniquely

addressable via the internal address register. The

control register bits are initialized during device

RESET.

able ITU R.BT601 data input on V [7:0]) for the

CS4954/5 to become operational after RESET.

14

DS278PP4

CS4954 CS4955

NTSC 27MHz Clock Count 1682 1683 1684 1685 1686 • • • 1716

PAL 27MHz Clock Count 1702 1703 1704 1705 1706 • • • 1728

1

2

3

• • • 128 129 • • • 244 245 246 247 248

• • • 128 129 • • • 264 265 266 267 268

CLK

HSYNC (input)

V[7:0]

Y

Cr

Y

Cb

Y

Cr

Y

(SYNC_DLY=0)

active pixel

#720

horizontal blanking

active pixel active pixel

#1 #2

• • •

V[7:0] Cb

Y

Cr

Y

Cb

Y

Cr

(SYNC_DLY=1)

active pixel active pixel

#719 #720

active pixel active pixel

#1 #2

Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing

SYNC_DLY = 0. When SYNC_DLY = 1, it expects

the first active pixel data on clock cycle 246 (NTSC).

5.2. Video Timing

5.2.1. Slave Mode Input Interface

5.2.2. Master Mode Input Interface

In Slave Mode, the CS4954/5 receives signals on

VSYNC and HSYNC as inputs. Slave Mode is the

The CS4954/5 defaults to Slave Mode following

default following RESET and is changed to Master RESET high but can be switched into Master Mode

Mode via a control register bit (CONTROL_0 [4]). via the MSTR bit in the CONTROL_0 Register

The CS4954/5 is limited to ITU R.BT601 horizon- (0x00). In Master Mode, the CS4954/5 uses the

tal and vertical input timing. All clocking in the VSYNC, HSYNC and FIELD device pins as out-

CS4954/5 is generated from the CLK pin. In Slave puts to schedule the proper external delivery of dig-

Mode, the Sync Generator uses externally provided ital video into the V [7:0] pins. Figure 5 illustrates

horizontal and vertical sync signals to synchronize horizontal timing for the CCIR601 input in Master

the internal timing of the CS4954/5. Video data that Mode.

is sent to the CS4954/5 must be synchronized to the

The timing of the HSYNC output is selectable in

horizontal and vertical sync signals. Figure 4 illus-

the PROG_HS Registers (0x0D, 0x0E). HSYNC

trates horizontal timing for ITU R.BT601 input in

can be delayed by one full line cycle. The timing of

Slave Mode. Note that the CS4954/5 expects to re-

the VSYNC output is also selectable in the

ceive the first active pixel data on clock cycle 245

(NTSC) when CONTROL_2 Register (0x02) bit

NTSC 27MHz Clock Count 1682 1683 1684 1685 1686 • • • 1716

PAL 27MHz Clock Count 1702 1703 1704 1705 1706 • • • 1728

1

2

3

• • • 128 129 • • • 244 245 246 247 248

• • • 128 129 • • • 264 265 266 267 268

CLK

HSYNC (output)

CB (output)

V[7:0]

Y

Cr

Y

Cb

Y

Cr

Y

horizontal blanking

active pixel

#720

active pixel active pixel

#1 #2

• • •

Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing

DS278PP4

15

CS4954 CS4955

PROG_VS Register (0x0D). VSYNC can be de- (falling) edge of HSYNC if the PROG_HS Regis-

layed by thirteen lines or advanced by eighteen lines. ters are set to default values.

5.2.3. Vertical Timing

5.2.5. NTSC Interlaced

The CS4954/5 can be configured to operate in any

The CS4954/5 supports NTSC-M, NTSC-J and

of four different timing modes: PAL, which is 625 PAL-M modes where there are 525 total lines per

vertical lines, 25 frames per second interlaced; frame and two fixed 262.5-line fields per frame and

NTSC, which is 525 vertical lines, 30 frames per 30 total frames occurring per second. NTSC inter-

second interlaced; and either PAL or NTSC in Pro- laced vertical timing is illustrated in Figure 7. Each

gressive Scan, in which the display is non-inter- field consists of one line for closed caption, 240 ac-

laced. These modes are selected in the

CONTROL_0 Register (0x00).

tive lines of video, plus 21.5 lines of blanking.

VSYNC field one transitions low at the beginning

The CS4954/5 conforms to standard digital decom- of line four and will remain low for three lines or

pression dimensions and does not process digital 2574 pixel cycles (858 × 3). The CS4954/5 exclu-

input data for the active analog video half lines as

they are typically in the over/underscan region of

sively reserves line 21 of field one for closed cap-

tion insertion. Digital video input is expected to be

televisions. 240 active lines total per field are pro- delivered to the CS4954/5 V [7:0] pins for 240

cessed for NTSC, and 288 active lines total per lines beginning on active video lines 22 and con-

field are processed for PAL. Frame vertical dimen- tinuing through line 261. VSYNC field two transi-

sions are 480 lines for NTSC and 576 lines for tions low in the middle of line 266 and stays low for

PAL. Table 2 specifies active line numbers for both

NTSC and PAL. Refer to Figure 6 for HSYNC,

VSYNC and FIELD signal timing.

three line-times and transitions high in the middle

of line 269. The CS4954/5 exclusively reserves line

284 of field two for closed caption insertion. Video

input on the V [7:0] pins is expected between lines

285 through line 525.

Mode

Field

Active Lines

NTSC

PAL

1, 3;

2, 4

22-261;

285-524

5.2.6. PAL Interlaced

1, 3, 5, 7;

2, 4, 6, 8

23-310;

336-623

The CS4954/5 supports PAL modes B, D, G, H, I,

N, and Combination N, in which there are 625 total

lines per frame, two fixed 312.5 line fields per

frame, and 25 total frames per second. Figure 8 il-

lustrates PAL interlaced vertical timing. Each field

consists of 287 active lines of video plus 25.5 lines

of blanking.

NTSC Progressive-Scan

PAL Progressive-Scan

NA

22-261

23-310

Table 2. Vertical Timing

5.2.4. Horizontal Timing

HSYNC is used to synchronize the horizontal-in-

put-to-output timing in order to provide proper hor-

izontal alignment. HSYNC defaults to an input pin

following RESET but switches to an output in Mas-

ter Mode (CONTROL_0 [4] = 1). Horizontal tim-

ing is referenced to HSYNC transitioning low. For

active video lines, digital video input is to be ap-

plied to the V [7:0] inputs for 244 (NTSC) or for

264 (PAL) CLK periods following the leading

VSYNC will transition low to begin field one and

will remain low for 2.5 lines or 2160 pixel cycles

(864 × 2.5). Digital video input is expected to be

delivered to the CS4954/5 V [7:0] pins for 287

lines beginning on active video line 24 and continu-

ing through line 310.

Field two begins with VSYNC transitioning low

after 312.5 lines from the beginning of field one.

16

DS278PP4

CS4954 CS4955

NTSC Vertical Timing (odd field)

Line

3

4

5

6

7

8

9

10

HSYNC

VSYNC

FIELD

NTSC Vertical Timing (even field)

264 265 266

Line

267

268

269

270

271

HSYNC

VSYNC

FIELD

PAL Vertical Timing (odd field)

265

Line

1

2

3

4

5

6

7

HSYNC

VSYNC

FIELD

PAL Vertical Timing (even field)

311 312 313

Line

314

315

316

317

318

HSYNC

VSYNC

FIELD

Figure 6. Vertical Timing

VSYNC stays low for 2.5 line-times and transitions commonly support progressive scan by repetitively

high with the beginning of line 315. Video input on displaying a 262 line field (524/525 lines for

the V [7:0] pins is expected between line 336

through line 622.

NTSC). The common method is flawed: over time,

the output display rate will overrun a system-clock-

locked MPEG-2 decompressor and display a field

twice every 8.75 seconds.

5.2.7. Progressive Scan

The CS4954/5 supports a progessive scan mode in

which the video output is non-interlaced. This is

accomplished by displaying only the odd video

field for NTSC or PAL. To preserve precise

MPEG-2 frame rates of 30 and 25 per second, the

CS4954/5 displays the same odd field repetitively

5.2.8. NTSC Progressive Scan

VSYNC will transition low at line four to begin

field one and will remain low for three lines or

2574 pixel cycles (858 × 3). NTSC interlaced tim-

ing is illustrated in Figure 9. In this mode, the

but alternately varies the field times. This mode is CS4954/5 expects digital video input at the V [7:0]

in contrast to other digital video encoders, which

DS278PP4

17

CS4954 CS4955

Analog

Field 1

VSYNC Drops

523

524

525

1

2

3

4

5

6

7

8

9

10

22

Analog

Field 2

261

262 263

264

265

266

267

268

269

270

271

272

284

285

Analog

Field 3

VSYNC Drops

1

2

3

4

5

6

7

8

9

10

22

523

524

525

Analog

Field 4

261

262 263

264

265

266

267

268

269

270

271

272

284

285

Burst begins with positive half-cycle

Burst begins with negative half-cycle

Figure 7. NTSC Video Interlaced Timing

pins for 240 lines beginning on active video line 22

and continuing through line 261.

high during the middle of line 315. Video input on

the V [7:0] pins is expected between line 335

through line 622. Field two is 313 lines; field one is

312 lines.

Field two begins with VSYNC transitioning low at

line 266. VSYNC stays low for 3 line cycles and

transitions high during the end of line 268. Video

input on the V [7:0] pins is expected between line

284 and line 522. Field two is 263 lines; field one

is 262 lines.

5.3. ITU-R.BT656

The CS4954/5 supports an additional ITU-

R.BT656 slave mode feature that is selectable

through the ITU-R.BT656 bit of the CONTROL_0

Register. The ITU-R.BT656 slave feature is unique

because the horizontal and vertical timing and dig-

ital video are combined into a single 8-bit 27 MHz

input. With ITU-R.BT656 there are no horizontal

and vertical input or output strobes, only 8-bit

27 MHz active CbYCrY data, with start- and end-

of-video codes implemented using reserved 00 and

FF code sequences within the video feed. As with

all modes, V [7:0] are sampled with the rising edge

of CLK. The CS4954/5 expects the digital ITU-

R.BT656 stream to be error-free. The FIELD out-

5.2.9. PAL Progressive Scan

VSYNC will transition low at the beginning of the

odd field and will remain low for 2.5 lines or 2160

pixel cycles (864 × 2.5). PAL non-interlaced tim-

ing is illustrated in Figure 10. In this mode, the

CS4954/5 expects digital video input on the V [7:0]

pins for 288 lines, beginning on active video line 23

and continuing through line 309.

The second begins with VSYNC transitioning low

after 312 lines from the beginning of the first field.

VSYNC stays low for 2.5 line-times and transitions

18

DS278PP4

CS4954 CS4955

VSYNC Drops

Analog

Field 1

620

621

622

623

624

625

1

2

3

4

5

6

318 319

6

7

23

24

Analog

Field 2

308

309

310

311

312

313

314

315

316

317

320

336

337

Analog

Field 3

620

621

622

623

624

625

1

2

3

4

5

7

23

24

Analog

Field 4

308

309

310

311

312

313

314

315

316

317

318 319

320

336

337

Analog

Field 5

620

621

622

623

624

625

1

2

3

4

5

6

7

23

24

Analog

Field 6

308

309

310

311

312

313

314

315

316

317

318 319

320

336

337

Analog

Field 7

620

621

622

623

624

625

1

2

3

4

5

6

7

23

24

Analog

Field 8

308

309

310

311

312

313

314

315

316

317

318 319

320

336

337

Burst Phase = 135 degrees relative to U

Burst Phase = 225 degrees relative to U

Figure 8. PAL Video Interlaced Timing

put toggles as with non ITU-R.BT656 input. ITU- output these timing signals for other purposes. By

R.BT656 input timing is illustrated in Figure 11.

setting the 656_SYNC_OUT register bit in

CONTROL_6 register, HSYNC and VSYNC are

output,so that other devices in the system can syn-

chronize to these timing signals.

As mentioned above, there are no horizontal and

vertical timing signals necessary in ITU-R.BT656

mode. However in some cases it is advantageous to

DS278PP4

19

CS4954 CS4955

Start of

VSYNC

Field 1

262

261

263

262

1

2

3

4

5

6

7

8

9

10

22

Field 2

Field 3

Field 4

3

4

Start of

VSYNC

262

261

263

262

1

2

3

4

5

6

7

8

9

10

22

4

Burst begins with positive half-cycle

Burst phase = reference phase = 180⁰relative to B-Y

Burst begins with negative half-cycle

Burst phase = reference phase = 180⁰relative to B-Y

Figure 9. NTSC Video Non-Interlaced Progressive Scan Timing

VSYNC Drops

Analog

Field 1

309

310

311

310

312

311

313

312

1

2

3

4

5

6

7

23

24

Analog

Field 2

308

309

1

Analog

Field 3

309

310

311

310

312

311

313

312

1

2

3

4

5

6

7

23

24

Analog

Field 4

308

309

1

Burst Phase = 135 degrees relative to U

Burst Phase = 225 degrees relative to U

Figure 10. PAL Video Non-Interlaced Progressive Scan Timing

20

DS278PP4

CS4954 CS4955

Composite

Video

ITU R.BT656

DATA

V[7:0]

Y

Cr

Y

FF 00 00 XY 80 10 80 10

80 10 80 10 80 10

Ancilliary Data

80 10 80 10 FF 00 00 XY Cb

SAV Code

Y

Cr Cb Y Cr

EAV Code

268 Clocks (NTSC)

280 Clocks (PAL)

4 Clocks

1440 Clocks

Active Video

Horizontal Blanking

Figure 11. CCIR656 Input Mode Timing

Output formats are configured by writing control

registers with the values shown in Table 3.

5.4. Digital Video Input Modes

The CS4954/5 provides two different digital video

input modes that are selectable through the

IN_MODE bit in the CONTROL_0 Register.

5.6. Subcarrier Generation

The CS4954/5 automatically synthesizes NTSC

and PAL color subcarrier clocks using the CLK fre-

In Mode 0 and upon RESET, the CS4954/5 de-

faults to output a solid color (one of a possible of

256 colors). The background color is selected by

writing the BKG_COLOR Register (0x08). The

colorspace of the register is RGB 3:3:2 and is unaf-

fected by gamma correction. The default color fol-

lowing RESET is blue.

quency

and

four

control

registers

(SC_SYNTH0/1/2/3). The NTSC subcarrier syn-

thesizer is reset every four fields (every eight fields

for PAL).

The SC_SYNTH0/1/2/3 registers used together

provide a 32-bit value that defaults to NTSC

(43E0F83Eh) following RESET. Table 4 shows the

32-bit value required for each of the different

broadcast formats.

In Mode 1 the CS4954/5 supports a single 8-bit

27 MHz CbYCrY source as input on the V [7:0]

pins. Input video timing can be ITU-R.BT601 mas-

ter or slave and ITU-R.BT656.

System

Fsubcarrier

Value (hex)

5.5. Multi-standard Output Format

Modes

NTSC-M, NTSC-J

3.5795455 MHz 43E0F83E

PAL-B, D, G, H, I, N 4.43361875 MHz 54131596

The CS4954/5 supports a wide range of output for-

mats compatible with worldwide broadcast stan-

dards. These formats include NTSC-M, NTSC-J,

PAL-B/D/G/H/I, PAL-M, PAL-N, and PAL Com-

bination N (PAL-Nc) which is the broadcast stan-

dard used in Argentina. After RESET, the CS4954/5

defaults to NTSC-M operation with ITU R.BT 601

analog timing. NTSC-J can also be supported in the

Japanese format by turning off the 7.5 IRE pedestal

through the PED bit in the CONTROL_1 Register

(0x01).

PAL-N (Argentina)

PAL-M

3.582056 MHz 43ED288D

3.579611 MHz 43CDDFC7

Table 3.

5.7. Subcarrier Compensation

Since the subcarrier is synthesized from CLK the

subcarrier frequency error will track the clock fre-

quency error. If the input clock has a tolerance of

200 ppm then the resulting subcarrier will also

have a tolerance of 200 ppm. Per the NTSC speci-

fication, the final subcarrier tolerance is ±10 Hz

DS278PP4

21

CS4954 CS4955

which is approximately 3 ppm. Care must be taken

in selecting a suitable clock source.

data to be inserted is also written into the four

Closed Caption Data registers. The CS4954/5,

when enabled, automatically generates the seven

cycles of clock run-in (32 times the line rate), start

bit insertion (001), and finally insertion of the two

data bytes per line. Data low at the video outputs

corresponds to 0 IRE and data high corresponds to

50 IRE.

In MPEG-2 system environments the clock is actu-

ally recovered from the data stream. In these cases

the recovered clock can be 27 MHz ±50 ppm or

±1350 Hz. It varies per television, but in many cas-

es given an MPEG-2 system clock of 27 MHz,

±1350 Hz, the resultant color subcarrier produced

will be outside of the television’s ability to com- There are two independent 8-bit registers per line

pensate and the chrominance information will not

be displayed (resulting in a black-and-white picture

only).

(CC_21_1 & CC_21_2 for line 21 and CC_284_1

& CC_284_2 for line 284). Interrupts are also pro-

vided to simplify the handshake between the driver

software and the device. Typically the host would

write all 4 bytes to be inserted into the registers and

then enable closed caption insertion and interrupts.

As the closed caption interrupts occur the host soft-

ware would respond by writing the next two bytes

to be inserted to the correct control registers and

then clear the interrupt and wait for the next field.

The CS4954/5 is designed to provide automatic

compensation for an excessively inaccurate

MPEG-2 system clock. Sub-carrier compensation

is enabled through the XTAL bit of the

CONTROL_2 Register. When enabled the

CS4954/5 will utilize a common quartz color burst

crystal (3.579545 MHz ± 50 ppm for NTSC) at-

tached to the XTAL_IN and XTAL_OUT pins to

automatically compare and compensate the color

subcarrier synthesis process.

5.9. Programmable H-sync and V-sync

It is possible in master mode to change the H-sync

and V-sync times based on register settings. Pro-

grammable H-sync and V-sync timings are helpful

in several digital video systems, where latencies of

the control signals are present. The user can then

program H-sync and V-sync timing according to

their system requirements. The default values are

244, and 264 for NTSC and PAL respectively.

5.8. Closed Caption Insertion

The CS4954/5 is capable of NTSC Closed Caption

insertion on lines 21 and 284 independently.

Closed captioning is enabled for either one or both

lines via the CC_EN [1:0] Register bits and the

NTSC-M NTSC-J

PAL-N

ITU

NTSC-M

PAL-

Comb.

Address

0×00

0×01

0×04

0×05

0×10

0×11

Register

R.BT601 R.BT601 RS170A B,D,G,H,I PAL-M

PAL-N

A1h

30h

07h

78h

15h

96h

15h

13h

54h

(Argent)

CONTROL_0

CONTROL_1

CONTROL_4

CONTROL_5

SC_AMP

01h

12h

07h

78h

1Ch

3Eh

F8h

E0h

43h

01h

10h

07h

78h

1Ch

3Eh

F8h

E0h

43h

21h

16h

07h

78h

1Ch

3Eh

F8h

E0h

43h

41h

30h

07h

78h

15h

96h

15h

13h

54h

61h

12h

07h

78h

15h

C7h

DFh

CDh

43h

81h

30h

07h

78h

15h

8Ch

28h

EDh

43h

SC_SYNTH0

SC_SYNTH1

SC_SYNTH2

SC_SYNTH3

0×12

0×13

0×14

Table 4. Multi-standard Format Register Configurations

22

DS278PP4

CS4954 CS4955

H-sync can be delayed by a full line, in 74 nsec in-

tervals.

5.11. Teletext Support

This chip supports several teletext standards, like

European teletext, NABTS (North American tele-

text), and WST (World Standard Teletext) for

NTSC and PAL.

V-sync can be shifted in both directions in time.

The default values are 18 and 23 for NTSC and

PAL respectively. Since the V-sync register is 5

bits wide (Sync Register 0), the V-sync pulse can

be shifted by 31 lines in total.

All these teletext standards are defined in the ITU-

R BT.653-2 document. The European teletext is

defined as “teletext system B” for 625/50 Hz TV

V-sync can preceed by a maximum of 18 lines

(NTSC) or 23 lines (PAL) respectively from its de- systems. NABTS teletext is defined as “teletext

fault location, and V-sync can follow by a maxi- system C” for 525/60 Hz TV systems. WST for

mum of 13 lines (NTSC) or 8 lines (PAL) from its PAL is defined as “teletext system D” for

default location.

624/50 Hz TV systems and WST for NTSC is de-

fined as “teletext system D” for 525/60 Hz TV

systems.

5.10. Wide Screen Signaling (WSS) and

CGMS

This chip provides independant teletext encoding

into composite 1, composite 2 and s-video signals.

The teletext encoding into these various signals is

software programmable.

Wide screen signaling support is provided for

NTSC and for PAL standards. Wide screen signal-

ing is currently used in most countries with 625 line

systems as well as in Japan for EDTV-II applica-

tions. For complete description of WSS standard,

please refer to ITU-R BT.1119 (625 line system)

and to EIAJ CPX1204 for the Japanese 525 line

system.

In teletext pulsation mode, (TTX_WINDOW=0),

register 0×31 bit 3, the pin TTXDAT receives a

teletext bitstream sampled at the 27 Mhz clock. At

each rising edge of the TTXRQ output signal a sin-

gle teletext bit has to be provided after a program-

mable input delay at the TTXDAT input pin.

The wide screen signal is transferred in a blanking

line of each video field (NTSC: lines 20 and 283,

PAL: lines 23 and 336). Wide screen signaling is

enabled by setting WW_23 to “1”. Some countries

with PAL standard don’t use line 336 for wide

screen signaling (they use only line 23), therefore

we provide another enable bit (WSS_22) for that

particular line.

Phase variant interpolation is achieved on this bit-

stream in the internal teletext encoder, providing

sufficient small phase jitter on the ouput text lines.

TTXRQ provides a fully programmable request

signal to the teletext source, indicating the insertion

period of the bitstream at indepenantly selectable

lines for both TV fields. The internal insertion win-

dow for text is set to either 360, 296 or 288 teletext

bits, depending on the selected teletext standard.

The clock run-in is included in this window.

There are 3 registers dedicated to contain the trans-

mitted WSS bits (WSS_REG_0, WSS_REG_1,

WSS_REG_2). The data insertion into the appro-

priate lines are performed automatically by this de-

vice. The run-in and start code bits do not have to

be loaded into this device, it automatically inserts

the correct code at the beginning of transfer.

Teletext in enabled by setting the TTX_EN bit to

“1”. The TTX_WST bit in conjunction with the

TV_FORMAT register select one of the 4 possible

teletext encoding possibilities.

The teletext timing is shown in the Figure 12.

TTXHS and TTXHD are user programmable and

DS278PP4

23

CS4954 CS4955

therefore allow the user to have full control over to (5.6427875 Mbit/sec) (WST PAL) or 288 TTX bits

when sending teletext data to this device.

(5.727272 Mbit/sec) (NABTS) or 296 TTX bits

(5.727272 Mbit/sec) (WST NTSC) respectively.

The time t is the time needed to interpolate tele-

FD

text input data and inserting it into the CVBS and Using the appropriate programming, all suitable

Y output signals, such that it appears between lines of the odd field (TTXOVS through TTX-

= 9.8 µs and t = 12 µs after the leading OVE) plus all suitable lines of the even field

t

TTX

edge of the horizontal synchronization pulse. t

(TTXEVS through TTXEVE) can be used for tele-

text insertion. In addition it is possible to selec-

tively disable the teletext insertion on single lines.

This can be programmed by setting the

FD

changes with the TV standard and the selected

teletext standard. Please refer to ITU-R BT.653-2

for more detailed information.

TTX_LINE_DIS1,

TTX_LINE_DIS3 registers appropriately.

TTX_LINE_DIS2

and

The time t is the pipeline delay time introduced

by the source that is gated by TTXRQ in order to

PD

deliver teletext data. This delay is programmable Note that the TTXDAT signal must be synchro-

through the register TTXHD. For every active

HIGH transition at output pin TTXRQ, a new tele-

text bit must be provided by the source. The time

between the beginning of the first TTXRQ pulse

and the leading edge of H-sync is programmable

through the TTXHS register.

nized with the 27 Mhz clock. The pulse width of

the TTXRQ signal varies between three and four

27 Mhz clock cycles. The variation is necessary in

order to maintain the strict timing requirements of

the teletext standard.

Table 5 shows how to program the TTXHS register

for teletext instantiation into the analog signals for

the various supported TV formats. TTXHS is the

time between the leading edge of the HSYNC sig-

nal and the rising edge of the first TTXRQ signal

and consists of multiples of 27 Mhz clock cycles

Since the beginning of the pulses representing the

TTXRQ signal and the delay between the rising

edge of TTXRQ and valid teletext input data are

fully programmable, the TTXDAT data is always

inserted at the correct position after the leading

edge of the outgoing horizontal synchronization

pulse.

Note that with increasing values of TTXHS the

time t

increases as well. The time t accounts

TTX

FD

The time t

is the internally used insertion

TTXWin

for the internal pipeline delay due to processing,

synchronization and instantiation of the teletext

data. The time t is dependant on the TTXHD

window for TTX data; it has a constant length

depending on the selected teletext standard which

allows insertion of 360 TTX bits (6.9375

Mbit/sec) (European teletext) or 296 TTX bits

PD

register.

CVBS/Y

t

TTXWin

t

TTX

TTXWin

TTX

TTXRQ

textbit #:

1

2

3

4

5

textbit #:

1

2

3

4

5

TTXDAT

t

FD

PD

FD

PD

Figure 12. Teletext Timing (Pulsation Mode)

Figure 13. Teletext Timing (Window Mode)

24

DS278PP4

CS4954 CS4955

Note that the teletext databits are shaped according CONTROL_1 Register. The color bar generator

to the ITU R.BT653-2 specifications.

works in master or Slave Mode and has no effect on

the video input/output timing. If the CS4954/5 is

configured for Slave Mode color bars, proper video

timing must be present on the HSYNC and

VSYNC pins for the color bars to be displayed.

Given proper Slave Mode input timing or Master

Mode, the color bar generator will override the vid-

eo input pixel data.

If register 0×31 bit 3 is set, (TTX_WINDOW=1)

the teletext is in windows mode, the request pulses

become a window where the bit provided on the

TTXDAT pin are valid (see Figure 13).

Alternately to the pulsation mode (where the num-

ber of request pulses are determined by the teletext

standard chosen), the length of the window must be

programmed by the user independently of the tele-

text standard used. The length of the window is

programmed through register 0×29 TTXHS (start

of window) and register 0×2A (TTXHD) and 0×31

(end of window). The end-of-window register is a

11 bit value.

The output of the color bar generator is instantiated

after the chroma interpolation filter and before the

luma delay line. The generated color bar numbers

are for 100% amplitude, 100% saturation NTSC

EIA color bars or 100% amplitude, 100% satura-

tion PAL EBU color bars. For PAL color bars, the

CS4954/5 generates NTSC color bar values, which

are very close to standard PAL values. The exact

luma and chroma values are listed in Table 6. .

In teletext window mode, the TTXHS value can be

selected using the values in Table 5. Although

these values may need to be adjusted to match your

system delay, use the following equation to com-

pute the TTXHD value:

Color

Cb

0

Cr

0

Y

White

Yellow

Cyan

+ 167

+ 156

+ 138

+ 127

+ 110

+ 99

- 84

+ 28

- 56

+ 56

- 28

+ 84

0

+ 14

- 84

- 70

+ 70

+ 84

- 14

0

TTXHS + 1402 = TTXHD (for Europe)

TTXHS + 1151 = TTXHD (for WST)

TTXHS + 1122 = TTXHD (for NABTS)

TTXHS

Green

Magenta

Red

Blue

+ 81

Teletext

standard

(register

value)

Black

+ 70

t_TTX

TV standard

NTSC-M

PAL-B

Table 6. Internal Color Bar Values (8-bit values, Cb/Cr

are in twos complement format)

NABTS

WST-NTSC

Europe TTX

WST-PAL

NABTS

161

142

204

163

161

142

204

163

204

163

10.5 µs

9.8 µs

5.13. VBI encoding

12.0 µs

10.5 µs

9.8 µs

PAL-B

VBI (Vertical Blanking Interval) encoding is per-

formed according to SMPTE RP 188 recommenda-

tions. In NTSC mode lines 10 - 20 and lines 272 -

283 are used for the transmission of ancillary data.

In PAL mode lines 6 - 22 and lines 318 -335 are

used. The VBI encoding mode can be set through

the CONTROL_3 register.

PAL-M

WST-NTSC

PAL-N (non Arg.) Europe TTX

12.0 µs

10.5 µs

12.0 µs

10.5 µs

PAL-N (non Arg.)

PAL-N (Arg.)

WST-PAL

Europe TTX

WST-PAL

PAL-N (Arg.)

Table 5. Teletext timing parameters

All digital input data is passed through the chip

when this mode is enabled. It is therefore the re-

sponsibility of the user to ensure appropriate ampli-

5.12. Color Bar Generator

The CS4954/5 is equipped with a color bar genera-

tor that is enabled through the CBAR bit of the

DS278PP4

25

CS4954 CS4955

tude levels. Table 7 shows the relationship of the

digital input signal and the analog output voltage.

signal which is presented on the INT output pin. If

an interrupt has occurred, it cannot be eliminated

with a disable, it must be cleared.

Digital Input

0×38

Analog Output Voltage

286 mV

5.16. General Purpose I/O Port

0×3B

300 mV

The CS4954/5 has a GPIO port and register that is

0×C4

1000 mV

2

available when the device is configured for I C

Table 7. VBI Encoding Signal Amplitudes

2

host interface operation. In I C host interface

mode, the PDAT [7:0] pins are unused by the host

interface and they can operate as input or output

pins for the GPIO_DATA_REG Register (0×0A).

Each LSB corresponds to a step of 5 mV in the out-

put voltage.

5.14. Super White/Super Black support

The

CS4954/5

also

contains

the

GPIO_CTRL_REG Register (0×09) which is used

to configure the GPIO pins for input or output op-

eration.

The ITU-R BT.601 recommendation limits the al-

lowed range for the digital video data between

0×10 - 0×EB for luma and between 0×10 - 0×F0 for

the chrominance values. This chip will clip any

digital input value which is out of this range to con-

form to the ITU-R BT.601 specifications.

The GPIO port PDAT [7:0] pins are configured for

input operation when the corresponding

GPIO_CTRL_REG [7:0] bits are set to 0. In GPIO

input mode, the CS4954/5 will latch the data on the

PDAT [7:0] pins into the corresponding bit loca-

tions of GPIO_DATA_REG when it detects regis-

However for some applications it is useful to allow

a wider input range. By setting the CLIP_OFF bit

(CONTROL_6 register) the allowed input range is

extended between 0×01 - 0×FE for both luma and

chrominance values.

2

ter address 0×0A through the I C interface. A

detection of address 0×0A can happen in two ways.

The first and most common way this will happen is

when address 0×0A is written to the CS4954/5 via

Note that 0×00 and 0×FF values are never allowed,

since they are reserved for synchronization infor-

mation.

2

its I C interface. The second method for detecting

address 0×0A is implemented by accessing register

2

address 0×09 through I C. In I C host interface op-

eration, the CS4954/5 register address pointer will

auto-increment to address 0×0A after an address

0×09 access.

5.15. Interrupts

In order to better support precise video mode

switches and to establish a software/hardware

handshake with the closed caption insertion block

the CS4954/5 is equipped with an interrupt pin The GPIO port PDAT [7:0] pins are configured for

named INT. The INT pin is active high. There are output operation when the corresponding

three interrupt sources: VSYNC, Line 21, and Line GPIO_CTRL_REG [7:0] bits are set. In GPIO out-

284. Each interrupt can be individually disabled put mode, the CS4954/5 will output the data in

with the INT_EN Register. Each interrupt is also GPIO_DATA_REG [7:0] bit locations onto the

cleared via writing a one to the corresponding

INT_CLR Register bits. The three individual inter-

rupts are OR-ed together to generate an interrupt

corresponding PDAT [7:0] pins when it detects a

register address 0×0A through the I C interface.

2

26

DS278PP4

CS4954 CS4955

6. FILTER RESPONSES

1.3 Mhz. filter passband response

1.3 Mhz. filter frequency response

0

-10

-20

-30

-40

-50

-60

-70

0

-0.1

-0.2

-0.3

-0.4

-0.5

0

1

2

3

4

5

6

0

2

4

6

8

10

12

x 10

6

5

x 10

frequency (Hz)

Figure 14. 1.3 Mhz Chrominance low-pass filter trans-

fer characteristic

Figure 15. 1.3 Mhz Chrominance low-pass filter trans-

fer characterstic (passband)

650 Khz. filter passband response

0

650 Khz. filter frequency response

0

-0.5

-1

-5

-10

-15

-20

-25

-30

-1.5

-2

-2.5

-3

0

2

4

6

8

10

12

0

1

2

3

4

5

6

5

6

x 10

Figure 16. 650 kHz Chrominance low-pass filter trans-

fer characteristic

Figure 17. 650 kHz Chrominance low-pass filter trans-

fer characteristic (passband)

DS278PP4

27

CS4954 CS4955

Luma Output Interpolation Filter Response at 27MHz full scale

Chroma Output Interpolator Pass band

0

-5

1

0.8

0.6

0.4

0.2

0

-10

-15

-20

-25

-30

-35

-40

-0.2

-0.4

-0.6

-0.8

-1

0

2

4

6

8

10

12

14

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Frequency (MHz)

Figure 18. Chrominance output interpolation filter

transfer characteristic (passband)

Figure 19. Luminance interpolation filter transfer char-

acteristic

RGB datapath filter for rgb_bw = 0 full scale

0

Luma Output Interpolation Filter Response at 27 MHz (-3 dB)

0.5

-5

-10

-15

-20

-25

-30

-35

-40

0

-0.5

-1

-1.5

-2

-2.5

-3

-3.5

0

2

4

6

8

10

12

0

1

2

3

4

5

6

7

8

Frequency (MHz)

Figure 20. Luminance interpolation filter transfer char-

acterstic (passband)

Figure 21. Chrominance interpolation filter transfer

characteristic for RGB datapath

28

DS278PP4

CS4954 CS4955

RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth)

RGB datapath filter when rgb_bw = 1 (Reduced Bandwidth) (-3 dB)

1

0.5

0

-5

-10

-15

-20

-25

-30

-35

-40

-45

-0.5

-1

-1.5

-2

-2.5

-3

0

2

4

6

8

10

12

0

2

4

6

8

10

12

Frequency (MHz)

Figure 22. Chroma Interpolator for RGB Datapath

when rgb_bw=1 (Reduced Bandwidth)

Figure 23. Chroma Interpolator for RGB Datapath

when rgb_bw=1 (Reduced Bandwidth)

RGB datapath filter for rgb_bw = 0 (-3 dB)

1

Chroma Output Interpolator Full Scale

0

0.5

0

-5

-10

-15

-20

-25

-30

-35

-40

-0.5

-1

-1.5

-2

-2.5

-3

0

2

4

6

8

10

12

0

5

10

15

20

25

Frequency (MHz)

Figure 24. Chroma Interpolator for RGB Datapath

when rgb_bw=0 -3 dB

Figure 25. Chroma Interpolator for RGB Datapath

when rgb_bw=0 (Full Scale)

DS278PP4

29

CS4954 CS4955

digital amplifiers. The DAC output levels are de-

fined by the following operations:

7. ANALOG

7.1. Analog Timing

VREF/RISET = IREF

All CS4954/5 analog timing and sequencing is de-

rived from 27 MHz clock input. The analog outputs

are controlled internally by the video timing genera-

tor in conjunction with master and slave timing. The

video output signals perform accordingly for NTSC

and PAL specifications.

(e.g., 1.232 V/4K Ω = 308 µA)

CVBS/Y/C/R/G/B outputs in low impedance mode:

VOUT (max) = IREF*(16/145)*1023*37.5 Ω = 1.304V

CVBS/Y/C/R/G/B outputs in high impedance mode:

VOUT (max) = IREF*(4/145)*1023*150Ω = 1.304 V

Being that the CS4954/5 is almost entirely a digital

circuit, great care has been taken to guarantee ana-

log timing and slew rate performance as specified

in the NTSC and PAL analog specifications. Refer-

ence the Analog Parameters section of this data

sheet for exact performance parameters.

7.4. DACs

The CS4954/5 is equipped with six independent,

video-grade, current-output, digital-to-analog con-

verters (DACs). They are 10-bit DACs operating at

a 27 MHz two-times-oversampling rate. All six

DACs are disabled and default to a low power

mode upon RESET. Each DAC can be individually

powered down and disabled. The output-current-

per-bit of all six DACs is determined by the size of

the resistor connected between the ISET pin and

electrical ground.

7.2. VREF

The CS4954/5 can operate with or without the aid

of an external voltage reference. The CS4954/5 is

designed with an internal voltage reference genera-

tor that provides a VREFOUT signal at the VREF

pin. The internal voltage reference is utilized by not

making a connection to the VREF pin. The VREF

pin can also be connected to an external precision

7.4.1. Luminance DAC

1.232 volt reference, which then overrides the in- The Y pin is driven from a 10-bit 27 MHz current

ternal reference.

output DAC that internally receives the Y, or lumi-

nance portion, of the video signal (black and white

only). Y is designed to drive proper video levels

into a 37.5 Ω load. Reference the detailed electrical

section of this data sheet for the exact Y digital to

analog AC and DC performance data. A EN_L en-

able control bit in the Control Register 5 (0×05) is

provided to enable or disable the luminance DAC.

For a complete disable and lower power operation

the luminance DAC can be totally shut down via

the SVIDLUM_PD control bit in the Control Regis-

ter 4 (0×04). In this mode, turn-on through the con-

trol register will not be instantaneous.

7.3. ISET

All six of the CS4954/5 digital to analog converter

DACs are output current normalized with a com-

mon ISET device pin. The DAC output current per

bit is determined by the size of the resistor connect-

ed between ISET and electrical ground. Typically a

4 KΩ, 1% metal film resistor should be used. The

ISET resistance can be changed by the user to ac-

commodate varying video output attenuation via

post filters and also to suit individual preferred per-

formance.

In conjunction with the ISET value, the user can

also independently vary the chroma, luma and col-

orburst amplitude levels via host addressable con-

trol register bits that are used to control internal

7.4.2. Chrominance DAC

The C pin is driven from a 10-bit 27 MHz current

output DAC that internally receives the C or

30

DS278PP4

CS4954 CS4955

chrominance portion of the video signal (color current flow from the output. For a complete dis-

only). C is designed to drive proper video levels able and lower power operation, the red DAC can

into a 37.5 Ω load. Reference the detailed electrical be totally shut down via the R_PD control register

section of this data sheet for the exact C digital to bit in Control Register 4 (0×04). In this mode turn-

analog AC and DC performance data. A EN_C en-

on through the control register will not be instanta-

able control register bit in the Control Register 1 neous.

(0×05) is provided to enable or disable the chromi-

7.4.5. Green DAC

nance DAC. For a complete disable and lower

power operation the chrominance DAC can be to-

tally shut down via the SVIDCHR_PD register bit

in the Control Register 4 (0×04). In this mode turn-

on through the control register will not be instanta-

neous.

The green pin is driven from a 10-bit 27 MHz cur-

rent output DAC that internally receives a com-

bined luma and chroma signal to provide

composite video output. Green is designed to drive

proper composite video levels into a 37.5 Ω load.

Reference the detailed electrical section of this data

sheet for the exact green digital to analog AC and

DC performance data. The EN_G enable control

7.4.3. CVBS DAC

The CVBS pin is driven from a 10-bit 27 MHz cur-

rent output DAC that internally receives a com- register bit, in Control Register 1 (0×05), is provid-

bined luma and chroma signal to provide ed to enable or disable the output pin. When dis-

composite video output. CVBS is designed to drive

abled, there is no current flow from the output. For

proper composite video levels into a 37.5 Ω load. a complete disable and lower power operation, the

Reference the detailed electrical section of this data

sheet for the exact CVBS digital to analog AC and

DC performance data. The EN_COM enable con-

green DAC can be totally shut down via the G_PD

control register bit in Control Register 4 (0×04). In

this mode turn-on through the control register will

trol register bit, in Control Register 1 (0×05), is not be instantaneous.

provided to enable or disable the output pin. When

7.4.6. Blue DAC

disabled, there is no current flow from the output.

The blue pin is driven from a 10-bit 27 MHz cur-

For a complete disable and lower power operation,

the CVBS37 DAC can be totally shut down via the

COMDAC_PD control register bit in Control

Register 4 (0×04). In this mode turn-on through the

control register will not be instantaneous.

rent output DAC that internally receives a com-

bined luma and chroma signal to provide

composite video output. Blue is designed to drive

proper composite video levels into a 37.5 Ω load.

Reference the detailed electrical section of this data

sheet for the exact blue digital to analog AC and

DC performance data. The EN_B enable control

7.4.4. Red DAC

The Red pin is driven from a 10-bit 27 MHz current

output DAC that internally receives a combined register bit, in Control Register 5 (0×05), is provid-

luma and chroma signal to provide composite vid- ed to enable or disable the output pin. When dis-

eo output. Red is designed to drive proper compos- abled, there is no current flow from the output. For

ite video levels into a 37.5 Ω load. Reference the

detailed electrical section of this data sheet for the blue DAC can be totally shut down via the B_PD

exact red digital to analog AC and DC performance control register bit in Control Register 4 (0×04). In

a complete disable and lower power operation, the

data. The EN_R enable control register bit, in Con- this mode turn-on through the control register will

trol Register 1 (0×05), is provided to enable or dis- not be instantaneous.

able the output pin. When disabled, there is no

DS278PP4

31

CS4954 CS4955

If some of the 6 DACs are not used, it is strongly

recommended to power them down (see

CONTROL_4 register) in order to reduce the pow-

er dissipation.

Low/High

Impedance

mode

Nominal Power

supply

maximum # of

active DACs

3.3V

5.0V

Low Impedance

High Impedance

Low Impedance

High Impedance

3

6

3

6

Depending on the external resistor connected to the

ISET pin the output drive of the DACs can be

changed. There are two modes in which the DACs

should either be operated in. An external resistor of

4 kΩ must be connected to the ISET pin.

Table 8. Maximum DAC Numbers

8. PROGRAMMING

The first mode is the high impedance mode

(LOW_IMP bit set to 0). The DAC outputs will

then drive a double terminated load of 300 Ω and

will output a video signal which conforms to the

analog video specifications for NTSC and PAL.

External buffers will be needed if the DAC output

load differs from 300 Ω.

8.1. Host Control Interface

The CS4954/5 host control interface can be config-

2

ured for I C or 8-bit parallel operation. The

2

CS4954/5 will default to I C operation when the

RD and WR pins are both tied low at power up. The

RD and WR pins are active for 8-bit parallel oper-

ation only.

The second mode is the low impedence mode

(LOW_IMP but set to 1). The DAC output will

then drive a double terminated load of 75 Ω and

will output a video signal which conforms to the

analog video specifications for NTSC and PAL. No

external buffers are necessary, the ouputs can di-

rectly drive a television input.

8.1.1. I²C Interface

2

The CS4954/5 provides an I C interface for access-

ing the internal control and status registers. Exter-

nal pins are a bidirectional data pin (SDA) and a

serial input clock (SCL). The protocol follows the

2

I C specifications. A complete data transfer is

2

Note that for power dissipation purposes it is not

always possible to have all the 6 DACs active at the

same time. Table 8 shows the maximum allowed

active DACs depending on the power supply and

low/high impedance modes. If less than 6 DACs

are allowed to be active the other ones must be

power down (see CONTROL_4 register).

shown in Figure 26. Note that this I C interface will

work in Slave Mode only - it is not a bus master.

SDA and SCL are connected via an external pull-

up resistor to a positive supply voltage. When the

bus is free, both lines are high. The output stages of

devices connected to the bus must have an open-

drain or open-collector in order to perform the

2

wired-AND function. Data on the I C bus can be

SDA

SCL

1-7

8

9

1-7

8

9

1-7

8

9

A

P

Start Address R/W

ACK

Data

ACK

Data ACK

Stop

Note: I²C transfers data always with MSB first, LSB last

Figure 26. I²C Protocol

32

DS278PP4

CS4954 CS4955

transferred at a rate of up to 400 Kbits/sec in fast

mode. The number of interfaces to the bus is solely

dependent on the limiting bus capacitance of 400

pF. When 8-bit parallel interface operation is being

active low strobes and host address enable

(ADDR), which, when low, enables unique address

register accesses. The control port is used to access

internal registers which configure the CS4954/5 for

used, SDA and SCL can be tied directly to ground. various modes of operation. The internal registers

2

are uniquely addressed via an address register. The

address register is accessed during a host write cy-

cle with the WR and ADDR pins set low. Host

write cycles with ADDR set high will write the 8-

bits on the PDAT [7:0] pins into the register cur-

rently selected by the address register. Likewise

read cycles occur with RD set low and ADDR set

high will return the register contents selected by the

address register. Reference the detailed electrical

timing parameter section of this data sheet for exact

host parallel interface timing characteristics and

specifications.

The I C bus address for the CS4954/5 is program-

mable via the I2C_ADR Register (0×0F). When

I C interface operation is being used, RD and WR

must be tied to ground. PDAT [7:0] are available to

be used for GPIO operation in I C host interface

mode. For 3.3 V operation it is necessary to have

the appropriate level shifting for I C signals.

2

8.1.2. 8-bit Parallel Interface

The CS4954/5 is equipped with a full 8-bit parallel

microprocessor write and read control port. Along

with the PDAT [7:0] pins, the control port interface

is comprised of host read (RD) and host write (WR)

WR

T_rec

RD

Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle

T_rd

T_rah

T_rpw

ADDR

PDAT[7:0]

T_rdh

T_rda

T_as

Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle

DS278PP4

33

CS4954 CS4955

T_wr

T_wac

T_wpw

WR

ADDR

PDAT[7:0]

T_as

Figure 29. 8-bit Parallel Host Port Timing: Address Write Cycle

T_wdsT_wdh

subsequent register description section describe the

8.2. Register Description

full register map for the CS4954 only. A complete

CS4955 register set description is available only to

Macrovision ACP-PPV Licensed Buyers.

A set of internal registers are available for control-

ling the operation of the CS4954/5. The registers

extend from internal address 0×00 through 0×5A.

Table 9 shows a complete list of these registers and

their internal addresses. Note that this table and the

8.2.1. Control Registers

Address

0×00

0×01

0×02

0×03

0×04

0×05

0×06

0×07

0×08

0×09

0×0A

0×0B

0×0C

0×0D

0×0E

0×0F

0×10

0×11

0×12

0×13

0×14

0×15

0×16

Register Name

control_0

Type

r/w

Default value

01h

02h

00h

3Fh

00h

control_1

control_2

control_3

control_4

control_5

control_6

RESERVED

bkg_color

r/w

03h

00h

gpio_ctrl_reg

gpio_data_reg

RESERVED

SYNC_0

r/w

90h

F4h

00h

1Ch

3Eh

F8h

E0h

43h

00h

SYNC_1

I²C_ADR

SC_AMP

SC_SYNTH0

SC_SYNTH1

SC_SYNTH2

SC_SYNTH3

HUE_LSB

HUE_MSB

Table 9. Control Registers

34

DS278PP4

CS4954 CS4955

Address

0×17

0×18

Register Name

SCH PHASE ADJUST

CC_EN

Type

r/w

Default value

00h

0×19

CC_21_1

r/w

0×1A

0×1B

0×1C

0×1D

0×1E

0×1F

0×20

0×21

0×22

0×23

0×24

0×25

0×26

0×27

0×28

0×29

0×2A

0×2B

0×2C

0×2D

0×2E

0×2F

0×30

0×31

0×32

0×33

CC_21_2

r/w

CC_284_1

CC_284_2

RESERVED

WSS_REG_0

WSS_REG_1

WSS_REG_2

RESERVED

CB_AMP

r/w

00h

r/w

80h

00h

A1h

02h

00h

CR_AMP

Y_AMP

r/w

R_AMP

r/w

G_AMP

r/w

B_AMP

r/w

BRIGHT_OFFSET

TTXHS

r/w

TTXHD

r/w

TTXOVS

r/w

TTXOVE

r/w

TTXEVS

r/w

TTXEVE

r/w

TTX_DIS1

TTX_DIS2

TTX_DIS_3

INT_EN

r/w

INT_CLR

r/w

0×34

STATUS_0

RESERVED

STATUS_1

RESERVED

read only

0×35 - 0×59

0×5A

0×61 - 0×7F

read only

04h

Table 9. Control Registers (Continued)

DS278PP4

35

CS4954 CS4955

Control Register 0

Address

0×00

CONTROL_0 Read/Write

Default Value = 01h

Bit Number

Bit Name

Default

7

6

TV_FMT

0

5

4

MSTR

0

3

CCIR656

0

2

PROG

0

1

0

IN_MODE CBCR_UV

0

1

Bit

Mnemonic

Function

selects the TV display format

000:

NTSC-M CCIR601 timing (default)

NTSC-M RS170A timing

PAL-B, D, G, H, I

001:

010:

7:5

TV_FMT

011:

PAL-M

100:

PAL-N (Argentina)

PAL-N (non Argentina)

reserved

101:

110-111:

4

3

2

1

0

MSTR

CCIR656

PROG

1 = Master Mode, 0 = Slave Mode

video input is in ITU R.BT656 format (0 = off, 1 = on)

Progressive scanning enable (enable = 1)

IN_MODE

CBCR_UV

Input select (0 = solid background, 1 = use V [7:0] data)

enable YCbCr to YUV conversion (1 = enable, 0 = disable)

Control Register 1

Address

0×01

CONTROL_1 Read/Write

Default Value = 02h

7

6

5

CH BW

0

4

LPF_ON

0

3

RGB_BW

0

2

FLD

0

1

PED

1

0

CBCRSEL

0

Bit Number

Bit Name

Default

LUM DEL

0

Bit

Mnemonic

Function

luma delay on the composite1 output

00:

01:

10:

11:

no delay (default)

7:6

LUM DEL

1 pixel clock delay

2 pixel clock delay

3 pixel clock delay

5

4

3

2

1

0

CH BW

LPF ON

RGB_BW

FLD_POL

PED

chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 Mhz)

chroma lpf on/off (0 = off, 1 = on)

0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0)

Polarity of Field (0: odd field = 0,1: odd field = 1)

Pedestal offset (0: 0 IRE, 1: 7.5 IRE)

CBCRSEL

CbCr select (0 = chroma undelayed, 1 = chroma delayed by one clock)

36

DS278PP4

CS4954 CS4955

Control Register 2

Address

0×02

CONTROL_2 Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

TTX WST

0

3

2

1

XTAL

0

SC_EN

0

OUTPUT FORMAT

0

TTX EN SYNC_DLY

0

Bit

Mnemonic

Function

selects the output through the DACs

000 :

rgb, s-video, composite1 (6 DACs) (default)

yuv, s-video, composite1 (6 DACs)

s-video, composite1, composite2, (4 DACs)

rgb, composite1, composite2 (5 DACs)

yuv, composite1, composite2 (5 DACs)

don’t care

001 :

7:5

OUTPUT FORMAT

010 :

011 :

100 :

101-111:

To select between world standard (NTSC), world standard (PAL), or north

american teletext standard during NTSC or PAL modes (1 = WST TTX) (default

is 0)

In NTSC-M or PAL-M mode. This bit works in conjunction with the TV FORMAT

register.

4

TTX WST

0:

1:

0:

1:

NABTS, if TV FORMAT is NTSC or PAL-M

WST (NTSC), if TV FORMAT is NTSC or PAL-M

Europe TTX, if TV FORMAT is PAL-B, G..., N

WST (PAL), if TV FORMAT is PAL-B, G, ..., N

3

2

1

0

TTX EN

SYNC DLY

XTAL

Enable teletext process (1 = enable)

Slave mode 1 pixel sync delay (1 = enable)

Crystal oscillator for subcarrier adjustment enable (1 = enable)

Chroma burst disable (1 = disable)

BU DIS

DS278PP4

37

CS4954 CS4955

Control Register 3

Address

0×03

CONTROL_3 Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

CBAR

0

RESERVED

0

FD THR C1 FD THR C2 FD THR SV FD THR EN

0

Bit

7:5

4

Mnemonic

-

Function

reserved

FD THR C1

FD THR C2

FD THR SV

FD THR_EN

CBAR

feedthrough enabled for composite 1 output (0 = off, 1 = on)

feedthrough enabled for composite 2 output (0 = off, 1 = on)

3

2

feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on)

Enable (1 = enable) input to feed through during inactive lines

internal color bar generator (0 = off, 1 = on)

1

0

Control Register 4

Address

0×04

CONTROL_4 Read/Write

Default Value = 3Fh

7

6

5

4

3

2

1

G_PD

1

0

Bit Number

CB_H_SEL

0

CB_FLD_SEL COMDAC_PD SVIDLUM_PD SVIDCHR_PD R_PD

B_PD

Bit Name

Default

0

1

Bit

7

Mnemonic

CB_H_SEL

Function

Composite Blank / HSYNC output select (1 = CB select, 0 = HSYNC select)

Composite Blank / FIELD output select (1 = CB select, 0 = HSYNC select)

power down composite DAC

6

CB_FLD_SEL

5

4

3

2

1

0

COMDAC_PD

SVIDLUM_PD

SVIDCHR_PD

R_PD

0: power up, 1: power down

power down luma s-video DAC

0: power up, 1: power down

power down chroma s-video DAC

0: power up, 1: power down

power down red rgb video DAC

0: power up, 1: power down

power down green rgb video DAC

0: power up, 1: power down

G_PD

power down blue rgb video DAC

B_PD

0: power up, 1: power down

38

DS278PP4

CS4954 CS4955

Control Register 5

Address

0×05

CONTROL_5 Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

LOW IMP

0

5

EN COM

0

4

EN L

0

3

EN C

0

2

EN R

0

1

EN G

0

EN B

0

RSVD

0

Bit

7

Mnemonic

-

Function

reserved

6

LOW IMP

EN COM

EN L

selects between high output impedance (0) or low output impedance (1) mode of DACs

enable DAC for composite output 0: tri-state, 1: enable

5

4

enable s-video DAC for luma output 0: tri-state, 1: enable

enable s-video DAC for chroma output 0: tri-state, 1: enable

enable rgb video DAC for red output 0: tri-state, 1: enable

enable rgb video DAC for green output 0: tri-state, 1: enable

enable rgb video DAC for blue output 0: tri-state, 1: enable

3

EN C

2

EN_R

1

EN_G

EN_B

0

Control Register 6

Address

0×06

CONTROL_6 Read/Write

Default Value = 00h

7

6

CLIP OFF

0

5

4

3

2

1

0

Bit Number

Bit Name

656 SYNC

OUT

TTXEN

COM2

TTXEN

COM1

TTXEN

SVID

BSYNC DIS GSYNC DIS RSYNC DIS

Default

0

Bit

7

Mnemonic

656 SYNC OUT

CLIP OFF

Function

Enable (=1) output of hsync and vsync in the ITU R.BT656 mode

Clipping input signals disable (0: clipping active 1: no clipping)

6

5

TTXEN COM2 Enable teletext at the composit2 output (0: disable teletext, 1 : enable teletext)

4

TTXEN COM1

TTXEN SVID

BSYNC DIS

GSYNC DIS

RSYNC DIS

Enable teletext at the composit1 output ( 0: disable teletext, 1 : enable teletext)

Enable teletext at the s-video output ( 0: disable teletext, 1: enable teletext)

Disable syncs in the blue or v output (0: enable syncs, 1: disable syncs)

Disable syncs in the green or u output ( 0: enable syncs, 1: disable syncs)

Disable syncs in the red or y output (0: enable syncs, 1: disable syncs)

3

2

1

0

DS278PP4

39

CS4954 CS4955

Background Color Register

Address

0×08

BKG_COLOR Read/Write

Default Value = 03h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

BG

0

1

Bit

Mnemonic

Function

7:0

BG

Background color (7:5 = R, 4:2 = G, 1:0 = B) (default is 0000 0011 - blue)

GPIO Control Register

Address

0×09

GPIO__REG Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

GPR_CNTRL

0

Bit

Mnemonic

Function

7:0

GPR CNTRL

Input(0)/output(1) control of GPIO registers (bit 0: PDAT(0), bit 7: PDAT(7))

GPIO Data Register

Address

0×0A

GPIO_REG

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

GPIO REG

0

Bit

Mnemonic

Function

GPIO data register ( data is output on PDAT bus if appropriate bit in address 09 is

set to “1”, otherwise data is input/output through I²C)- This register is only accessible

in I²C mode.

7:0

GPIO REG

Sync Register 0

Address

0×0D

Sync_0

Read/Write

Default Value = 90h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

PROG VS[4:0]

0

PROG HS[10:8]

0

1

0

1

0

Bit

7:3

2:0

Mnemonic

PROG VS[4:0] programmable vsync lines

PROG HS[10:8] programmable hsync pixels (3 most significant bits)

Function

40

DS278PP4

CS4954 CS4955

Sync Register 1

Address

0×0E

Sync_1

Read/Write

Default Value = F4h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

PROG HS[7:0]

1

0

1

0

Bit

Mnemonic

Function

7:0

PROG HS[7:0]

programmable hsync pixels lsb

2

I C Address Register

Address

0×0F

I²C_ADR

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

I²C ADR

0

RESERVED

0

Bit

7

Mnemonic

Function

-

reserved

I²C device address (programmable)

I²C

6:0

Subcarrier Amplitude Register

Address

0×10

SC_AMP

Read/Write

Default Value = 1Ch

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

BU AMP

0

1

0

Bit

Mnemonic

Function

7:0

BU AMP

Color burst amplitude

Subcarrier Synthesis Register

Address

0×11

0×12

0×13

0×14

SC_SYNTH0 Read/Write

SC_SYNTH1

SC_SYNTH2

Default Value = 3Eh

F8h

E0h

43h

SC_SYNTH3

Register

Bits

7:0

Mnemonic

Function

SC_SYNTH0

SC_SYNTH1

SC_SYNTH2

SC_SYNTH3

CC 0

CC 1

CC 2

CC 3

Subcarrier synthesis bits 7:0

Subcarrier synthesis bits 15:8

7:0

Subcarrier synthesis bits 23:16

Subcarrier synthesis bits 31:24

7:0

DS278PP4

41

CS4954 CS4955

Hue LSB Adjust Register

Address

0×15

HUE_LSB

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

HUE LSB

0

Bit

Mnemonic

Function

7:0

HUE LSB

8 LSBs for hue phase shift

Hue MSB Adjust Register

Address

0×16

HUE_MSB

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

RESERVED

MSB

0

Bit

7:2

1:0

Mnemonic

-

Function

reserved

2 MSBs for hue phase shift

HUE MSB

SCH Sync Phase Adjust

Address

0×17

SCH

Read/Write

Default Value = 00h

Bit

Mnemonic

Function

7:0

SCH

Default - 00h in increments of ≈1.4 degree per bit up to 360°

Closed Caption Enable Register

Address

0×18

CC_EN

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

RESERVED

EN_284

0

EN_21

0

Bit

7:2

1

Mnemonic

-

Function

reserved

CC EN[1]

CC EN[0]

enable closed caption for line 284

enable closed caption for line 21

0

42

DS278PP4

CS4954 CS4955

Closed Caption Data Register

Address

0×19

0×1A

0×1B

0×1C

CC_21_1

CC_21_2

CC_284_1

CC_284_2

Read/Write

Default Value = 00h

00h

Bit

7:0

Mnemonic

CC_21_1

Function

first closed caption databyte of line 21

second closed caption databyte of line 21

first closed caption databyte of line 284

second closed caption databyte of line 284

CC_21_2

CC_284_1

CC_284_2

Wide Screen Signaling Register 0

Address

0×1E

WSS_REG_0 Read/Write

Default Value = 00h

7

WSS_23

0

6

WSS_22

0

5

WSS_21

0

4

WSS_20

0

3

WSS_19

0

2

WSS_18

0

1

WSS_17

0

WSS_16

0

Bit Number

Bit Name

Default

Bit

Mnemonic

Function

7

WSS_23

Enable wide screen signalling (enable =1)

PAL: enable WSS (enable = 1) on line 23 of field 2,

NTSC: don’t care

6

WSS_22

5

4

3

2

1

0

WSS_21

WSS_20

WSS_19

WSS_18

WSS_17

WSS_16

PAL: group 4, bit 13, NTSC: don’t care

PAL: group 4, bit 12, NTSC: don’t care

PAL: group 4, bit 11, NTSC: bit 20

PAL: group 3, bit 10, NTSC: bit 19

PAL: group 3, bit 9, NTSC: bit 18

PAL: group 3, bit 8, NTSC: bit 17

DS278PP4

43

CS4954 CS4955

Wide Screen Signalling Register 1

Address

0×1F

WSS_REG_1 Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

WSS_15

0

6

WSS_14

0

5

WSS_13

0

4

WSS_12

0

3

WSS_11

0

2

WSS_10

0

1

WSS_9

0

WSS_8

0

Bit

7

Mnemonic

WSS_15

WSS_14

WSS_13

WSS_12

WSS_11

WSS_10

WSS_9

Function

PAL: group 2, bit 7, NTSC: bit 16

PAL: group 2, bit 6, NTSC: bit 15

PAL: group 2, bit 5, NTSC: bit 14

PAL: group 2, bit 4, NTSC: bit 13

PAL: group 1, bit 3, NTSC: bit 12

PAL: group 1, bit 2, NTSC: bit 11

PAL: group 1, bit 1, NTSC: bit 10

PAL: group 1, bit 0, NTSC: bit 9

6

5

4

3

2

1

0

WSS_8

Wide Screen Signalling Register 2

Address

0×20

WSS_REG_2 Read/Write

Default Value = 00h

7

WSS_7

0

6

WSS_6

0

5

WSS_5

0

4

WSS_4

0

3

WSS_3

0

2

WSS_2

0

1

WSS_1

0

WSS_0

0

Bit Number

Bit Name

Default

Bit

7

Mnemonic

WSS_7

WSS_6

WSS_5

WSS_4

WSS_3

WSS_2

WSS_1

WSS_0

Function

PAL: don’t care, NTSC: bit 8

PAL: don’t care, NTSC: bit 7

PAL: don’t care, NTSC: bit 6

PAL: don’t care, NTSC: bit 5

PAL: don’t care, NTSC: bit 4

PAL: don’t care, NTSC: bit 3

PAL: don’t care, NTSC: bit 2

PAL: don’t care, NTSC: bit 1

6

5

4

3

2

1

0

Filter Register 0

Address

0×22

CB_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

U_AMP

1

0

Bit

Mnemonic

U_AMP

Function

7:0

U(Cb) amplitude coefficient

44

DS278PP4

CS4954 CS4955

Filter Register 1

Address

0×23

CR_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

V_AMP

1

0

Bit

Mnemonic

Function

7:0

V_AMP

V(Cr) amplitude coefficient

Filter Register 2

Address

0×24

Y_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

Y_AMP

1

0

Bit

Mnemonic

Function

7:0

Y_AMP

Luma amplitude coefficient

Filter Register 3

Address

0×25

R_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

R_AMP

1

0

Bit

Mnemonic

Function

7:0

R_AMP

Red amplitude coefficient

Filter Register 4

Address

0×26

G_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

G_AMP

1

0

Bit

Mnemonic

Function

7:0

G_AMP

Green amplitude coefficient

DS278PP4

45

CS4954 CS4955

Filter Register 5

Address

0×27

B_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

B_AMP

1

0

Bit

Mnemonic

Function

7:0

B_AMP

Blue amplitude coefficient

Filter Register 6

Address

0×28

Bright_Offsett Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

BRIGHTNESS_OFFSET

0

Bit

Mnemonic

Function

7:0

BRGHT_OFFSET Brightness adjustment ( range: -128 to +127)

Teletext Register 0

Address

0×29

TTXHS

Read/Write

Default Value = A1h

7

6

5

4

3

2

1

0

Bit Number

Bit Name

Default

TTXHS

1

0

1

0

1

Bit

Mnemonic

Function

Start of teletext request pulses or start of window

7:0

TTXHS

Teletext Register 1

Address

0×2A

TTXHD

Read/Write

Default Value = 02h

7

6

5

4

3

2

1

0

Bit Number

Bit Name

Default

TTXHD

0

1

0

Bit

Mnemonic

Function

If TTX_WINDOW = 0 then this register is used as the Pipeline delay between

TTXRQ and TTXDAT signal in the teletext source. User programmable delay step

of 37 ns per LSB.

7:0

TTXHD

If TTX_WINDOW = 1 then this register is used as the 8 LSBs of the teletext insertion

windows; the 3 MSBs are located in register 0×31. (register 0×31 bit 3)

46

DS278PP4

CS4954 CS4955

Teletext Register 2

Address

0×2B

TTXOVS

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

TTXOVS

0

Bit

Mnemonic

Function

Start of teletext line window in odd field

7:0

TTXOVS

Teletext Register 3

Address

0×2C

TTXOVE

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

TTXOVE

0

Bit

Mnemonic

Function

End of teletext line window in odd field

7:0

TTXOVE

Teletext Register 4

Address

0×2D

TTXEVS

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

TTXEVS

0

Bit

Mnemonic

Function

Start of teletext line window in even field

7:0

TTXEVS

Teletext Register 5

Address

0×2E

TTXEVE

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

TTXEVE

0

Bit

Mnemonic

Function

End of teletext line window in even field

7:0

TTXEVE

DS278PP4

47

CS4954 CS4955

Teletext Register 6

Address

0×2F

TTX_DIS1

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

TTX_LINE_DIS1

0

Bit

Mnemonic

Function

Teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all

eight lines are disabled),

7:0

TTX_LINE_DIS1

(MSB is for line 5, LSB is for line 12)

Teletext Register 7

Address

0×30

TTX_DIS2

Read/Write

Default Value = 00h

7

6

5

4

3

2

1

0

Bit Number

Bit Name

Default

TTX_LINE_DIS2

0

Bit

Mnemonic

Function

Teletext disable bits corresponding to the lines 13-20 respectively, (11111111=all

eight lines are disablled,

7:0

TTX_LINE_DIS2

(MSB is for line 13, LSB is for line 20)

Teletext Register 8

Address

0×31

TTX_DIS3

Read/Write

Default Value = 00h

7

6

TTXHD

0

5

4

3

2

1

0

Bit Number

Bit Name

Default

RESERVED TTX_WINDOW

TTX_LINE_DIS3

0

Bit

Mnemonic

TTXHD

Function

If TTX_WINDOW = 0 these 3 bits are unused.

If TTX_WINDOW = 1 these 3 bits are the MSBs of the register 0×2A; they are used

to specify the length of the teletext insertion window

7:5

4

3

Reserved

TTX_WINDOW Selects between TTXRQ (= 0) pulsation or TTXRQ (= 1) Window mode

Teletext disable bits corresponding to the lines 13-20 respectively, (111=all three

lines are disabled),

2:0

TTX_LINE_DIS3

(MSB is for line 21, LSB is for line 23)

48

DS278PP4

CS4954 CS4955

Interrupt Register 0

Address

0×32

INT_EN

Read/Write

Default Value = 00h

7

6

5

4

3

2

1

0

INT_V_EN

0

Bit Number

Bit Name

Default

RESERVED

0

INT_21_EN INT_284_EN

0

Bit

7:3

2

Mnemonic

-

Function

reserved

INT_21_EN

INT_284_EN

INT_V_EN

interrupt enable for closed caption line 21

interrupt enable for closed caption line 284

interrupt enable for new video field

1

0

Interrupt Register 1

Address

0×33

INT_CLR

Read/Write

Default Value = 00h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

RESERVED

0

CLR_INT_21

0

CLR_INT_284

0

CLR_INT_V

0

Bit

7:3

2

Mnemonic

Function

-

reserved

CLR_INT_21

CLR_INT_284

CLR_INT_V

clear interrupt for closed caption line 21 (INT 21)

clear interrupt for closed caption line 284 (INT_284)

clear interrupt for new video field (INT_V)

1

0

Status Register 0

Address

0×34

STATUS_0

Read Only

Default Value = 00h

5

4

3

INT_V

0

2:0

FLD

0

Bit Number

Bit Name

Default

INT_21

0

INT_284

0

Bit

5

Mnemonic

INT_21

Function

Interrupt flag for line 21 (closed caption) complete

Interrupt flag for line 284 (closed caption) complete

Interrupt flag for video field change

4

INT_284

INT_V

3

2:0

FLD_ST

Field Status bits(001 = field 1,000 = field 8)

Status Register 1

Address

0×5A

STATUS_1

Read only

Default Value = 04h

Bit Number

Bit Name

Default

7

6

5

4

3

2

1

0

DEVICE_ID

0

1

0

Bit

Mnemonic

Function

7:0

DEVICE_ID

Device identification: CS4954: 0000 0100, CS4955: 0000 0101

DS278PP4

49

CS4954 CS4955

Place all decoupling caps as close as possible the

the device as possible. Surface mount capacitors

generally have lower inductance than radial lead or

axial lead components. Surface mount caps should

be place on the component side of the PCB to min-

imize inductance caused by board vias. Any vias,

especially to ground, should be as large as possible

to reduce their inductive effects.

9. BOARD DESIGN AND LAYOUT

CONSIDERATIONS

The printed circuit layout should be optimized for

lowest noise on the CS4954/5 placed as close to the

output connectors as possible. All analog supply

traces should be as short as possible to minimize in-

ductive ringing.

A well designed power distribution network is es-

sential in eliminating digital switching noise. The

ground planes must provide a low-impedance re-

turn path for the digital circuits. A PC board with a

minimun of four layers is recommended. The

ground layer should be used as a shield to isolate

noise from the analog traces. The top layer (1)

should be reserved for analog traces but digital

traces can share this layer if the digital signals have

low edge rates and switch little current or if they are

separated from the analog traces by a signigicant

distance (dependent on their frequency content and

current). The second layer should then be the

ground plane followed by the analog power plane

on layer three and the digital signal layer on layer

four.

9.3. Digital Interconnect

The digital inputs and outputs of the CS4954/5

should be isolated from the analog outputs as much

as possible. Use separate signal layers whenever

possible and do not route digital signals over the

analog power and ground planes.

Noise from the digital section is related to the digi-

tal edge rates used. Ringing, overshoot, under-

shoot, and ground bounce are all related to edge

rate. Use lower speed logic such as HCMOS for the

host port interface to reduce switching noise. For

the video input ports, higher speed logic is re-

quired, but use the slowest practical edge rate to re-

duce noise. To reduce noise, it is important to

match the source impedance, line impedance, and

load impedance as much as possible. Generally, if

the line length is greater than one fourth the signal

edge rate, line termination is necessary. Ringing

can also be reduced by damping the line with a se-

ries resistor (22-150 Ω). Under extreme cases, it

may be advisable to use microstrip techniques to

further reduce radiated switching noise if very fast

edge rates (<2ns) are used. If microstrip techniques

are used, split the analog and digital ground planes

and use proper RF decoupling techniques.

9.1. Power and Ground Planes

The power and ground planes need isolation gaps

of at least 0.05" to minimize digital switching noise

effects on the analog signals and components. A

split analog/digital ground plane should be con-

nected at one point as close as possible to the

CS4954/5.

9.2. Power Supply Decoupling

Start by reducing power supply ripple and wiring

harness inductance by placing a large (33-100 uF)

capacitor as close to the power entry point as pos-

sible. Use separate power planes or traces for the

digital and analog sections even if they use the

same supply. If necessary, further isolate the digital

and analog power supplies by using ferrite beads on

each supply branch followed by a low ESR capac-

itor.

9.4. Analog Interconnect

The CS4954/5 should be located as close as possi-

ble the output connectors to minimize noise pickup

and reflections due to impedance mismatch. All un-

used analog outputs should be placed in shutdown.

This reduces the total power that the CS4954/5 re-

quires, and eliminates the impedance mismatch

50

DS278PP4

CS4954 CS4955

presented by an unused connector. The analog out- idea to use output filters that are AC coupled to

puts should not overlay the analog power plane to avoid any problems.

maximize high frequency power supply rejection.

9.6. ESD Protection

9.5. Analog Output Protection

All MOS devices are sensitive to Electro Static

To minimize the possibility of damage to the ana- Discharge (ESD). When manipulating these devic-

log output sections, make sure that all video con- es, proper ESD precautions are recommended to

nectors are well grounded. The connector should

avoid performance degradation or permanent dra-

have a good DC ground path to the analog and dig- mage.

ital power supply grounds. If no DC (and low fre-

9.7. External DAC Output Filter

quency) path is present, improperly grounded

equipment can impose damaging reverse currents

on the video out lines. Therefore, it is also a good

If an output filter is required, the low pass filter

shown in Figure 30 can be used.

2.2µH

IN

OUT

C

2

C

1

330pF

220pF

Figure 30. External Low Pass Filter

C₂should be chosen so that C₁= C₂+ C_cable

DS278PP4

51

CS4954 CS4955

L1

Ferrite Bead

Vcc

4.7 µF

0.1 µF

17

36 41 46

15

VDD

VAA

XTALIN

14

16

NC

VREF

XTALOUT

PADDR

38

39

RED

75 or

300 Ω

30

31

TTXDAT

40

43

GREEN

BLUE

TTXRQ

PDAT[7:0]

RD

75 or

300 Ω

26-19

27

28

to SCART

Connector

Gpio port

Vcc

75or

300 Ω

WR

44

48

Video

1.5 kΩ

Composite

Connector

1.5 kΩ

110

CVBS

Y

Ω

CS4954

CS4955

32

75 or 300 Ω

SDA

SCL

I²C

Controller

33

110

Ω

S-Video

Connector

29

8

27 MHz Clock

Pixel Data

CLK

47

C

V[7:0]

8-1

9

75 or 300 Ω

/CB

FIELD

12

34

37

10

11

13

INT

RESET

ISET

HSYNC/CB

VSYNC

TEST

GNDD

GNDA

34 42 45

4 kΩ±1%

18

Figure 31. Typical Connection Diagram

52

DS278PP4

CS4954 CS4955

10. PIN DESCRIPTION

B

CVBS

GNDA

VAA

GNDA

VAA

G

R

C

VREF

ISET

Y

V0

VAA

48 47 46 45 44 43 42 41 40 39 38 37

V1

GNDA

RESET

SCL

1

36

35

34

33

32

31

30

29

28

27

26

25

2

V2

3

V3

4

V4

SDA

5

CS4954-CQ

CS4955-CQ

48-Pin TQFP

Top View

V5

6

TTXRQ

TTXDAT

CLKIN

WR

7

V6

8

V7

9

FIELD /CB

HSYNC/CB

VSYNC

INT

10

11

12

RD

PDAT0

PDAT1

PDAT2

PDAT3

PDAT4

PDAT5

PDAT6

PDAT7

13 14 15 16 17 18 19 20 21 22 23 24

TEST

XTAL_OUT

XTAL_IN

PADR

VDD

GNDD

DS278PP4

53

CS4954 CS4955

Pin Name

V [7:0]

Pin Number

Type

IN

Description

Digital video data inputs

8, 7, 6, 5, 4, 3, 2, 1

CLK

29

16

15

14

10

IN

27 MHz input clock

PADDR

IN

Address enable line

subcarrier crystal input

subcarrier crystal output

XTAL_IN

XTAL_OUT

IN

OUT

I/O

Active low horizontal sync, or composite blank signal

HSYNC/CB

VSYNC

11

9

I/O

OUT

IN

Active low vertical sync.

FIELD/CB

Video field ID. Selectable polarity or composite blank

Host parallel port read strobe, active low

27

RD

28

IN

Host parallel port write strobe, active low

WR

PDAT [7:0]

19, 20, 21, 22, 23, 24, 25, 26

I/O

IN

Host parallel port/ general purpose I/O

I²C data

SDA

SCL

CVBS

Y

32

33

44

48

47

39

40

43

38

I²C clock input

CURRENT Composite video output

CURRENT Luminance analog output

CURRENT Chrominance analog output

CURRENT Red analog output

C

R

G

CURRENT Green analog output

CURRENT Blue analog output

B

VREF

I/O

Internal voltage reference output or external refer-

ence input

CURRENT DAC current set

ISET

37

30

31

12

34

TTXDAT

TTXRQ

INT

IN

OUT

IN

Teletext data input

Teletext request output

Interrupt output, active high

Active low master RESET

RESET

TEST

VAA

13

36, 41, 46

18

IN

TEST pin. Ground for normal operation

+ 5 V or + 3.3 V supply (must be same as VDD)

Ground

PS

GNDD

VDD

17

+5 V or 3.3 V supply (must be same as VAA)

Ground

GNDA

35, 42, 45

Table 10. Device Pin Descriptions

54

DS278PP4

CS4954 CS4955

11. PACKAGE DRAWING

48L TQFP PACKAGE DRAWING

E

E1

D1

D

1

e

B

A

A1

L

INCHES

MILLIMETERS

MIN

DIM

A

A1

B

D

D1

E

E1

e*

L

MIN

---

MAX

1.60

0.15

0.27

9.30

7.10

9.30

7.10

0.60

0.75

7.00°

0.063

0.006

0.011

0.366

0.280

0.366

0.280

0.024

0.030

7.000°

---

0.002

0.007

0.343

0.272

0.343

0.272

0.016

0.018

0.000°

0.05

0.17

8.70

6.90

8.70

6.90

0.40

0.45

0.00°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm.

JEDEC Designation: MS026

DS278PP4

55


型号：	CS4954
厂家：	CIRRUS LOGIC
描述：	NTSC/PAL Digital Video Encoder NTSC / PAL数字视频编码器编码器
文件：	总56页 (文件大小：892K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS4954 [CIRRUS]

相关型号：

CS4954-CQ

CS4954-CQZ

CS4954_06

CS4955

CS4955-CQ

CS4955-CQZ

CS496102

CS496102-CQZ

CS496102-CQZ/A1

CS496112

CS496112-CQZ

CS496112-CQZ/A1