CS496112-CQZ/A1_技术文档

CS1810xx, CS4961xx, & CM-2

Digital AudioNetworking Processor

™

CobraNet

S i l i c o n S e r i e s

CS18100x, CS18101x, CS18102x, and CM-2

CS49610x, CS49611x, and CS49612x

Hardware User’s Manual

Version 2.3

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

JUN ’05

DS651UM23

http://www.cirrus.com

CobraNet Hardware User’s Manual

Table of Contents

List of Figures.........................................................................................................................................4

1.0 .Introduction .....................................................................................................................................5

2.0 Features...........................................................................................................................................6

2.1 CobraNet.............................................................................................................................6

2.2 CobraNet Interface..............................................................................................................6

2.3 Host Interface......................................................................................................................7

2.4 Asynchronous Serial Interface ............................................................................................7

2.5 Synchronous Serial Audio Interface....................................................................................7

2.6 Audio Clock Interface..........................................................................................................7

2.7 Audio Routing and Processing............................................................................................7

3.0 Hardware..........................................................................................................................................8

4.0 Pinout and Signal Descriptions ........................................................................................................9

4.1 CS1810xx & CS4961xx Package Pinouts.........................................................................10

4.1.1 CS1810xx/CS4961xx Pinout.............................................................................10

4.1.2 CM-2 Connector Pinout.....................................................................................11

4.2 Signal Descriptions ...........................................................................................................12

4.2.1 Host Port Signals ..............................................................................................12

4.2.2 Asynchronous Serial Port (UART Bridge) Signals ............................................12

4.2.3 Synchronous Serial (Audio) Signals..................................................................13

4.2.4 Audio Clock Signals ..........................................................................................13

4.2.5 Miscellaneous Signals.......................................................................................14

4.2.6 Power and Ground Signals ...............................................................................14

4.2.7 System Signals .................................................................................................15

4.3 Characteristics and Specifications ....................................................................................16

4.3.1 Absolute Maximum Ratings ..............................................................................16

4.3.2 Recommended Operating Conditions...............................................................16

4.3.3 Digital DC Characteristics .................................................................................16

4.3.4 Power Supply Characteristics ...........................................................................16

5.0 Synchronization..............................................................................................................................17

5.1 Synchronization Modes.....................................................................................................17

5.1.1 Internal Mode ....................................................................................................18

5.1.2 External Word Clock Mode ...............................................................................18

5.1.3 External Master Clock Mode.............................................................................18

6.0 Digital Audio Interface....................................................................................................................19

6.1 Digital Audio Interface Timing ...........................................................................................20

6.1.1 Normal Mode Data Timing ................................................................................21

2

6.1.2 I S Mode Data Timing.......................................................................................21

6.1.3 Standard Mode Data Timing .............................................................................22

7.0 Host Management Interface (HMI).................................................................................................23

7.1 Hardware...........................................................................................................................23

7.4 Protocol and Messages.....................................................................................................28

7.4.1 Messages..........................................................................................................28

7.4.1.1. Translate Address .................................................................................29

7.4.1.2. Interrupt Acknowledge...........................................................................29

7.4.1.3. Goto Packet...........................................................................................29

7.4.1.4. Goto Translation....................................................................................29

7.4.1.5. Packet Received ...................................................................................30

7.4.1.6. Packet Transmit ....................................................................................30

7.4.1.7. Goto Counters.......................................................................................30

7.4.2 Status................................................................................................................31

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7.4.3 Data...................................................................................................................32

7.4.3.1. Region length ........................................................................................32

7.4.3.2. Writable Region.....................................................................................32

7.4.3.3. Translation Complete ............................................................................32

7.4.3.4. Packet Transmission Complete.............................................................32

7.4.3.5. Received Packet Available....................................................................32

7.4.3.6. Message Togglebit................................................................................32

8.0 HMI Reference Code .....................................................................................................................33

8.1 HMI Definitions..................................................................................................................33

8.2 HMI Access Code .............................................................................................................34

8.3 CM-1, CM-2 Auto-detection ..............................................................................................36

9.0 Mechanical Drawings and Schematics ..........................................................................................37

9.1 CM-2 Mechanical Drawings ..............................................................................................38

9.2 CM-2 Schematics..............................................................................................................44

9.3 CS1810xx/CS4961xx Package.........................................................................................51

9.4 Temperature Specifications ..............................................................................................52

10.0 Ordering Information ....................................................................................................................53

10.1 Device Part Numbers......................................................................................................53

10.2 Device Part Numbering Scheme.....................................................................................53

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List of Figures

Figure 1. CobraNet Data Services .........................................................................................................5

Figure 2. CobraNet Interface Hardware Block Diagram.........................................................................8

Figure 3. Audio Clock Sub-system.......................................................................................................17

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) -

CS18100x/CS49610x & CS18101x/CS49611x............................................................19

Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) -

CS18102x/CS49612x...................................................................................................19

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1.....................................20

Figure 7. Serial Port Data Timing Overview.........................................................................................20

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS -

CS18100x/CS49610x, CS18101x/CS49611x ..............................................................21

Figure 9. Audio Data Timing Detail - Normal Mode, 128FS -

CS18102x/CS49612x...................................................................................................21

2

Figure 10. Audio Data Timing Detail - I S Mode, 64FS -

CS18100x/CS49610x, CS18101x/CS49611x ..............................................................21

2

Figure 11. Audio Data Timing Detail - I S Mode, 128FS -

CS18102x & CS49612x................................................................................................21

Figure 12. Audio Data Timing Detail - Standard Mode, 64FS -

CS18100x/CS49610x, CS18101x/CS49611x ..............................................................22

Figure 13. Audio Data Timing Detail - Standard Mode, 128FS -

CS18102x/CS49612x...................................................................................................22

Figure 14. Host Port Read Cycle Timing - Motorola Mode ..................................................................25

Figure 15. Host Port Write Cycle Timing - Motorola Mode...................................................................25

Figure 16. Parallal Control Port - Intel Mode Read Cycle ....................................................................27

Figure 17. Parallel Control Port - Intel Mode Write Cycle ....................................................................27

Figure 18. CM-2 Module Assembly Drawing, Top ...............................................................................38

Figure 19. CM-2 Module Assembly Drawing, Bottom ..........................................................................39

Figure 20. General PCB Dimensions...................................................................................................40

Figure 21. Example Configuration, Side View......................................................................................41

Figure 22. Faceplate Dimensions ........................................................................................................42

Figure 23. Connector Detail .................................................................................................................43

Figure 24. CM-2 RevF Schematic Page 1 of 7 ....................................................................................44

Figure 25. CM-2 RevF Schematic Page 2 of 7 ....................................................................................45

Figure 26. CM-2 RevF Schematic Page 3 of 7 ....................................................................................46

Figure 27. CM-2 RevF Schematic Page 4 of 7 ....................................................................................47

Figure 28. CM-2 RevF Schematic Page 5 of 7 ....................................................................................48

Figure 29. CM-2 RevF Schematic Page 6 of 7 ....................................................................................49

Figure 30. CM-2 RevF Schematic Page 7 of 7 ....................................................................................50

Figure 31. 144-Pin LQFP Package Drawing........................................................................................51

Figure 32. Device Part Numbering Explanation...................................................................................53

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CobraNet Hardware User’s Manual

Introduction

1.0 Introduction

This document is intended to help hardware designers integrate the CobraNet^TMinterface

into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x,

CS49611x, and CS49612x members of the CobraNet^TMSilicon Series of devices, where

“x” is the ROM version (ROM ID). This document also describes the CM-2 module with

schematics, mechanical drawings, etc.

CobraNet is a combination of hardware (the CobraNet interface), network protocol, and

firmware. CobraNet operates on a switched Ethernet network and provides the following

additional communications services.

• Isochronous (Audio) Data Transport

• Sample Clock Distribution

• Control and Monitoring Data Transport

The CobraNet interface performs synchronous-to-isochronous and isochronous-to-

synchronous conversions as well as the data formatting required for transporting real-time

digital audio over the network.

The CobraNet interface has provisions for carrying and utilizing control and monitoring

data such as Simple Network Management Protocol (SNMP) through the same network

connection as the audio. Standard data transport capabilities of Ethernet are shown here

as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data

communications and CobraNet applications can coexist on the same physical network.

Figure 1 illustrates the different data services available through the CobraNet system.

Isochronous Data

(Audio)

Ethernet

Unregulated

Traffic

Control Data

Clock

Figure 1. CobraNet Data Services

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Features

2.0 Features

2.1 CobraNet

• Real-time Digital Audio Distribution via Ethernet

• No Overall Limit on Network Channel Capacity

• Fully IEEE 802.3 Ethernet Standards Compliant

• Fiber optic and gigabit Ethernet variants are fully supported.

• Ethernet infrastructure can be used simultaneously for audio and data

communications.

• Free CobraCAD™ Audio Network Design Tool

• High-quality Audio Sample Clock Delivery Over Ethernet

• Bit-transparent 16-, 20-, and 24-bit Audio Transport

• Professional 48-kHz and 96-kHz sample rate

• Select Latency as Low as 1.33ms

• Flexible Many-to-many Network Audio Routing Capabilities

• Reduced-cost, Improved-performance, Convergent Audio Distribution

Infrastructure

2.2 CobraNet Interface

• 120 MIPS Customer-configurable Audio DSP

• Auto-negotiating 100Mbit Full-duplex Ethernet Connections

• Up to 32-channel Audio I/O Capability

• Implements CobraNet Protocol for real-time transport of audio over Ethernet.

• Local Management via 8-bit Parallel Host Port

• UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or

RARP

• Remote Management via Simple Network Management Protocol (SNMP)

• Economical Three-chip Solution

• Available Module form factor allows for flexible integration into audio products.

• Non-volatile Storage of Configuration Parameters

• Safely Upgrade Firmware Over Ethernet Connection

• LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status

• Watchdog Timer Output for System Integrity Assurance

• Comprehensive Power-on Self-test (POST)

• Error and Fault Reporting and Logging Mechanisms

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Features

2.3 Host Interface

• 8-bit Data, 4-bit Address

• Virtual 24-bit Addressing with 32-bit Data

• Polled, Interrupt, and DMA Modes of Operation

• Configure and Monitor CobraNet Interface

• Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed

2.4 Asynchronous Serial Interface

• Full-duplex Capable

• 8-bit Data Format

• Supports all Standard Baud Rates

2.5 Synchronous Serial Audio Interface

• Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O

• 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/

CS49611x

• 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x

• Accommodates Many Synchronous Serial Formats Including I²S

• 32-bit Data Resolution on All Audio I/O

2.6 Audio Clock Interface

• 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface

Design

• Low-jitter Master Audio Clock Oscillator (24.576 MHz)

• Synchronize to Supplied Master and/or Sample Clock

• Sophisticated jitter attenuation assures network perturbations do not affect

audio performance.

2.7 Audio Routing and Processing

• Single-channel Granularity in Routing From Synchronous Serial Audio

Interface to CobraNet Network

• Two levels of inward audio routing affords flexibility in audio I/O interface design

in the host system.

• Local Audio Loopback and Output Duplication Capability

• Peak-read Audio Metering with Ballistics

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Hardware

3.0 Hardware

Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture.

CobraNet CM-2

Module

Clock

Flash

Memory

Clock

VCXO

Control

Audio

Serial

Host

CS1810xx/

CS4961xx

Ethernet

Controller

Ethernet

Magnetics

Figure 2. CobraNet Interface Hardware Block Diagram

Flash memory holds the CobraNet firmware and management interface variable settings.

The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface. It

implements the network protocol stacks and performs the synchronous-to-isochronous

and isochronous-to-synchronous conversions. The network processor has a role in

sample clock regeneration and performs all interactions with the host system.

The sample clock is generated by a voltage-controlled crystal oscillator (VCXO)

controlled by the network processor. The VCXO frequency is carefully adjusted to achieve

lock with the network clock.

The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast

Ethernet standard. As per Ethernet requirements the interface is transformer isolated.

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Pinout and Signal Descriptions

4.0 Pinout and Signal Descriptions

This section details the chip pinout and signal interfaces for each module and is divided

as follows:

• "CS1810xx & CS4961xx Package Pinouts" on page 10

• "Host Port Signals" on page 12

• "Asynchronous Serial Port (UART Bridge) Signals" on page 12

• "Synchronous Serial (Audio) Signals" on page 13

• "Audio Clock Signals" on page 13

• "Miscellaneous Signals" on page 14

• "Power and Ground Signals" on page 14

• "System Signals" on page 15

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Pinout and Signal Descriptions

4.1 CS1810xx & CS4961xx Package Pinouts

4.1.1 CS1810xx/CS4961xx Pinout

Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces

for these signals are expanded in the following sections.

Table 1. CS1810xx/CS4961xx Pin Assignments

Pin #

Pin Name

Pin #

Pin Name

Pin #

Pin Name

Pin #

Pin Name

1

2

3

4

5

6

7

8

9

VCXO_CTRL

MCLK_SEL

DBDA

37

DATA1

73

VDDIO

109

HADDR1

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

WE

74

ADDR10

ADDR14

GND

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

HADDR0

HDATA7

HDATA6

VDDIO

HDATA5

HDATA4

GND

DATA0

DATA15

DATA14

DATA13

DATA12

VDDIO

DATA11

DATA10

GND

75

DBCK

76

NC

77

ADDR13

NC

78

NC

79

NC

DAO_MCLK

TEST

80

NC

81

NC

HDATA3

HDATA2

VDDD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VDDD

82

ADDR15

VDDD

ADDR16

ADDR17

GND

HS3

83

NC

DATA9

DATA8

NC

84

HDATA1

HDATA0

GND

85

DAO2_LRCLK

DAO1_DATA3

DAO1_DATA2/HS2

DAO1_DATA1/HS1

VDDIO

86

NC

87

ADDR18

ADDR19

OE

XTAL_OUT

XTO

NC

88

NC

89

XTI

VDDD

ADDR12

ADDR11

GND

90

CS1

GND_a

FILT2

DAO1_DATA0/HS0

DAO1_SCLK

GND

91

VDDIO

MUTE

HRESET

GND

92

FILT1

93

VDDA

DAO1_LRCLK

UART_TX_OE

VDDD

ADDR9

ADDR8

VDDIO

ADDR7

ADDR6

GND

94

VDDD

95

WATCHDOG

IOWAIT

REFCLK_IN

VDDD

GPIO0

GPIO1

GND

DAI1_DATA3

DAI1_DATA2

GND

96

UART_TXD

UART_RXD

GND

97

98

DAI1_DATA1

DAI1_DATA0

VDDIO

DAI1_SCLK

DAI1_LRCLK

GND

99

NC

ADDR5

CS2

100

101

102

103

104

105

106

107

108

DATA7

DATA6

VDDD

ADDR4

ADDR3

GND

HACK

DATA5

HDS

DATA4

HEN

HREQ

VDDIO

HADDR3

HADDR2

HR/W

NC

DATA3

ADDR2

ADDR1

ADDR0

NC

DATA2

IRQ1

GND

GPIO2

IRQ2

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CobraNet Hardware User’s Manual

Pinout and Signal Descriptions

4.1.2 CM-2 Connector Pinout

Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The

interfaces for these signals are expanded following the table.

Table 2. CM-2 Pin Assignments

Conn.

Pin #

Pin Name

Conn.

Pin #

Pin Name

Conn.

Pin #

Pin Name

J1/J2

A1

UART_RXD

J1/J2

J3/J4

B8

GND

J3/J4

A15

DAI1_DATA3

RSVD3

A2

UART_TX_OE

HACK

B9

VCC_+3.3V

GND

A16

A17

A18

A19

A20

B1

A3

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

A1

WATCHDOG

RSVD4

A4

HR/W

VCC_+3.3V

GND

A5

HDS

AUX_POWER2

AUX_POWER0

GND

A6

HREQ

VCC_+3.3V

GND

A7

HEN

A8

HADDR0

HADDR1

HADDR2

HDATA0

HDATA1

HDATA2

HDATA3

HDATA4

HDATA5

HDATA6

HRESET

HDATA7

HADDR3

UART_TXD

GND

VCC_+3.3V

GND

B2

VCC_+3.3V

GND

A9

B3

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

VCC_+3.3V

RSVD1

B4

VCC_+3.3V

GND

B5

GND

B6

VCC_+3.3V

GND

VCC_+3.3V

RSVD2

B7

B8

VCC_+3.3V

GND

A2

MUTE

B9

A3

FS1

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

VCC_+3.3V

GND

A4

MCLK_OUT

MCLK_IN

REFCLK_IN

DAO1_SCLK/DAI1_SCLK

DAO1_DATA0

DAO1_DATA1

DAO1_DATA2

DAO1_DATA3

DAI1_DATA0

DAI1_DATA1

DAI1_DATA2

A5

VCC_+3.3V

GND

A6

A7

VCC_+3.3V

GND

A8

B2

A9

GND

B3

VCC_+3.3V

GND

A10

A11

A12

A13

A14

VCC_+5V

AUX_POWER3

AUX_POWER1

B4

B5

VCC_+3.3V

GND

B6

B7

VCC_+3.3V

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Pinout and Signal Descriptions

4.2 Signal Descriptions

4.2.1 Host Port Signals

The host port is used to manage and monitor the CobraNet interface. Electrical operation

and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this

Manual.

The host port can operate in two modes in order to accomodate Motorola^®or Intel^®style

interfaces. The default mode is Motorola. Intel mode is set via a firmware modification.

Table 2-1: Host Port Signals

CM-2

Pin #

CS1810xx/

CS4961xx Pin #

Signal

Description Direction

Notes

111, 112, 114,

115, 117, 118,

102, 121

J1:A19,

A[17:11]

HDATA[7:0]

Host Data

In/Out

Host port data.

J1:A20,

A[10:8]

HADDR[3:0] Host Address

In

105, 106, 109,110 Host port address.

Host

HRW

J1:A4

107

Host port transfer direction (Motorola mode).

Direction

HRD

HREQ

HACK

HDS

Host Read

Host Request

Host Alert

Host Strobe

Host Write

Host Enable

Select

In

Out

In

J1:A4

J1:A6

J1:A3

J1:A5

J1:A7

107

140

102

103

104

Host Read (Intel mode).

Host port data request.

Host port interrupt request.

Host port strobe (Motorola mode).

Host Write (Intel mode).

Host Port Enable.

HWR

HEN

In

HCS

In

Select (Intel mode).

4.2.2 Asynchronous Serial Port (UART Bridge) Signals

Level-shifting drive circuits are typically required between these signals and any external

connections.

CM-2

Pin #

CS1810xx/

CS4961xx Pin #

Signal

Description

Direction

Notes

Asynchronous Serial

Receive Data

UART_RXD

UART_TXD

In

J1:A1

J1:B1

J1:A2

26

25

23

Pull-up to VCC if unused.

Asynchronous Serial

Transmit Data

Out

Enable transmit (active high) drive for

two wire multi-drop interface.

UART_TX_OE

Transmit Drive Enable

12

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Pinout and Signal Descriptions

4.2.3 Synchronous Serial (Audio) Signals

The synchronous serial interfaces are used to bring digital audio into and out of the

system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing

and format is described in "Digital Audio Interface" on page 19.

CM-2

Pin #

CS1810xx/

CS4961xx Pin #

Signal

Description

Direction

Notes

Synchronous serial bit clock.

64 FS for CS18100x & CS49610x (2x1 channel)

64 FS for CS18101x & CS49611x (2x4

channels)

DAO1_SCLK

Audio Bit Clock

Out

J3:A7

20

128 FS for CS18102x & CS49612x (4x4

channels)

Typically tied to DAI1_SCLK.

Output synchronous serial audio data

DAO1_DATA[3:1] not used for CS18100x &

CS49610x.

Audio Output

Data

J3:A18,

B18

DAO1_DATA[3:0]

Out

15-17, 19

Input synchronous serial audio data

131, 132, 134, 135 DAI1_DATA[3:1] not used for CS18100x &

CS49610x.

J3:

A[15:12]

DAI1_DATA[3:0]

DAI1_SCLK

Audio Input Data

Audio Bit Clock

In

Should be tied to DAO1_SCLK.

Synchronous serial bit clock.

J4:A7

137

4.2.4 Audio Clock Signals

See "Synchronization" on page 17 for an overview of synchronization modes and issues.

CM-2

Pin #

CS1810xx/

CS4961xx Pin #

Signal

Description

Direction

Notes

Sample clock

input

DAI1_LRCLK

In

138

22

Should be tied to DAO1_LRCLK for all devices.

DAO1_LRCLK

(FS1)

Sample clock

output

FS1 (word clock) for CS18100x/CS49610x and

CS18101x/CS49611x.

Out

J3:A3

DAO2_LRCLK

(FS1)

Sample clock

output

14

FS1 (word clock) for CS18102x & CS49612x.

Clock input for synchronizing network to an

external clock source, for redundancy control

and synchronization of FS divider chain to

external source. See "Synchronization" on

page 17 for more detail.

REFCLK_IN

Reference clock

In

J3:A6

97

For systems featuring multiple CobraNet

interfaces operating off a common master

clock. See "Synchronization" on page 17 for

more detail.

Master audio

clock input

MCLK_IN

In

J3:A5

J3:A4

8*

Master audio

clock output

MCLK_OUT

Out

Low jitter 24.576 MHz master audio clock.

*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out

implementation.

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Pinout and Signal Descriptions

4.2.5 Miscellaneous Signals

CM-2

Pin #

CS1810xx/

CS4961xx Pin #

Signal

Description Direction

Notes

System reset (active low).

HRESET

Reset

In

J1:A18

93

95

92

10 ns max rise time. 1 ms min assertion time.

Toggles at 750 Hz nominal rate to indicate proper

operation. Period duration in excess of 200 ms

indicates hardware or software failure has occurred

and the interface should be reset. Note that

improper operation can also be indicated by short

pulses (<100 ns).

WATCHDOG

Watch Dog

Out

J3:A17

Interface

Ready

Asserts (active low) during initialization and when a

fault is detected or connection to the network is lost.

MUTE

NC

Out

-

J3:A2

-

28, 50-53, 78-

81, 141, 142

No Connect

4.2.6 Power and Ground Signals

CS1810xx/CS4961xx

Signal

Description

CM-2 Pin #

Specification

Pin #

J1:B20, B17, B15,

B13, B11, B9, B7,

B5, B3

System Digital +3.3 v

N/A

VCC_+3V

3.3 0.3v, 500 mA Typ., 750 mA Max.

J3:B14, B12, B10,

B8, B6, B4, B2

J3;B[18:17]

N/A

Backwards Compatibility

^VCC_+5V

10, 24, 54, 66, 83,

98, 119, 130

VDDD

+1.8 V @ 500mA Typ. for Core Logic

18, 33, 44, 60, 73,

91, 113, 136

VDDIO

VDDA

N/A

+3.3 V @ 120mA Typ. for I/O Logic

Filtered +1.8 V @ 10mA Typ.

129

N/A

AUX_POWER

[3-0]

J3:B[20:19],

A[20:19]

J1:B19, B16, B14,

B12, B10, B8, B6,

B4, B2

13, 21, 27, 36, 47,

57, 63, 69, 76, 86,

94, 101, 116, 122,

126, 133, 139

GND

Digital Ground

J3:B16, B15, B13,

B11, B9, B7, B5,

B3, B1

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Pinout and Signal Descriptions

4.2.7 System Signals

Use these CS1810xx/CS4961xx signals stricktly in the manner described in CM-2

Schematics (Section 9.2 on page 44). Each signal is briefly described below.

CS1810xx/CS4961xx

Signal

Description

Pin #

VCXO_CTRL

MCLK_SEL

A Delta-sigma DAC Output for Controlling the On-board VCXO

Control Signal for Selecting MCLK Sources

I2C Debugger Interface

1

2

DBDA, DBCK

3, 4

Used for testing during manufacturing. Keep grounded for normal

operation.

TEST

9

29-32, 34, 35, 37, 39-43,

45, 46, 48, 49

DATA[15:0]

Data Bus for Flash & Ethernet Controller(s)

Address Bus for Flash & Ethernet Controller(s)

55, 56, 58, 59, 61, 62, 64,

67, 68, 70-72, 74, 75, 77,

82, 84, 85, 87, 88

ADDR[19:0]

WE

CS1

Write Enable for Flash and Ethernet Controller(s)

Chip Select for Flash Memory Device

Chip Select for Ethernet Controller(s)

Output Enable

38

90

CS2

65

OE

89

IOWAIT

GPIO[2:0]

XTI

Wait State Signal from Ethernet Controller(s)

General-purpose I/O Signals

Reference Clock Input / Crystal Oscillator Input

Crystal Oscillator Output

96

99, 100, 108

125

XTO

124

XTAL_OUT

FILT2, FILT1

DAO_MCLK

HS[3:0]

A Buffered Version of XTI

123

PLL Loop Filter

127, 128

8

MCLK Input

CS1810xx/CS4961xx Boot Mode Selection

11, 16, 17, 19

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Pinout and Signal Descriptions

4.3 Characteristics and Specifications

4.3.1 Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

DC power supplies:

Core supply

PLL supply

I/O supply

VDD

VDDA

VDDIO

–0.3

-

2.0

5.0

0.3

V

|VDDA – VDD|

Input current, any pin except supplies

Input voltage on FILT1, FILT2

Input voltage on I/O pins

I

-

+/- 10

2.0

5.0

mA

V

in

V

filt

V

-

inio

Storage temperature

T

–65

150

°C

stg

Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

4.3.2 Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

DC power supplies:

Core supply

PLL supply

I/O supply

VDD

VDDA

VDDIO

1.71

3.13

1.8

3.3

1.89

3.46

0.3

V

|VDDA – VDD|

Ambient operating temperature

T

-

°C

A

- CQ

- DQ

0

- 40

+ 70

+ 85

4.3.3 Digital DC Characteristics

(measurements performed under static conditions.)

Parameter

High-level input voltage

Symbol

Min

2.0

Typ

-

Max

-

Unit

V

IH

Low-level input voltage, except XTI

Low-level input voltage, XTI

Input Hysteresis

V

-

0.8

0.6

V

IL

V

ILXTI

V

0.3

-

V

hys

OH

High-level output voltage at

VDDIO * 0.9

-

I = –8.0 mA = –16.0 mA

O

Low-level output voltage at

I = 8.0 mA = –16.0 mA

V

-

VDDIO * 0.1

V

OL

IN

O

Input leakage current (all pins without internal pull-

up resistors except XTI)

Input leakage current (pins with internal pull-up

resistors, XTI)

I

5

µA

I

50

IN-PU

4.3.4 Power Supply Characteristics

(measurements performed under operating conditions))

Parameter

Min

Typ

Max

Unit

Power supply current:

Core and I/O operating: VDD

PLL operating: VDDA

With external memory and most ports operating: VDDIO

(Note 1)

-

500

10

120

-

mA

NOTES:1. Dependent on application firmware and DSP clock speed.

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Synchronization

5.0 Synchronization

Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design

(CM-2). This circuitry allows the synchronization modes documented below to be

achieved. Modes are distinguished by different settings of the multiplexors and software

elements.

MCLK_OUT

VCXO

24.576 MHz

CS1810xx/CS4961xx

DAC

AClkConfig

FS1

Audio

Clock

Generator

SLCK

MCLK_IN

Sample

Phase

Counter

MCLK_SEL

Phase

Detector

Loop

Filter

RefClkEnable

RefClkPolarity

Edge

Detect

REFCLK_IN

BeatReceived

Legend:

External

Internal

Hardware

Component

(CM2)

Hardware

Component

(CS1810xx, CS4961xx)

Software

Component

Figure 3. Audio Clock Sub-system

5.1 Synchronization Modes

Clock synchronization mode for conductor and performer roles is independently

selectable via management interface variables syncConductorClock and

syncPerformerClock. The role (conductor or performer) is determined by the network

environment including the conductor priority setting of the device and the other devices on

the network. It is possible to ensure you will never assume the conductor role by selecting

a conductor priority of zero. However, it is not reasonable to assume that by setting a high

conductor priority, you will always assume the conductor role. For more information, refer

to CobraNet Programmer’s Reference Manual.

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Synchronization

The following synchronization modes are further described below:

• "Internal Mode" on page 18

• "External Word Clock Mode" on page 18

• "External Master Clock Mode" on page 18

5.1.1 Internal Mode

All CobraNet clocks are derived from the onboard VCXO. The master clock generated by

the VCXO is available to external circuits via the master clock output.

Conductor—The VCXO is “parked” according to the syncClockTrim setting.

Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.

5.1.2 External Word Clock Mode

All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an

external clock supplied to the reference clock input. The clock supplied can be any

integral division of the sample clock in the range of 750Hz to 48kHz.

External synchronization lock range: 5 µs. This specification indicates drift or wander

between the supplied clock and the generated network clock at the conductor. Absolute

phase difference between the supplied reference clock and generated sample clock is

dependant on network topology.

Conductor—This mode gives a means for synchronizing an entire CobraNet network to

an external clock.

Performer—The interface disregards the fine timing information delivered over the

network from the conductor. Coarse timing information from the conductor is still used;

fine timing information is instead supplied by the reference clock. The external clock

source must be synchronous with the network conductor. This mode is useful in

installations where a house sync source is readily available.

5.1.3 External Master Clock Mode

The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a

“hard” synchronization mode. The supplied clock is used directly by the CobraNet

interface for all timing. This mode is primarily useful for devices with multiple CobraNet

interfaces sharing a common master audio clock. The supplied clock must be

24.576 MHz. The supplied clock must have a 37 ppm precision.

Conductor—The entire network is synchronized to the supplied master clock.

Performer—The node will initially lock to the network clock and will “jam sync” via the

supplied master clock. The external clock source must be synchronous with the network

conductor.

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Digital Audio Interface

6.0 Digital Audio Interface

The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional

synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional

synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as

the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial

data includes two (or four) audio channels. CobraNet supports two synchronous serial bit

rates: 48 Khz and 96 KHz. However, 96 kHz sample rate is not available when using

CS18102x/CS49612x with 16X16 channels. Bit rate is selected by the modeRateControl

variable. All synchronous serial interfaces operate from a common clock at the same bit

rate.

FS1

DAO 1_DATA0 / DAI1_DATA0

*DAO 1_DATA1 / DAI1_DATA1

*DAO 1_DATA2 / DAI1_DATA2

*DAO 1_DATA3 / DAI1_DATA3

* Not present in CS18100x or CS49610x.

1

3

5

7

2

4

6

8

Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x &

CS18101x/CS49611x

FS1

DAO1_DATA0 / DAI1_DATA0

DAO1_DATA1 / DAI1_DATA1

DAO1_DATA2 / DAI1_DATA2

DAO1_DATA3 / DAI1_DATA3

1

5

2

6

3

7

4

8

9

10

14

11

15

12

16

13

Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x

Default channel ordering is shown above. Note that the first channel always begins after

the rising or falling edge of FS1 (depending on the mode).

DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are

received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are

transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant

(sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits

15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic

recommends driving unused LS bits to zero.

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Digital Audio Interface

Although data is always transmitted and received with a 32-bit resolution by the

synchronous serial ports, the resolution of the data transferred to/from the Ethernet may

be less. Incoming audio data is truncated to the selected resolution. Unused least

significant bits on outgoing data is zero filled.

6.1 Digital Audio Interface Timing

0 – 5ns

MCLK_OUT

DAO1_SCLK

FS1

0 – 10ns

Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1

An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows

a MCLK_OUT edge by 0.0 to 10.0ns.

Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or

the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends

on power up timing.

≥5ns

≥0ns

DAO1_SCLK

DAI1_DATAx

DAO1_DATAx

0 – 12ns

Figure 7. Serial Port Data Timing Overview

Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to

the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the

edge of DAO1_SCLK.

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Digital Audio Interface

6.1.1 Normal Mode Data Timing

DAI1_SCLK

FS1

DAI1_DATAx

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23

DAO1_DATAx

Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

DAI1_SCLK

FS1

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23

DAI1_DATAx

DAO1_DATAx

Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The

figure above shows 24-bit audio data.

The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of

DAI_SCLK and data changes on the falling edge.

2

6.1.2 I S Mode Data Timing

DAI1_SCLK

FS1

DAI1_DATAx

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23

DAO1_DATAx

Figure 10. Audio Data Timing Detail - I²S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

DAI1_SCLK

FS1

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23

DAI1_DATAx

DAO1_DATAx

Figure 11. Audio Data Timing Detail - I²S Mode, 128FS - CS18102x & CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The

figure above shows 24-bit audio data.

The MSB is left justified and arrives one bit period following FS1. Data is sampled on the

rising edge of DAI_SCLK and data changes on the falling edge.

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Digital Audio Interface

6.1.3 Standard Mode Data Timing

DAI1_SCLK

FS1

DAI1_DATAx

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23

DAO1_DATAx

Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x

DAI1_SCLK

FS1

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

8

7

6

5

4

3

2

1

0

Unused

23

DAI1_DATAx

DAO1_DATAx

Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102x/CS49612x

Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The

figure above shows 24-bit audio data.

The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of

DAI_SCLK and data changes on the falling edge.

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Host Management Interface (HMI)

7.0 Host Management Interface (HMI)

7.1 Hardware

The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers

are implemented. The upper two registers can be used to configure and retrieve the

status on the host port hardware. However, only the first 8 are essential for normal HMI

communications. It is therefore feasible, in most applications, to utilize only the first 3

address bits and tie the most significant bit (A3) low.

Host port hardware supports Intel^®(little-endian), Motorola^®, and Motorola multiplexed

bus (big-endian) protocols. Standard CobraNet firmware configures the port in the

Motorola, big-endian mode.

The host port memory map is shown in Table 3. Refer also to "HMI Definitions" on

page 33 and "HMI Access Code" on page 34.

Host Address

Register

0

1

2

3

4

5

6

7

8

9

Message A (MS)

Message B

Message C

Message D (LS)

Data A (MS)

Data B

Data C

Data D (LS)

Control

Status

Table 3. Host port memory map

The message and data registers provide separate bi-directional data conduits between

the host processor and the CS1810xx/CS4961xx. A 32-bit word of data is transferred to

the CS1810xx/CS4961xx when the host writes the D message or data register after

presumably previously writing the A, B, and C registers with valid data. Data is transferred

from the CS1810xx/CS4961xx following a read of the D message or data register. Again,

presumably the A, B, and C registers are read previously.

Two additional hardware signals are associated with the host port: HACK and HREQ.

Both are outputs to the host.

HACK may be wired to an interrupt request input on the host. HACK can be made to

assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is

deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see “Messages”

below).

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Host Management Interface (HMI)

HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the

host that data is available (read case, logic 0) or space is available in the host port data

channel (write case, logic 1).

The read and write case are distinguished by the HMI based on the preceding message.

Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to

represent read status. Goto Translation (write) and Goto Packet (write) switch HREQ to

write mode. All other commands have no effect on HREQ operation.

In general, the host can read from the CS1810xx/CS4961xx when HREQ is low and can

write data to CS1810xx/CS4961xx when HREQ is high.

7.2 Host Port Timing - Motorola^®Mode

(C = 20 pF)

L

Parameter

Symbol

Min

5

Max

Unit

ns

Address setup before HEN and HDS low

Address hold time after HEN and HDS low

Read

t

-

mas

mah

t

5

ns

Delay between HDS then HEN low or HEN then HDS low

Data valid after HEN and HDS low with HRW high

HEN and HDS low for read

t

0

-

19

-

ns

mcdr

t

mdd

t

24

8

mrpw

Data hold time after HEN or HDS high after read

Data high-Z after HEN or HDS high after read

HEN or HDS high to HEN and HDS low for next read

HEN or HDS high to HEN and HDS low for next write

t

-

mdhr

t

-

18

-

mdis

t

30

-

mrd

t

-

mrdtw

t

12

HR/W rising to HREQ falling

mrwirqh

Write

Delay between HDS then HEN low or HEN then HDS low

Data setup before HEN or HDS high

HEN and HDS low for write

t

0

8

-

ns

mcdw

t

mdsu

t

24

8

mwpw

mrwsu

HRW setup before HEN and HDS low

HRW hold time after HEN or HDS high

Data hold after HEN or HDS high

t

mrwhld

t

8

mdhw

HEN or HDS high to HEN and HDS low with HRW high for

next read

t

30

mwtrd

HEN or HDS high to HEN and HDS low for next write

t

30

-

ns

mwd

t

-

12

ns

HRW rising to HREQ falling

mrwbsyl

NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may

be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed

to prevent overflowing the input data buffer.

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Host Management Interface (HMI)

HADDR[3:0]

HDATA[7:0]

HEN

t _mas

t_{m ah}

LSP

t _mdhr

MSP

t _mdd

t _mrwsu

t _mcdr

t _mdis

t_{m rwhld}

HRW

t_mrdtw

t _{m rpw}

t_{m rd}

HDS

t_mrwirqh

HREQ

Figure 14. Host Port Read Cycle Timing - Motorola Mode

HADDR[3:0]

t_{m as}

t_{m ah}

LSP

t _mdsu

MSP

HDATA[7:0]

HEN

t _{m dhw}

t _{m rw hld}

t _{m wpw}

t _{m cdw}

HRW

t _{m rw su}

t_{m w d}

t _{m w trd}

HDS

t_{m rwirql}

HREQ

Figure 15. Host Port Write Cycle Timing - Motorola Mode

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Host Management Interface (HMI)

7.3 Host Port Timing - Intel^®Mode

(C = 20 pF)

L

Parameter

Symbol

Min

Max

Unit

Address setup before HCS and HRD low or HCS and HWR

low

t

5

-

ns

ias

Address hold time after HCS and HRD low or HCS and HWR

high

t

5

-

ns

iah

Read

Delay between HRD then HCS low or HCS then HRD low

Data valid after HCS and HRD low

t

0

-

18

-

ns

icdr

t

idd

HCS and HRD low for read

t

24

8

irpw

Data hold time after HCS or HRD high

Data high-Z after HCS or HRD high

t

-

idhr

t

-

18

-

idis

HCS or HRD high to HCS and HRD low for next read

HCS or HRD high to HCS and HWR low for next write

t

30

-

ird

t

-

irdtw

t

12

HRD rising to HREQ rising

irdirqhl

Write

Delay between HWR then HCS low or HCS then HWR low

Data setup before HCS or HWR high

HCS and HWR low for write

t

0

8

-

ns

icdw

t

idsu

t

24

8

-

iwpw

Data hold after HCS or HWR high

HCS or HWR high to HCS and HRD low for next read

HCS or HWR high to HCS and HWR low for next write

t

-

idhw

iwtrd

t

30

-

t

-

iwd

t

12

HWR rising to HREQ falling

iwrbsyl

NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may

be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed

to prevent overflowing the input data buffer.

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Host Management Interface (HMI)

HADDR[3:0]

HDATA[7:0]

HCS

t_iah

LSP

t _idhr

MSP

t _ias

t _idd

t _icdr

t _idis

HW R

t _irpw

t _ird

t _irdtw

HRD

t_irdirqh

HREQ

Figure 16. Parallal Control Port - Intel Mode Read Cycle

HADDR[3:0]

HDATA[7:0]

HCS

t _iah

LSP

MSP

t _ias

t_idhw

t_icdw

t _idsu

HRD

t _iwpw

t_iwd

t _iwtrd

HW R

t_iwrbsyl

HREQ

Figure 17. Parallel Control Port - Intel Mode Write Cycle

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Host Management Interface (HMI)

7.4 Protocol and Messages

The message conduit is used to issue commands to the CS1810xx/CS4961xx and

retrieve HMI status. The data conduit is used to transfer data dependent on the HMI state

as determined by commands issued by the host via the message conduit.

7.4.1 Messages

Messages are used to efficiently invoke action in the CS1810xx/CS4961xx. To send a

message, the host optionally writes to the A, B, and C registers. Writing to the D register

transmits the message to the CS1810xx/CS4961xx. A listing of all HMI messages is

shown in Table 4. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on

page 34.

DRQ Handshake

Message

A

B

C

D

Mode

Translate Address

Acknowledge Interrupt

Identify

n/c

Address (MS)

Address

n/c

Address (LS)

0xB3

0xB4

0xB5

n/c

7

read

n/c

Goto Packet Transmit

Buffer

write

n/c

6

5

4

0xB5

Goto Translation

Acknowledge Packet

Receipt

Transmit Packet

Goto Counters

n/c

3

2

0xB5

read

Goto Packet Receive

Buffer

read

n/c

1

0

0xB5

Goto Translation

Table 4. HMI messages

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Host Management Interface (HMI)

7.4.1.1. Translate Address

Translate Address does not actually update the address pointers but initiates the

processing required to eventually move them. The host can accomplish other tasks,

including HMI Reads and Writes while the address translation is being processed. A

logical description of Translate Address is given below. A contextual use of the Translate

Address operation is shown in the reference implementations. Refer also to "HMI

Definitions" on page 33 and "HMI Access Code" on page 34.

void TranslateAddress(

long address )

{

int msgack = MSG_D;

MSG_A = ( address & 0xff0000 ) >> 16;

MSG_B = ( address & 0xff00 ) >> 8;

MSG_C = address & 0xff;

MSG_D = CVR_TRANSLATE_ADDRESS;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

7.4.1.2. Interrupt Acknowledge

Causes HACK to be de-asserted.

void InterruptAck( void )

{

int msgack = MSG_D;

MSG_D = CVR_INTERRUPT_ACK;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

7.4.1.3. Goto Packet

Moves HMI pointers to bridgeRxPktBuffer (write = 0) or bridgeTxPktBuffer (write = 1).

void GotoPacket(

bool write )

{

int msgack = MSG_D;

MSG_C = write ? MOP_GOTO_PACKET_TRANSMIT : MOP_GOTO_PACKET_RECEIVE;

MSG_D = CVR_MULTIPLEX_OP;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

7.4.1.4. Goto Translation

Moves HMI data pointers to the results of the most recently completed translate address

operation. The write parameter dictates the operation of the HREQ signal and only needs

to be supplied for applications using hardware data handshaking via this signal.

void GotoTranslation(

bool write = 0 )

{

int msgack = MSG_D;

MSG_C = write ? MOP_GOTO_TRANSLATION_WRITE : MOP_GOTO_TRANSLATION_READ;

MSG_D = CVR_MULTIPLEX_OP;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

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7.4.1.5. Packet Received

Sets bridgeRxPkt = bridgeRxReady thus acknowledging receipt of the packet in

bridgeRxPktBuffer.

void PacketReceive( void )

{

int msgack = MSG_D;

MSG_C = MOP_PACKET_RECEIVE;

MSG_D = CVR_MULTIPLEX_OP;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

7.4.1.6. Packet Transmit

Sets bridgeTxPkt = bridgeTxPktDone+1 thus initiating transmission of the contents of

bridgeTxPktBuffer. Presumably bridgeTxPktBuffer has been previously written with valid

packet data.

void PacketTransmit( void )

{

int msgack = MSG_D;

MSG_C = MOP_PACKET_TRANSMIT;

MSG_D = CVR_MULTIPLEX_OP;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

7.4.1.7. Goto Counters

Moves HMI data pointers to interrupt status variables (beginning at hackStatus).

void GotoCounters( void )

{

int msgack = MSG_D;

MSG_C = MOP_GOTO_COUNTERS;

MSG_D = CVR_MULTIPLEX_OP;

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

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Host Management Interface (HMI)

7.4.2 Status

HMI status can always be retrieved by reading the message conduit. Status is updated in

a pipelined manner whenever the Message D register is read. Reading the message

conduit gives the current status as of the last time the conduit was read. Bitfields in the

HMI Status Register are outlined in Table 5 below. Refer also to "HMI Definitions" on

page 33 and "HMI Access Code" on page 34.

Status

Bit(s)

Reserved

[31:24]

Region Length

Reserved

[23:8]

[7:5]

Writable Region

4

3

2

1

0

Translation Complete

Packet Transmission Complete

Received Packet Available

Message Togglebit

Table 5. HMI status bits

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Host Management Interface (HMI)

7.4.3 Data

Before accessing data, address setup must be performed. Address setup consists of

issuing a Translate Address request, waiting for the request to complete, then issuing a

Goto Translation.

Pipelining requires that a “garbage read” be performed following an address change. The

second word read contains the data for the address requested. No similar pipelining issue

exists with respect to write operations.

7.4.3.1. Region length

Distance from the original pointer position (as per Translate Address) to the end of the

instantiated region. A value of 0 indicates an invalid pointer.

7.4.3.2. Writable Region

When set, this bit indicates the address pointer is positioned within a writable region. MI

variables may be modified in a writable region by writing data to the data conduit.

7.4.3.3. Translation Complete

When set, this bit indicates that the address translator is available (translation results are

available and a new translation request may be submitted). This bit is cleared when a

Translate Address message is issued and is set when the translation completes.

7.4.3.4. Packet Transmission Complete

This bit is cleared when transmission is initiated by issuance of the Transmit Packet

message. The bit is set when the packet has been transmitted and the transmit buffer is

ready to accept a new packet.

7.4.3.5. Received Packet Available

This bit is set when a packet is received into the packet bridge. It is cleared when the

packet data is read and receipt is acknowledged by issuance of an Acknowledge Packet

Receipt message. Note that Received Packet Available only goes low when there are no

longer any pending received packets for the packet bridge. The packet bridge has the

capacity to queue multiple packets in the receive direction.

7.4.3.6. Message Togglebit

This bit toggles on completion of processing of each message. A safe means for the host

to acknowledge processing of messages is as follows:

void WaitToggle( void )

{

int msgack = MSG_D; /* clean pipeline */

msgack = MSG_D; /* record current state of togglebit */

MSG_D = YOUR_COMMAND_HERE; /* issue command */

/* wait for togglebit to flip */

while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

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HMI Reference Code

8.0 HMI Reference Code

The following C code provides examples in using HMI messages, HMI status, and the

HMI memory map.

8.1 HMI Definitions

/*========================================================================

** hmi.h

** CobraNet Host Management Interface example code

** Definitions

**------------------------------------------------------------------------

** $Header$

**========================================================================*/

#define MSG_A 0

#define MSG_B 1

#define MSG_C 2

#define MSG_D 3

#define DATA_A 4

#define DATA_B 5

#define DATA_C 6

#define DATA_D 7

#define CONTROL 8

#define STATUS 9

#define CVR_SET_ADDRESS 0xb2

/* Not availbale on CS1810xx/CS4961xx/CM-2. */

/*CM-1 and Reference Design only. */

#define CVR_TRANSLATE_ADDRESS 0xb3

#define CVR_INTERRUPT_ACK 0xb4

#define CVR_MULTIPLEX_OP 0xb5

#define MOP_GOTO_TRANSLATION_READ 0

#define MOP_GOTO_TRANSLATION_WRITE 5

#define MOP_GOTO_PACKET_RECEIVE 1

#define MOP_GOTO_PACKET_TRANSMIT 6

#define MOP_GOTO_COUNTERS 2

#define MOP_PACKET_TRANSMIT 3

#define MOP_PACKET_RECEIPT 4

#define MOP_IDENTIFY 7

#define MSG_TOGGLE_BO 0

#define MSG_RXPACKET_BO 1

#define MSG_TXPACKET_BO 2

#define MSG_TRANSLATION_BO 3

#define MSG_WRITABLE_BO 4

#define MSG_LENGTH_BO 8

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8.2 HMI Access Code

/*========================================================================

** hmi.c

** CobraNet Host Management Interface example code

** Simple edition

**------------------------------------------------------------------------

** $Header$

**========================================================================*/

#include "hmi.h"

/* variables model HMI state */

long PeekLimit;

long PeekPointer = -1;

long PokeLimit;

long PokePointer = -1;

/* access host port hardware */

#define HMI_BASE 0

unsigned char ReadRegister(

int hmiregister )

{

return *(unsigned char volatile *const) ( hmiregister + HMI_BASE );

}

void WriteRegister(

int hmiregister,

unsigned char value )

{

*(unsigned char volatile *const) ( hmiregister + HMI_BASE ) = value;

}

void SendMessage(

unsigned char message )

{

int msgack = ReadRegister( MSG_D );

/* issue (last byte of) message */

WriteRegister( MSG_D, message );

/* wait for acceptance of message */

while( !( ( msgack ^ ReadRegister( MSG_D ) ) & ( 1 << MSG_TOGGLE_BO ) ) );

}

void SetAddress(

long address )

{

/* translate address */

WriteRegister( MSG_A, ( address & 0xff0000 ) >> 16 );

WriteRegister( MSG_B, ( address & 0xff00 ) >> 8 );

WriteRegister( MSG_C, address & 0xff );

SendMessage( CVR_TRANSLATE_ADDRESS );

/* wait for completion of translate address */

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while( !( ReadRegister( MSG_D ) & ( 1 << MSG_TRANSLATION_BO ) ) );

/* goto translation */

WriteRegister( MSG_C, MOP_GOTO_TRANSLATION_READ );

SendMessage( CVR_MULTIPLEX_OP );

/* "garbage" read clears data pipeline */

ReadRegister( DATA_D );

/* maintain local pointers */

PeekPointer = PokePointer = address;

PeekLimit = PokeLimit = PeekPointer +

ReadRegister( MSG_C ) + ( ReadRegister( MSG_B ) << 8 );

/* read-only region addressed */

if( !( ReadRegister( MSG_A ) & ( 1 << MSG_WRITABLE_BO ) ) ) {

PokeLimit = PokePointer;

}

unsigned long Peek(

long address )

{

if( address != PeekPointer ) {

SetAddress( address );

}

if( PeekPointer >= PeekLimit ) {

throw "Peek addressing error!";

}

unsigned long value = ReadRegister( DATA_A ) << 24;

value += ReadRegister( DATA_B ) << 16;

value += ReadRegister( DATA_C ) << 8;

value += ReadRegister( DATA_D );

PeekPointer++; /* maintain local pointer */

return value;

}

void Poke(

long address,

unsigned long value )

{

if( address != PokePointer ) {

SetAddress( address );

}

if( PokePointer >= PokeLimit ) {

throw "Poke addressing error or read-only!";

}

WriteRegister( DATA_A, (unsigned char) ( ( value >> 24 ) & 0xff ) );

WriteRegister( DATA_B, (unsigned char) ( ( value >> 16 ) & 0xff ) );

WriteRegister( DATA_C, (unsigned char) ( ( value >> 8 ) & 0xff ) );

WriteRegister( DATA_D, (unsigned char) ( value & 0xff ) );

/* maintain local pointers */

PokePointer++;

PeekPointer = -1; /* force SetAddress()next Peek() to freshen data */

}

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8.3 CM-1, CM-2 Auto-detection

The following function is useful for systems that support both the CM-1 and CM-2 or

where a CobraNet interface is an optional add-in.

Detect() returns 0 if no CobraNet interface module is detected, 1 for CM-1 and 2 for CM-2.

int Detect( void ) {

/* check for presence of CM-1 */

MSG_B = 0x55; /* write to CM-1 CVR register */

DATA_A = 0xaa; /* write to unused CM-1 register to flip data bus */

if( MSG_B == 0x55 ) { /* read back CVR */

/* redo same detection with different data */

MSG_B = 0x3c;

DATA_A = 0xc3;

if( MSG_B == 0x3c ) {

return 1; /* CM-1 detected */

}

/* check for presence of CM-2 */

/* issue identify command */

MSG_C = MOP_IDENTIFY;

MSG_D = CVR_MULTIPLEX_OP;

int msgack = MSG_D; /* clean pipeline */

msgack = MSG_D;

/* wait for togglebit to flip in response to command */

int tm0 = gettimeofday();

while( !( ( MSG_D ^ toggle ) & ( 1 << MSG_TOGGLE_BO ) ) ) {

int tm1 = gettimeofday();

if( ( tm1 - tm0 ) > time_out ) {

return 0; /* command timed out, no CobraNet interface present */

}

int garbage = MSG_D; /* clean pipeline */

/* verify identify results */

if( DATA_A == 'C' ) if( DATA_B == 'S' )

if( DATA_C == ( 18101 >> 8 ) ) if( DATA_D == ( 18101&0xff ) {

return 2; /* CM-2 detected */

}

return 0; /* no interface or non-supported interface */

}

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Mechanical Drawings and Schematics

9.0 Mechanical Drawings and Schematics

The section contains detailed drawings of the CM-2 board and CS1810xx/CS4961xx

device package design. The mechanical drawings are arranged as follows:

• "CM-2 Module Assembly Drawing, Top" on page 38

• "General PCB Dimensions" on page 40

• "Example Configuration, Side View" on page 41

• "Faceplate Dimensions" on page 42

• "Connector Detail" on page 43

• "CM-2 RevF Schematic Page 1 of 7" on page 44

• "CM-2 RevF Schematic Page 2 of 7" on page 45

• "CM-2 RevF Schematic Page 3 of 7" on page 46

• "CM-2 RevF Schematic Page 4 of 7" on page 47

• "CM-2 RevF Schematic Page 5 of 7" on page 48

• "CM-2 RevF Schematic Page 6 of 7" on page 49

• "CM-2 RevF Schematic Page 7 of 7" on page 50

• "144-Pin LQFP Package Drawing" on page 51

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9.1 CM-2 Mechanical Drawings

Figure 18. CM-2 Module Assembly Drawing, Top

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Figure 19. CM-2 Module Assembly Drawing, Bottom

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3 . 5 0 0

0 . 1 7 5

B 2 0

A 2 0

B 1

A 1

B 2 0

A 2 0

B 1

A 1

Figure 20. General PCB Dimensions

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Figure 21. Example Configuration, Side View

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0 . 8 6 2

1 . 0 0 0

1 . 0 0 0 m a x , 0 . 9 t y p .

0 . 4 9 0

0 . 3 4 0

0 . 8 1 0

0 . 8 0 0

0 . 5 5 0

0 . 5 0 0

Figure 22. Faceplate Dimensions

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Component

Side Up

J3

8x 0.047 Alignment holes

J1

0.208

0.039

Connector Detail

Figure 23. Connector Detail

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9.2 CM-2 Schematics

connector

connector.sch

core

core.sch

HRESET#

HEN#

HRW

HDS#

HADDR[0..3]

HDATA[0..7]

HREQ#

HEN#

HRW

HDS#

HEN#

HRW

HDS#

HADDR[0..3]

HDATA[0..7]

HREQ#

HADDR[0..3]

HDATA[0..7]

HREQ#

HACK#

WATCHDOG

MUTE#

WATCHDOG

MUTE#

WATCHDOG

MUTE#

UART_TX_OE

UART_TXD

UART_RXD

UART_TX_OE

UART_TXD

UART_RXD

UART_TX_OE

UART_TXD

UART_RXD

MCLK_OUT

MCLK_IN

REFCLK_IN

MCLK_OUT

MCLK_IN

REFCLK_IN

MCLK_OUT

MCLK_IN

REFCLK_IN

FS1

SSI_CLK

SSI_DIN[0..3]

SSI_DOUT[0..3]

FS1

SSI_CLK

SSI_DIN[0..3]

SSI_DOUT[0..3]

FS1

SSI_CLK

SSI_DIN[0..3]

SSI_DOUT[0..3]

GPIO[0..1] is not used elsewhere.

These pulldowns are used for test points and

to keep these signals at valid levels.

GPIO[0..1]

RSVD[1..5]

AUX_POWER[0..3]

GPIO0

GPIO1

R1

R2

RSVD[1..5]

AUX_POWER[0..3]

RSVD[1..5]

AUX_POWER[3..0]

GND

10K Ohm

This linear regulator is used to assure that the +1.8v rail quickly passes

the 0.5v threshold at powerup, thus minimizing power sequencing issues

and making sure that the DSP does not draw excessive power as the

power rails ramp up. This linear regulator is set with Vout=1.22v, so it

is effectively shut off once the switching regulator comes up. Further

testing and characterization of the DSP is require to determine if this

linear regulator is in fact required.

U9

1

2

4

3

5

IN

OUT

BYP

ADJ

C45

0.01 uF

GND

LTC1761

U1

LTC3406-1.8

L1

4

1

3

5

VCC_+3.3

VIN

SW

VCC_+1.8

2.2 uH

RUN

Vout/FB

C1

10 uF, X5R, 6.3 Volts

C2

C3

10 uF, X5R, 6.3 Volts

This is a simple switching regulator. It produces

1.8V at >500 mA at about 90% efficency. A simple low drop

out linear regulator would be a cheaper alternative at the

expense of power. A linear regulator would dissapate

about 0.75 watts max, This switching regulator dissapates

about 0.10 watts max.

Figure 24. CM-2 RevF Schematic Page 1 of 7

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LED_BUF[0..7]

V C C

G N D

8

1 6

L E D _ C T R L [ 0 . . 2 ]

V C C

G N D

8

1 6

A D D R [ 0 . . 1 9 ]

D A T A [ 0 . . 1 5 ]

Figure 25. CM-2 RevF Schematic Page 2 of 7

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G N D

4 6

2 7

V C C

3 7

Figure 26. CM-2 RevF Schematic Page 3 of 7

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R 5 0

R 4 8

R 4 6

R 4 2

R 5 1

R 4 9

R 4 7

R 4 3

V C C

G N D

8

1 6

3 . 3 K O h m

R 5 6

V D D _ A

G N D _ A

1 2 9

1 2 6

T E S T

N C

9

8 1

8 0

N C

D B D A

D B C K

R 1 4

R 1 3

3

4

7 9

7 8

5 3

5 2

5 1

5 0

2 8

V D D I O

7 3

1 3 6

1 1 3

9 1

6 0

4 4

G N D

1 3 9

3 3

1 8

1 3 3

1 2 2

1 1 6

1 0 1

V D D D

1 3 0

1 1 9

9 8

8 3

6 6

5 4

2 4

1 0

9 4

8 6

7 6

6 9

6 3

5 7

4 7

3 6

2 7

2 1

1 3

4

6

2

8

5

3

7

1

4

6

2

8

5

3

7

1

4

6

2

8

5

3

7

1

4

6

2

8

5

3

7

1

4

6

2

8

5

3

7

1

4

6

2

8

5

3

7

1

Figure 27. CM-2 RevF Schematic Page 4 of 7

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L E D _ B U F 1 L 1

L E D _ B U F 0 L 2

L E D _ B U F 3 L 3

L E D _ B U F 2 L 4

R 3 2

R 3 1

R 3 0

R 2 9

R 2 8

R 2 7

V C C

G N D

1 4

7

4

6

2

8

5

3

7

1

G P I O 0

G P I O 1

G P I O 2

G P I O 3

E E C S

E E C K

E E D O

E E D I

6 8

L E D _ C T R 6 9 L 0

L E D _ C T R 7 0 L 1

L E D _ C T R 7 1 L 2

6 7

6 6

6 5

6 4

S P E E D #

D U P #

L I N K A C T #

6 0

6 1

6 2

B G G N D

2 5

B G R E S

2 6

C L K 2 0 M O

5 9

T E S T 1

T E S T 2

T E S T 3

T E S T 4

T E S T 5

1 6

1 7

1 8

1 9

4 8

X 1 _ 2 5 M

2 2

C L K _ 2 5

X 2 _ 2 5 M

2 1

4

6

2

8

5

3

7

1

N C

7 7

N C

7 5

A V D D

N C

7 4

3 5

2 8

2 7

A G N D

3 2

A G N D

3 1

D V D D

9 0

7 3

7 2

5 5

3 6

2 0

5

D G N D

9 9

D G N D

8 1

D G N D

7 6

D G N D

6 3

D G N D

5 8

D G N D

4 2

D G N D

2 3

D G N D

1 5

4

6

2

8

5

3

7

1

Figure 28. CM-2 RevF Schematic Page 5 of 7

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L E D _ B U F L 5 1

L E D _ B U F L 4 2

L E D _ B U F L 7 3

L E D _ B U F L 6 4

R 3 8

R 3 7

R 3 6

R 3 5

R 3 4

R 3 3

4 9 . 9 O h m , 1 %

R 2 2

R 2 1

4

6

2

8

5

3

7

1

G P I O 0

G P I O 1

G P I O 2

G P I O 3

E E C S

6 7

6 8

6 9

7 0

7 1

E E C K

6 6

E E D O

6 5

E E D I

6 4

S P E E D #

D U P #

L I N K A C T #

6 0

6 1

6 2

B G G N D

2 5

B G R E S

2 6

C L K 2 0 M O

5 9

T E S T 1

T E S T 2

T E S T 3

T E S T 4

T E S T 5

1 6

1 7

1 8

1 9

4 8

X 1 _ 2 5 M

X 2 _ 2 5 M

2 2

2 1

C L K _ 2 5

4

6

2

8

5

3

7

1

N C

7 7

7 5

7 4

A V D D

3 5

2 8

2 7

A G N D

3 2

3 1

D V D D

9 0

7 3

7 2

5 5

3 6

2 0

5

D G N D

9 9

8 1

7 6

6 3

5 8

4 2

2 3

1 5

4

6

2

8

5

3

7

1

Figure 29. CM-2 RevF Schematic Page 6 of 7

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1

Figure 30. CM-2 RevF Schematic Page 7 of 7

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9.3 CS1810xx/CS4961xx Package

E

E1

D D1

Notes:

SEATING PLANE

B

e

b

ddd

M

B

1. Controlling dimension is millimeter.

2. Dimensioning and tolerancing per ASME

L1

Y14.5M-1994.

θ

A

A1

L

Figure 31. 144-Pin LQFP Package Drawing

MILLIMETERS

INCHES

NOM

DIM

MIN

NOM

MAX

MIN

MAX

A

A1

b

---

1.60

0.15

0.27

---

.063”

.006”

.011”

0.05

0.17

---

.002”

.007”

---

0.22

.009”

.866”

.787”

.866”

.787”

.020”

D

22.00 BSC

20.00 BSC

22.00 BSC

20.00 BSC

0.50 BSC

D1

E

E1

e

0°

---

7°

0°

---

7°

θ

L

0.45

0.60

0.75

.018”

.024”

.030”

L1

1.00 REF

.039” REF

TOLERANCES OF FORM AND POSITION

ddd

0.08

.003”

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9.4 Temperature Specifications

• Thermal Coefficient (junction-to-ambient): θ_ja- 38° C / Watt

• Ambient Temperature Range: 0-70 deg C

• Junction Temperature Range: 0-125 deg C

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Ordering Information

10.0 Ordering Information

10.1 Device Part Numbers

CS181002-CQ/A1

CS181012-CQ/A1

CS181022-CQ/A1

2x2 Channels

8x8 Channels

16x16 Channels

0°C to +70°C

144-pin LQFP

CS181002-CQZ/A1 2x2 Channels

CS181012-CQZ/A1 8x8 Channels

CS181022-CQZ/A1 16x16 Channels

0°C to +70°C

144-pin LQFP Lead Free

CS496102-CQZ/A1 2x2 Channels + DSP

0°C to +70°C

144-pin LQFP Lead Free

CS496112-CQZ/A1

8x8 Channels + DSP

CS496122-CQZ/A1 16x16 Channels + DSP 0°C to +70°C

10.2 Device Part Numbering Scheme

CS1810x2 — CQZ/A1

Die Revision

Base Part Number

Lead-free Designator:

Z = Lead-free Device Packaging

(not present if device contains lead)

Channel Count Designator:

0 = 2x2

1 = 8x8

2 = 16x16

Package Type:

Q = LQFP (144-pin)

ROM Version

(ROM ID)

Temperature Grade Designator:

C = Commercial (0°C to +70°C)

CS4961x2 — CQZ/A1

Die Revision

Base Part Number

Lead-free Designator:

Z = Lead-free Device Packaging

(not present if device contains lead)

Channel Count Designator:

0 = 2x2

1 = 8x8

2 = 16x16

Package Type:

Q = LQFP (144-pin)

ROM Version

(ROM ID)

Temperature Grade Designator:

C = Commercial (0°C to +70°C)

Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative.

Figure 32. Device Part Numbering Explanation

DS651UM23

Version 2.3

53

CobraNet Hardware User’s Manual

Ordering Information

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information

is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest

version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the

terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability.

No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or

for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license,

express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copy-

rights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization

with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution,

advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE

PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WAR-

RANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE

SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN

SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EX-

PRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,

WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR

PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS,

ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS'

FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be

trademarks or service marks of their respective owners.

Motorola is a registered trademark of Motorola, Inc.

Intel is a registered trademark of Intel, Inc.

54

DS651UM23

Version 2.3


型号：	CS496112-CQZ/A1
厂家：	CIRRUS LOGIC
描述：	Digital Audio Networking Processor 数字音频网络处理器消费电路商用集成电路
文件：	总54页 (文件大小：663K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS496112-CQZ/A1 [CIRRUS]

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