CS5317-KP_技术文档

CS5317

16-Bit, 20 kHz Oversampling A/D Converter

Features

Description

The CS5317 is an ideal analog front-end for voiceband

signal processing applications such as high-perfor-

mance modems, passive sonar, and voice recognition

systems. It includes a 16-bit A/D converter with an inter-

nal track & hold amplifier, a voltage reference, and a

linear-phase digital filter.

l Complete Voiceband DSP Front-End

- 16-Bit A/D Converter

- Internal Track & Hold Amplifier

- On-Chip Voltage Reference

- Linear-Phase Digital Filter

l On-Chip PLL for Simplified Output Phase

Locking in Modem Applications

l 84 dB Dynamic Range

An on-chip phase-lock loop (PLL) circuit simplifies the

CS5317’s use in applications where the output word rate

must be locked to an external sampling signal.

l 80 dB Total Harmonic Distortion

l Output Word Rates up to 20 kHz

l DSP-Compatible Serial Interface

l Low Power Dissipation: 220 mW

The CS5317 uses delta-sigma modulation to achieve

16-bit output word rates up to 20 kHz. The delta-sigma

technique utilizes oversampling followed by a digital fil-

tering and decimation process. The combination of

oversampling and digital filtering greatly eases antialias

requirements. Thus, the CS5317 offers 84 dB dynamic

range and 80 dB THD and signal bandwidths up to

10 kHz at a fraction of the cost of hybrid and discrete

solutions.

The CS5317’s advanced CMOS construction provides

low power consumption of 220 mW and the inherent re-

liability of monolithic devices.

ORDERING INFORMATION

See page 20.

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Cirrus Logic, Inc.

Copyright Cirrus Logic, Inc. 1997

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

MAR ‘95

DS27F4

1

CS5317

ANALOG CHARACTERISTICS _{(T = T}

± ±

; VA+, VD+ = 5V 10%; VA-, VD- = -5V 10%;

CLKIN = 4.9152 MHz in CLKOR mode; 1kHz Input Sinewave; with 1.2 kΩ, .01 µF antialiasing filter.)

- T

A

MIN

MAX

Parameter*

Specified Temperature Range

Min

Typ

Max

Units

0 to 70

°C

Resolution

16

-

Bits

Dynamic Performance

Dynamic Rnage

(Note 1)

(Note2)

78

72

-

84

80

84

-

dB

Total Harmonic Distortion

Signal to Intermodulation Distorition

dc Accuracy

Differential Nonlinearity

Positive Full-Scale Error

Positive Full-Scale Drift

Bipolar Offset Error

-

LSB

mV

±0.4

±150

±500

±10

µV/°C

mV

Bipolar Offset Drift

±50

µV/°C

Filter Characteristics

Absolute Group Delay

Passband Frequency

Input Characteristics

(Note 3)

(Note 4)

78.125

-

µs

5

kHz

AC Input Impedance

(1kHz)

-

80

-

kΩ

Analog Input Full Scale Signal Level

Power Supplies

V

±2.75

Power Dissipation

(Note5)

-

220

300

mW

Notes: 1. Measured over the full 0 to 9.6kHz band with a -20dB input and extrapolated to full-scale. Since this

includes energy in the stopband above 5kHz, additional post-filtering at the CS5317’s output can

typically achieve 88dB dynamic range by improving rejection above 5kHz. This can be increased to

90dB by bandlimiting the output to 2.5kHz.

2. No missing codes is guaranteed by design.

3. Group delay is constant with respect to input analog frequency; that is, the digital FIR filter has

linear phase. Group delay is determined by the formula D = 384/CLKIN in CLKOR mode, or

grp

192/CLKOUT in any mode.

4. The digital filter’s frequency response scales with the master clock. Its -3dB point is determined by

f

= CLKIN/977.3 in CLKOR mode, or CLKOUT/488.65 in any mode.

-3dB

5. All outputs unloaded. All inputs CMOS levels.

* Refer to the Parameter Definitions section after the Pin Description section.

2

DS27F4

CS5317

ANALOG CHARACTERISTICS (continued)

Parameter

Min

Typ

Max

Units

Power Supply Rejection

VA+

VA-

VD+

VD-

(Note 6)

-

60

45

60

55

-

dB

Specified Temperature Range

0 to 70

°C

Phase-Lock Loop Characteristics

VCO Gain Constant, Ko

(Note 7)

(Note 8)

-4

1.28

-3

-10

-

-30

5.12

-12

Mrad/Vs

MHz

VCO Operating Frequency

Phase Detector Gain Control, Kd

Phase Detector Prop. Delay

-8

50

µA/rad

ns

-

100

Notes: 6. With 300mV p-p, 1kHz ripple applied to each supply separately.

7. Over 1.28 MHz to 5.12 MHz VCO output range, where VCO frequency = 2 CLKOUT.

*

8. Delay from an input edge to the phase detector to a response at the PHDT output pin.

DIGITAL CHARACTERISTICS _{(T = T}

- T ; VA+, VD+ = 5V±10%; VA-, VD- = -5V±10%)

MAX

A

MIN

All measurements performed under static conditions.

Parameter

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

Low-Level Input Voltage

High-Level Output Voltage

V

2.0

-

0.8

-

V

IH

V

-

IL

(Note 9)

V

(VD+)-1.0V

-

V

OH

Low-Level Output Voltage

Input Leakage Current

3-State Leakage Current

I

= 1.6mA

V

I

-

0.4

10

±10

-

V

OL

OUT

-

µA

pF

in

I

-

OZ

Digital Output Pin Capacitance

C

out

9

Note: 9. I =-100µA. This specification guarantees the ability to drive one TTL load (V =2.4V @ I =-40µA.).

out

OH

out

RECOMMENDED OPERATING CONDITIONS (DGND, AGND = 0V, see Note 10.)

Parameter

Symbol

Min

Typ

Max

Units

DC Power Supplies:

Positive Digital

VD+

VD-

VA+

VA-

4.5

-4.5

4.5

5.0

-5.0

5.0

5.5

-5.5

5.5

V

Negative Digital

Positive Analog

Negative Analog

-4.5

-5.0

-5.5

Master Clock Frequency

f

0.01

-

5.12

MHz

clk

Note: 10. All voltages with respect to ground.

Specifications are subject to change without notice.

DS27F4

3

CS5317

SWITCHING CHARACTERISTICS _{(T = T}

-T

; C =50 pF; VD+ = 5V±10%; VD- = -5V±10%)

L

A

MIN MAX

Parameter

Symbol

Min

Typ

Max

Units

Master Clock Frequency:

CLKIN

CLKG1 Mode

CLKG2 Mode

CLKOR Mode

f

-

20

10

5.12

kHz

MHz

clkg1

clkg2

clkor

Output Word Rate:

Rise Times:

DOUT

f

-

20

kHz

dout

Any Digital Input

Any Digital Output

t

-

20

15

1000

20

ns

risein

t

riseout

Fall Times:

Any Digital Input

Any Digital Output

t

-

20

15

1000

20

ns

fallin

t

fallout

CLKIN Duty Cycle

CLKG1 and CKLG2 Modes

Pulse Width Low

Pulse Width High

Pulse Width Low

Pulse Width High

t

200

45

-

ns

pwl1

t

pwh1

CLKOR Mode

t

pwl1

t

45

pwh1

RST Pulse Width Low

t

400

-

ns

pwr

Set Up Times:

RST High to CLKIN High

CLKIN High to RST High

t

40

-

ns

su1

su2

Propagation Delays:

DOE Falling to Data Valid

CLKIN Rising to DOUT Falling

DOE Rising to Hi-Z Output

CLKOUT Rising to DOUT Falling

CLKOUT Rising to DOUT Rising

CLKOUT Rising to Data Valid

CLKIN Rising to CLKOUT Falling

CLKIN Rising to CLKOUT Rising

t

-

1

-

150

-

80

60

100

200

ns

CLKOUT

cycles

ns

phl1

phl2

plh1

plh2

plh3

plh4

plh5

plh6

(Note 11)

t

ns

(Note 12)

Notes: 11. CLKIN only pertains to CLKG1 and CLKG2 modes.

12. Only valid in CLKOR mode.

ABSOLUTE MAXIMUM RATINGS (DGND, AGND = 0V, all voltages with repect to groung)

Parameter

Symbol

Min

Max

Units

DC Power Supplies:

Positive Digital

VD+

VD-

VA+

VA-

-0.3

0.3

-0.3

0.3

(VA+) + 0.3

-6.0

V

Negative Digital

Positive Analog

Negative Analog

6.0

-6.0

Input Current, Any Pin Except Supplies

Analog Input Voltage (AIN and VREF pins)

Digital Input Voltage

(Note 13)

I

-

(VA-) - 0.3

-0.3

mA

V

±10

(VA+) + 0.3

(VD+) + 0.3

125

in

V

INA

V

IND

Ambient Operating Temperature

Storage Temperature

T

-55

°C

A

T

-65

150

stg

Notes: 13. Transient currents up to 100mA will not cause SCR latch-up.

WARNING:Operating this device at or beyond these extremes may result in permanent damage to the device.

Normal operation of the part is not guaranteed at these extremes.

4

DS27F4

CS5317

t

riseout

t

risein

fallin

fallout

2.0 V

0.8 V

2.4 V

0.4 V

Rise and Fall Times

t

pwh1

pwl1

CLKIN

CLKIN Timing

t

CLKIN

(Note 14)

phl2

t

plh3

CLKOUT

DOUT

t

plh1

plh2

t

phl1

15

14

1

0

DATA

t

plh4

(MSB)

DOE

(Note 15)

Serial Output Timing

CLKIN

t

plh6

t

plh5

CLKOUT

DOUT

t

su1

t

su2

su1

t

su2

pwr

RST

(Note 16)

Reset Timing

Notes: 14. CLKIN only pertains to CLKG1 and CLKG2 modes.

15. If DOE is brought high during serial data transfer, CLKOUT, DOUT, and DATA will immediately

3-state and the rest of the serial data is lost.

16. RST must be held high except in the clock override (CLKOR) mode where it can be used to align

the phases of all internal clocks.

DS27F4

5

CS5317

GENERAL DESCRIPTION

modulator’s 1-bit output conveys information in

the form of duty cycle. The digital filter then

processes the 1-bit signal and extracts a high

resolution output at a much lower rate (that is,

16-bits at a 20 kHz word rate with a 5 kHz input

bandwidth).

The CS5317 functions as a complete data conver-

sion subsystem for voiceband signal processing.

The A/D converter, sample/hold, voltage refer-

ence, and much of the antialiasing filtering are

performed on-chip. The CS5317’s serial interface

offers its 16-bit, 2’s complement output in a for-

An elementary example of a delta-sigma A/D

converter is a conventional voltage-to-frequency

converter and counter. The VFC’s 1-bit output

conveys information in the form of frequency (or

duty-cycle), which is then filtered (averaged) by

the counter for higher resolution. In comparison,

the CS5317 uses a more sophisticated multi-order

modulator and more powerful FIR filtering to ex-

tract higher word rates, much lower noise, and

more useful system-level filtering.

mat

which

easily

interfaces

with

industry-standard micro’s and DSP’s.

The CS5317 also includes a phase-locked loop

that simplifies the converter’s application in sys-

tems which require sampling to be locked to an

external signal source. The CS5317 continuously

samples its analog input at a rate set by an exter-

nal clock source. On-chip digital filtering, an

integral part of the delta-sigma ADC, processes

the data and updates the 16-bit output register at

up to 20 kHz. The CS5317 can be read at any rate

up to 20 kHz.

Filtering

At the system level, the CS5317’s digital filter

can be modeled exactly like an analog filter with

a few minor differences. First, digital filtering re-

sides behind the A/D conversion and can thus

reject noise injected during the conversion proc-

ess (i.e. power supply ripple, voltage reference

noise, or noise in the ADC itself). Analog filtering

cannot.

The CS5317 is a CS5316 with an on-chip sam-

pling clock generator. As such, it replaces the

CS5316 and should be considered for all new de-

signs. In addition, a CS5316 look-alike mode is

included, allowing a CS5317 to be dropped into a

CS5316 socket.

Also, since digital filtering resides behind the

A/D converter, noise riding unfiltered on a near-

full-scale input could potentially saturate the

ADC. In contrast, analog filtering removes the

noise before it ever reaches the converter. To ad-

dress this issue, the CS5317’s analog modulator

and digital filter reserve headroom such that the

device can process signals with 100mV "excur-

sions" above full-scale and still output accurately

converted and filtered data. Filtered input signals

above full-scale still result in an output of all

ones.

THEORY OF OPERATION

The CS5317 utilizes the delta-sigma technique of

executing low-cost, high-resolution A/D conver-

sions. A delta-sigma A/D converter consists of

two basic blocks: an analog modulator and a digi-

tal filter.

Conversion

The analog modulator consists of a 1-bit A/D

converter (that is, a comparator) embedded in an

analog negative feedback loop with high open-

loop gain. The modulator samples and converts

the analog input at a rate well above the band-

width of interest (2.5 MHz for the CS5317). The

An Application Note called "Delta Sigma Over-

view" contains more details on delta-sigma

conversion and digital filtering.

6

DS27F4

CS5317

SYSTEM DESIGN WITH THE CS5317

Some systems such as echo-canceling modems,

though, require the output sampling rate to be

locked to a sampling signal which is 20 kHz or

below. For this reason the CS5317 includes an

on-chip phase-lock loop (PLL) which can gener-

ate its requisite 5.12 MHz master clock from a

20 kHz sampling signal.

Like a tracking ADC, the CS5317 continuously

samples and converts, always tracking the analog

input signal and updating its output register at a

20 kHz rate. The device can be read at any rate to

create any system-level sampling rate desired up

to 20kHz.

The CS5317 features two modes of operation

which utilize the internal PLL. The first, termed

Clock Generation 1 (CLKG1), accepts a sam-

pling clock up to 20 kHz at the CLKIN pin and

internally generates the requisite 5.12 MHz clock.

The CS5317 then processes samples updating its

output register at the rate defined at CLKIN, typi-

cally 20 kHz. For a 20 kHz clock input the digital

filter’s 3 dB corner is set at 5.239 kHz, so CLKG1

provides a factor of 2X oversampling at the sys-

tem level (20 kHz is twice the minimum possible

sampling frequency needed to reconstruct a 5

kHz input). The CLKG1 mode is initiated by ty-

ing the MODE input to +5V.

Clocking

Oversampling is a critical function in delta-sigma

A/D conversion. Although system-level output

sample rates typically remain between 7kHz and

20kHz in voiceband applications, the CS5317 ac-

tually samples and converts the analog input at

rates up to 2.56 MHz. This internal sampling rate

is typically set by a master clock which is on the

order of several megahertz. See Table1 for a com-

plete description of the clock relationships in the

various CS5317 operating modes.

+5V

10

Ω

Analog

Supply

0.1

µ

F

1

2

0.1

µF

VA+

VD+

10

µF

10

µF

9

Clock

CLKIN

MODE

Source

VD- (clock override mode / CLKOR)

VD+ (clock gen. mode / CLKG1)

(clock gen. mode / CLKG2)

7

CS5317

Analog

Signal

Source

16

3

Signal

Conditioning

11

18

AIN

± 2.75V

RST

DOE

uP or DSP

Control

8

6

5

VA+

DOUT

DATA

Serial

Data

VCOIN

PHDT

AGND

25 k

Ω

17

15

25 nF

Interface

CLKOUT

0.1

µF

0.1

10

4

µ

F

12

DGND

VD-

REFBUF

VA-

14

10

µF

-5V

10

Ω

0.1

µF

Analog

Supply

Figure 1. System Connection Diagram with Example PLL Components

DS27F4

7

CS5317

Output Word

Rate Provides

CLKOUT DOUT

Mode

System-level 2X

RESET Oversampling

CLKIN

(kHz)

7.2

9.6

f

F

t

*

sin

sout

dcD

Mode

Clock

Symbol

(MHz)

(kHz) (kHz)

7.2

9.6

(ns)

CLKG2

CLKG1

CLKOR

0V

+5V

-5V

HIGH

SYNC

NO

1.8432

2.4576

2.56

1.8432

2.4576

2.56

1.8432

2.4576

2.56

14.4

19.2

20.0

14.4

19.2

20.0

14.4

19.2

20.0

542.5

406.9

390.6

542.5

406.9

390.6

N/A

Gen. 2

10.0 (max)

10.0

YES

14.4

19.2

20.0 (max)

3686.4

4915.2

5120.0 (max)

14.4

19.2

20.0

14.4

19.2

20.0

Clock

Gen. 1

Clock

Override

CS5316

CS5316 FSYNC LOW

5120.0 (max)

2.56

20.0

N/A

- Delay from CLKIN rising to DOUT falling = 1 CLKOUT cycle

* t

dcD

Table 1. Mode Comparisons

The second PLL mode is termed Clock Genera-

Analog Design Considerations

tion 2 (CLKG2) which generates its 5.12 MHz

clock from a 10 kHz external sampling signal.

Again, output samples are available at the system

sampling rate set by CLKIN, typically 10 kHz.

For the full-rated 10 kHz clock CLKG2 still sets

the filter’s 3 dB point at 5 kHz. Therefore,

CLKG2 provides no oversampling beyond the

Nyquist requirement at the system level

(10 kHz : 5 kHz) and its internal digital filter pro-

vides little anti-aliasing value. The CLKG2 mode

is initiated by grounding the MODE pin.

DC Characteristics

The CS5317 was designed for signal processing.

Its analog modulator uses CMOS amplifiers re-

sulting in offset and gain errors which drift over

temperature. If the CS5317 is being considered

for low-frequency (< 10 Hz) measurement appli-

cations, Crystal Semiconductor recommends the

CS5501, a low-cost, d.c. accurate, delta-sigma

ADC featuring excellent 60 Hz rejection and a

system-level calibration capability.

The CS5317 features a third operating mode

called Clock Override (CLKOR). Initiated by ty-

ing the MODE pin to -5V, CLKOR allows the

5.12 MHz master clock to be driven directly into

the CLKIN pin. The CS5317 then processes sam-

The Analog Input Range and Coding Format

The input range of the CS5317 is nominally ± 3V,

with ± 250 mV possible gain error. Because of

this gain error, analog input levels should be kept

below ± 2.75V. The converter’s serial output ap-

pears MSB-first in 2’s complement format.

ples updating its output register at f

/256.

clkin

Since all clocking is generated internally, the

CLKOR mode includes a Reset capability which

allows the output samples of multiple CS5317’s

to be synchronized.

Antialiasing Considerations

The CS5317 also has a CS5316 compatible

mode, selected by tying RST low, and using

MODE (pin 7) as the FSYNC pin. See the

CS5316 data sheet for detailed timing informa-

tion.

In applying the CS5317, aliasing occurs during

both the initial sampling of the analog input at f

s

in

(~2.5 MHz) and during the digital decimation

process to the 16-bit output sample rate, f

.

s

out

8

DS27F4

CS5317

Initial Sampling

noise within ± 5 kHz bands around 2.5 MHz, 5

MHz, 7.5 MHz, etc. will pass unfiltered and alias

into the baseband. Such noise can only be filtered

by analog filtering before the signal is sampled.

Since the signal is heavily oversampled (2.5

MHz : 5 kHz, or 500 : 1), a single-pole passive

RC filter can be used as shown in Figure 2.

The CS5317 samples the analog input, AIN, at

one-half the master clock frequency (~2.5 MHz

max). The input sampling frequency, f , appears

at CLKOUT regardless of whether the master

clock is generated on-chip (CLKG1 and CLKG2

modes) or driven directly into the CS5317

(CLKOR mode). The digital filter then processes

the input signal at the input sample rate.

s

in

Input

Signal

AIN

1.2 K

Like any sampled-data filter, though, the digital

0.01µF

filter’s passband spectrum repeats around integer

multiples of the sample rate, f . That is, when

s

in

the CS5317 is operating at its full-rated speed any

Note: Any nonlinearities contributed by this filter

will be encoded as distortion by the CS5317.

Therefore a low distortion, high frequency ca-

jω

0

Mag H(e ) (dB)

-2.74 dB

pacitor such as COG-ceramic is recommended.

Figure 2. Anti-alias Filter

-40

-80

f

0

.25 F .5 F

F

2F

3F

3

sin(128πƒT)

=

Magnitude where: T = 1/ƒ

sin

128sin(πƒT)

ƒ

= input sampling frequency = CLKOUT frequency for all modes

= CLKIN/2 in CLKOR mode

sin

= CLKIN*128 in CLKG1 mode

= CLKIN*256 in CLKG2 mode

F = ƒ /128 for all modes

sin

ƒ = input frequency

ƒ

= ƒ /128 = output data rate for CLKOR & CLKG1 = F

sin

sout

ƒ

= ƒ /256 = output data rate for CLKG2 = F/2

sin

sout

Examples:

For ƒ = 2.56 MHz at ƒ = 5 kHz: Magnitude is -2.74 dB

sin

For ƒ = 2.56 MHz at ƒ = 10 kHz: Magnitude is -11.8 dB

sin

Figure 3. CS5317 Low-Pass Filter Response

DS27F4

9

CS5317

Decimation

noise from the modulator. This will typically in-

crease the converter’s dynamic range to 88 dB.

Aliasing effects due to decimation are identical in

the CLKOR and CLKG1 modes. Aliasing is dif-

ferent in the CLKG2 mode due to the difference

in output sample rates (10 kHz vs. 20 kHz) and

thus will be discussed separately.

Further bandlimiting the digital output to f _out/8

(2.5 kHz at full speed) will typically increase dy-

namic range to 90 dB.

s

Aliasing in the CLKG2 Mode

Aliasing in the CLKOR and CLKG1 Modes

Aliasing effects in the CLKG2 mode can be mod-

eled exactly as those in the CLKG1 mode with

the output decimated by two (from 20 kHz to 10

kHz). This is most easily achieved by ignoring

every other sample. In the CLKG2 mode the ratio

of the output sampling rate to the filter’s -3 dB

point is two, with no oversampling beyond the

demands of the Nyquist criterion. Without the

The delta-sigma modulator output is fed into the

digital low-pass filter at the input sampling rate,

f . The filter’s frequency response is shown in

s

in

Figure 3. In the process of filtering the digitized

signal the filter decimates the sampling rate by

128 (that is, f

= f /128). In its most elemen-

s

in

s

out

tary form, decimation simply involves ignoring -

or selectively reading - a fraction of the available

samples.

ability to roll-off substantially before f _out/2, the

on-chip digital filter’s antialiasing value is dimin-

ished.

s

In the process of decimation the output of the

The CLKG2 mode should therefore be used only

when the output data rate must be minimized due

to communication and/or storage reasons. In ad-

dition, adequate analog filtering must be provided

prior to the A/D converter.

digital filter is effectively resampled at f _out, the

s

output word rate, which has aliasing implications.

Residual signals after filtering at multiples of f

s

out

will alias into the baseband. For example, an in-

put tone at 28 kHz will be attenuated by 39.9 dB.

If f

= 20 kHz, the residual tone will alias into

Digital Design Considerations

s

out

the baseband and appear at 8 kHz in the output

spectrum.

The CS5317 presents its 16-bit serial output

MSB-first in 2’s complement format. The con-

verter’s serial interface was designed to easily

interface to a wide variety of micro’s and DSP’s.

Appendix A offers several hardware interfaces to

industry-standard processors.

If the input signal contains a large amount of out-

of-band energy, additional analog and/or digital

antialias filtering may be required. If digital post-

filtering is used to augment the CS5317’s

rejection above f _out/4 (that is, above 5 kHz), the

s

filtering will also reject residual quantization

f

out

DOUT

CLKOUT

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

15 14

DATA

MSB

LSB

(sign bit)

Figure 4. Data Output

10

DS27F4

CS5317

Data Output Characteristics & Coding Format

manently damaged. If the two supplies are de-

rived from separate sources, care must be taken

that the analog supply comes up first at power-up.

Figure 1 shows a decoupling scheme which al-

lows the CS5317 to be powered from a single set

As shown in Figure 4, the CS5317 outputs its 16-

bit data word in a serial burst. The data appears at

the DATA pin on the rising edge of the same

CLKOUT cycle in which DOUT falls. Data

changes on the rising edge of CLKOUT, and can

be latched on the falling edge. The CLKOUT rate

±

of 5V rails. The digital supplies are derived

from the analog supplies through 10 Ω resistors

to prevent the analog supply from dropping be-

low the digital supply.

is set by the CLKIN input (f

/2 in the CLKOR

clkin

mode; f

*128 in the CLKG1 mode; and

clkin

f

*256 in the CLKG2 mode). DOUT returns

clkin

PLL Characteristics

high after the last bit is transmitted. After trans-

mitting the sixteen data bits, DATA will remain

high until DOUT falls again, initiating the next

data output cycle.

A phase-locked loop is included on the CS5317

and is used to generate the requisite high fre-

quency A/D sampling clock. A functional

diagram of the PLL is shown in Figure 5. The

PLL consists of a phase detector, a filter, a VCO

(voltage-controlled oscillator), and a counter/di-

A 3-state capability is available for bus-oriented

applications. The 3-state control input is termed

Data Output Enable, DOE, and is asynchronous

with respect to the rest of the CS5317. If DOE is

taken high at any time, even during a data burst,

the DATA, DOUT and CLKOUT pins go to a

high impedance state. Any data which would be

output while DOE is high is lost.

vider. The phase detector inputs are CLKIN (θ )

1

and a sub-multiple of the VCO output signal (θ ).

2

The inputs to the phase detector are positive-edge

triggered and therefore the duty cycle of the

CLKIN signal is not significant. With this type of

phase detector, the lock range of the PLL is equal

to the capture range and is independent of the low

pass filter. The output of the phase detector is in-

put to an external low pass filter. The filter

characteristics are used to determine the transient

response of the loop. The output voltage from the

filter functions as the input control voltage to the

VCO. The output of the VCO is then divided in

frequency to provide an input to the phase detec-

tor. The clock divider ratio is a function of the

PLL mode which has been selected.

Power Supplies

Since the A/D converter’s output is digitally fil-

tered in the CS5317, the device is more forgiving

and requires less attention than conventional 16-

bit A/D converters to grounding and layout

arrangements. Still, care must be taken at the de-

sign and layout stages to apply the device

properly. The CS5317 provides separate analog

and digital power supply connections to isolate

digital noise from its analog circuitry. Each sup-

ply pin should be decoupled to its respective

ground, AGND or DGND. Decoupling should be

accomplished with 0.1 µF ceramic capacitors. If

significant low frequency noise is present in the

supplies, 10 µF tantalum capacitors are recom-

mended in parallel with the 0.1 µF capacitors.

Phase Detector Gain (Kd)

A properly designed and operating phase-locked

loop can be described using steady state linear

analysis. Once in frequency lock, any phase dif-

ference between the two inputs to the phase

detector cause a current output from the detector

during the phase error. While either the +50 µA or

the -50 µA current source may be turned on, the

average current flow is:

The positive digital power supply of the CS5317

must never exceed the positive analog supply by

more than a diode drop or the chip could be per-

DS27F4

11

CS5317

tio sets the ratio of the VCO frequency to the

CLKIN frequency. As illustrated in Figure 5, the

VCO output is always divided by two to yield the

CLKOUT signal which is identical in frequency

to the delta-sigma modulator sampling clock.

The CLKOUT signal is then further divided by

either 128 in the CLKG1 mode or by 256 in the

CLKG2 mode. When the divide by two stage is

included, the divider ratio (N) for the PLL in the

CLKG1 mode is effectively 256. In the CLKG2

mode the divider ratio (N) is 512.

i

= Kd(θ −θ ) ≈ (−50µA ⁄ 2π) (θ −θ )

1 2 1 2

out

avg

where θ is the phase of IN1, θ is the phase of

1

2

IN2 and Kd is the phase detector gain. The factor

2π comes from averaging the current over a full

CLKIN cycle. Kd is in units of micro-am-

peres/radian.

VCO Gain (Ko)

The output frequency from the VCO ranges from

1.28 MHz to 5.12 MHz. The frequency is a func-

tion of the control voltage input to the VCO. The

VCO has a negative gain factor, meaning that as

the control voltage increases more positively the

output frequency decreases. The gain factor units

are Megaradians per Volt per Second. This is

equivalent to 2π Megahertz per volt. Changes in

output frequency are given by:

Loop Transfer Function

As the phase-locked loop is a closed loop system,

an equation can be determined which describes its

closed loop response. Using the gain factors for

the phase detector and the VCO, the filter ar-

rangement and the counter/divider constant N,

analysis will yield the following equation which

describes the transfer function of the PLL:

∆ω = Ko ∆VCO

[Ko is typ. -10Mrad/Vs.]

vco

in

KoKdR

N

KoKd

NC

s +

Counter/Divider Ratio

θ

2

1

=

KoKdR

KoKd

NC

2

s +

The CS5317 PLL multiplies the CLKIN rate by

an integer value. To set the multiplication rate, a

counter/divider chain is used to divide the VCO

output frequency to develop a clock whose fre-

quency is compared to the CLKIN frequency in

the phase detector. The binary counter/divider ra-

N

This equation may be rewritten such that its ele-

ments

correspond

with

the

following

+5V

VA+

External RC

50 µA

K

=

-8

µ

A/rad

d

C

1

C

2

R

IN1

DOWN

CLKOR

CLKIN

Phase/Frequency

Detect Logic

VCO

2

Delta-Sigma

Sampling Clock

(CLKOUT)

PHDT VCOIN

CLKOR

IN2

UP

K

= -10 Mrad/V.s

0

2

50

-5V

µ

A

CLKG2

CLKG1

128

2

Conversion Output Rate -

Same Frequency as DOUT

Internal Sync for Digital Filter

Figure 5. PLL Functional Diagram

12

DS27F4

CS5317

characteristic form in which the damping factor,

CLKIN is approximately 20 times greater than

the 3 dB corner frequency of the control loop.

ζ, and the natural frequency, ω , are evident:

n

2

Filter Components

θ

2ζω s + ω_n

n

2

1

=

2

s + 2ζω s + ω

n

Using the equations which describe the transfer

function of the PLL system, the following exter-

nal filter component equations can be determined:

Both thenaturalfrequencyand thedampingfac-

tor are particularly important in determining the

transient response of the phase-locked loop when

subjected to a step input of phase or frequency. A

family of curves are illustrated in Figure 6 that

indicate the overshoot and stability of the loop as

a function of the damping factor. Each response is

KoKd

C =

2

Nω

n

N

KoKd

R = 2ζω

n

plotted as a function of the normalized time, ω t.

n

The gain factors (Ko, Kd) are specified in the

Analog Characteristics table. In the event the sys-

tem calls for very low bandwidth, hence a

corresponding reduction in loop gain, the phase

detector gain factor Kd can be reduced. A large

series resistor (R1) can be inserted between the

output of the detector and the filter. Then the

50 µA current sources will saturate to the supplies

and yield the following gain factor:

For a given ζ and lock time, t, the ω required

n

can be determined. Alternatively, phase lock con-

trol loop bandwidth may be a specified parameter.

In some systems it may be desirable to reduce the

-3dB bandwidth of the PLL control loop to re-

duce the effects of jitter in the phase of the input

clock. The 3 dB bandwidth of the PLL control

loop is defined by the following equation:

ω_3dB= ω √2ζ²+ 1 +

2

n

√(2ζ + 1) + 1

−5V

Kd ≈

2πR

1

The equations used to describe the PLL and the

3 dB bandwidth are valid only if the frequency of

20 log(θ /θ )

2

1

θ

normalized to θ

2

1

4

3

ζ= 0.5

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

ζ = 0.5

ζ = 0.6

ζ = 0.7

ζ = 0.8

ζ = 0.9

ζ = 1.0

ζ = 1.5

ζ = 2.0

ζ = 3.0

ζ = 10.0

2

1

ζ = 10

0

ζ= 10.0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0

1

2

3

4

5

6

7

8

9

10

0.1

1

10

ω

t.

n

ω/ω

n

Figure 6a. θ Unit Step Response

2

Figure 6b. Second Order PLL Frequency Response

DS27F4

13

CS5317

In some applications additional filtering may be

useful to eliminate any jitter associated with the

discrete current pulses from the phase detector.

In this case a capacitor whose value is no more

than 0.1 C can be placed across the RC filter net-

To calculate values for the resistor R and capaci-

tor C of the filter, we must first derive a value for

ω . Using the general rule that the sample clock

n

should be at least 20 times higher frequency than

the 3dB bandwidth of the PLL control loop:

work (C in Figure 5).

2

CLKIN ≥ 20 ω_3dB

Filter Design Example

where CLKIN = 9600 Hz = 2π 9600 radians/sec.

So: ω_3dB= 2π 9600/20 = 3016 radians/sec.

Knowing ω_3dBand the damping factor of 1.0, we

The following is a step by step example of how to

derive the loop filter components. The CS5317

A/D sampling clock is to be derived from a 9600

Hz clock source. The application requires the sig-

nal passband of the CS5317 to be 4 kHz. The

on-chip digital filter of the CS5317 has a 3 dB

passband of CLKOUT/488.65 (see Note 4 in the

data sheet specifications tables). The 4 kHz pass-

band requirement dictates that the sample clock

(CLKOUT) of the CS5317 be a minimum of

4000 X 488.65 = 1.954 MHz. This requires the

VCO to run at 3.908 MHz. The 3.908 MHz rate is

407 times greater than the 9600 Hz PLL input

clock. Therefore the CS5317 must be set up in

mode CLKG2 with N = 512. If the CLKG1 mode

were used (N = 256), too narrow of a signal band-

width through the A/D would result.

can calculate the natural frequency, ω , of the

n

control loop:

2

ω = ω_3dB√2ζ + 1 +

n

√(2ζ + 1) + 1

2

ω = 3016 √2(1) + 1 +

n

√(2(1) + 1) + 1

ω = 1215

n

1 ⁄ sec

Once the natural frequency, ω , is determined,

n

values for R and C for the loop filter can be cal-

culated:

Once the operating mode has been determined

from the system requirements, a value for the

damping factor must be chosen. Figure 6 illus-

trates the dynamic aspects of the system with a

given damping factor. Damping factor is gener-

ally chosen to be between 0.5 and 2.0. The choice

of 0.5 will result in an overshoot of 30 % to a step

response whereas the choice of 2.0 will result in

an overshoot of less than 5 %. For example pur-

poses, let us use a damping factor of 1.0.

R = 2ζω N/KoKd

n

R = 2(1)(1215 1/s) 512/(-10Mrad/v.s.)(-8 µA/rad)

R = 15552 v/A = 15.55 kΩ. Use R = 15 kΩ.

2

C = KoKd/Nω

n

2

C = (-10 Mrad/v.s)(- 8 µA/rad)/512 (1215 1/s)

-9

So, let us begin with the following variables :

C = 105.8 x 10 A.s/v = 105 nF. Use 0.1 µF.

Ko = - 10 Mradians/volt.sec

Kd = - 8 µA/radian

N = 512

The above example assumed typical values for

Ko and Kd. Your application may require a worst

case analysis which includes the minimum or

maximum values. Table 2 shows some other ex-

ample situations and R and C values.

ζ = 1.0

14

DS27F4

CS5317

CLKIN

(Hz)

7200

9600

14400

19200

CLKOUT

(MHz)

1.8432

2.4576

1.8432

2.4576

Mode

CLKG2

CLKG1

N

ζ

ω

911

1215

1822

2430

R * (kΩ)

11.6

15.5

11.6

15.5

C * (nF)

187

106

94

3dB

n

512

256

1.0

2262

3016

4524

6032

52

* The values for R and C are as calculated using the described method. Component tolerances have

not been allowed for. Notice that Ko and Kd can vary over a wide range, so using tight tolerances

for R and C is not justified. Use the nearest conveniently available value.

Table 2 Example PLL Loop Filter R and C values

CS5317 PERFORMANCE

The quality of the window used for harmonic

analysis is typically judged by its highest side-

lobe level. The Blackman-Harris window used to

test the CS5317 has a maximum side-lobe level

of -92 dB.

The CS5317 features 100% tested dynamic per-

formance. The following section is included to

illustrate the test method used for the CS5317.

FFT Tests and Windowing

Figure 7 shows an FFT plot of a typical CS5317

with a 1 kHz sinewave input generated by an "ul-

tra-pure" sine wave generator and the output

multiplied by a Blackman-Harris window. Arti-

facts of windowing are discarded from the

signal-to-noise calculation using the assumption

that quantization noise is white. All FFT plots in

this data sheet were derived by averaging the FFT

results from ten time records. This filters the

spectral variability that can arise from capturing

finite time records, without disturbing the total

energy outside the fundamental. All harmonics

and the -92 dB side-lobes from the Blackman-

Harris window are therefore clearly visible in the

plots.

The CS5317 is tested using Fast Fourier Trans-

form (FFT) techniques to analyze the converter’s

dynamic performance. A pure sine wave is ap-

plied to the CS5317 and a "time record" of 1024

samples is captured and processed. The FFT algo-

rithm analyzes the spectral content of the digital

waveform and distributes its energy among 512

"frequency bins". Assuming an ideal sinewave,

distribution of energy in bins outside of the fun-

damental and dc can only be due to quantization

effects and errors in the CS5317.

If sampling is not synchronized to the input sine-

wave it is highly unlikely that the time record will

contain an exact integer number of periods of the

input signal. However, the FFT assumes that the

signal is periodic, and will calculate the spectrum

of a signal that appears to have large discontinui-

ties, thereby yielding a severely distorted

spectrum. To avoid this problem, the time record

is multiplied by a window function prior to per-

forming the FFT. The window function smoothly

forces the endpoints of the time record to zero,

removing the discontinuities. The effect of the

"window" in the frequency domain is to convo-

lute the spectrum of the window with that of the

actual input.

0dB

Sampling Rate: 19.2 kHz

-20dB

-40dB

Full Scale:

+_ 2.75 V

S/(N+D): 81.39 dB

-60dB

Signal

Amplitude

Relative to

Full Scale

-80dB

-100dB

-120dB

1 kHz

9.6 kHz

dc

Input Frequency

Figure 7. CS5317 Dynamic Performance

DS27F4

15

CS5317

Full - scale signal - to - noise - plus - distortion

[S/(N+D)] is calculated as the ratio of the rms

power of the fundamental to the sum of the rms

power of the FFT’s other frequency bins, which

include both noise and distortion. For the

CS5317, signal-to-noise-plus-distortion is shown

to be better than 81 dB for an input frequency

range of 0 to 9.6 kHz (fs/2).

0dB

-20dB

-40dB

-60dB

-80dB

-100dB

-120dB

S/I.M.D.: 84.7 dB

Signal

Amplitude

Relative to

Full Scale

Harmonic distortion characteristics of the CS5317

are excellent at 80 dB full scale signal to THD

(typical), as are intermodulation distortion char-

acteristics, shown in Figure 8. Intermodulation

distortion results from the modulation distortion

of two or more input frequencies by a non-linear

transfer function.

800 1450

9600

dc

Input Frequency (Hz)

Figure 8. CS5317 Intermodulation Distortion

The plot below illustrates the typical DNL per-

formance of the CS5317, and clearly shows the

part easily achieves no missing codes.

DNL Test

Figure 9 shows a plot of the typical differential

non-linearity (DNL) of the CS5317. This test is

done by taking a large number of conversion re-

sults, and counting the occurrences of each code.

A perfect A/D converter would have all codes of

equal size and therefore equal numbers of occur-

rences. In the DNL test, a code with the average

number of occurrences is considered ideal and

plotted as DNL = 0 LSB. A code with more or

less occurrences than average will appear as a

DNL of greater than or less than zero. A missing

code has zero occurrences, and will appear as a

DNL of -1 LSB.

Schematic & Layout Review Service

Confirm Optimum

Schematic & Layout

Before Building Your Board.

For Our Free Review Service

Call Applications Engineering.

C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2

+1

+1/2

0

-1/2

-1

0

32,768

65,535

Codes

Figure 9. CS5317 DNL Plot

16

DS27F4

CS5317

PIN DESCRIPTIONS (Pin numbers refer to the 18-pin DIP package)

18 pin DIP Pinout

POSITIVE ANALOG POWER

POSITIVE DIGITAL POWER

DATA OUTPUT ENABLE

DIGITAL GROUND

VA+

VD+

DOE

VCOIN

PHDT

RST

AGND

VA-

VCO INPUT

PHASE DETECT

RESET

ANALOG GROUND

NEGATIVE ANALOG POWER

NO CONNECT

18

17

16

15

14

13

12

11

10

1

2

3

4

5

6

7

8

9

DGND

SERIAL CLOCK OUTPUT CLKOUT

SERIAL DATA OUTPUT

CLOCKING MODE SELECT

DATA OUTPUT READY

CLOCK INPUT

DATA

MODE

DOUT

CLKIN

NC

REFBUF POSITIVE REFERENCE BUFFER

AIN

VD-

ANALOG INPUT

NEGATIVE DIGITAL POWER

20 pin SOIC pinout

POSITIVE ANALOG POWER

POSITIVE DIGITAL POWER

DATA OUTPUT ENABLE

VA+

VD+

DOE

VCOIN

PHDT

RST

VCO INPUT

PHASE DETECT

RESET

ANALOG GROUND

NO CONNECT

1

2

3

4

5

6

7

8

9

10

20

19

18

17

DIGITAL GROUND DGND

AGND

NO CONNECT

NC

16 NC

15

14

13

12

11

SERIAL CLOCK OUTPUT CLKOUT

SERIAL DATA OUTPUT DATA

CLOCKING MODE SELECT MODE

DATA OUTPUT READY DOUT

CLOCK INPUT CLKIN

NC

VA-

NEGATIVE ANALOG POWER

REFBUF POSITIVE REFERENCE BUFFER

AIN

VD-

ANALOG INPUT

NEGATIVE DIGITAL POWER

Power Supplies

VD+ - Positive Digital Power, PIN 2.

Positive digital supply voltage. Nominally 5 volts.

VD- - Negative Digital Power, PIN 10.

Negative digital supply voltage. Nominally -5 volts.

DGND - Digital Ground, PIN 4.

Digital ground reference.

VA+ - Positive Analog Power, PIN 1.

Positive analog supply voltage. Nominally 5 volts.

VA- - Negative Analog Power, PIN 14.

Negative analog supply voltage. Nominally -5 volts.

AGND - Analog Ground, PIN 15.

Analog ground reference.

PLL/Clock Generator

CLKIN - Clock Input, PIN 9.

Clock input for both clock generation modes and the clock override mode (see MODE).

DS27F4

17

CS5317

MODE - Mode Set, PIN 7.

Determines the internal clocking mode utilized by the CS5317. Connect to +5V to select

CLKG1 mode. Connect to DGND to select CLKG2 mode. Connect to -5V to select CLKOR

mode. This pin becomes equivalent to FSYNC in the CSZ5316 compatible mode.

VCOIN - VCO Input, PIN 18.

This pin is typically connected to PHDT. A capacitor and resistor in series connected between

VA+ and this pin sets the filter response of the on-chip phase locked loop.

PHDT - Phase Detect, PIN 17.

This pin is typically connected to VCOIN. A capacitor and resistor in series connected between

VA+ and this pin sets the filter response of the on-chip phase locked loop.

Inputs

AIN - Analog Input, PIN 11.

DOE - Data Output Enable, PIN 3.

Three-state control for serial output interface. When low, DATA, DOUT, and CLKOUT are

active. When high, they are in a high impedance state.

RST - Sample Clock Reset, PIN 16.

Sets phase of CLKOUT. Functions only in the clock override mode, CLKOR. Used to

synchronize the output samples of multiple CS5317’s. Must be kept high in CLKG1 or CLKG2

modes. Also, tying this pin low, with MODE not tied to - 5V, will place the CS5317 into

CSZ5316 compatible mode.

Outputs

DOUT - Data Output Flag, PIN 8.

The falling edge indicates the start of serial data output on the DATA pin. The rising edge

indicates the end of serial data output.

DATA - Data Output, PIN 6.

Serial data output pin. Converted data is clocked out on this pin by the rising edge of

CLKOUT. Data is sent MSB first in two’s complement format.

CLKOUT - Data Output Clock, PIN 5.

Serial data output clock. Data is clocked out on the rising edge of this pin. The falling edge

should be used to latch data. Since CLKOUT is a free running clock, DOUT can be used to

indicate valid data.

REFBUF - Positive Voltage Reference Noise Buffer, PIN 12.

Used to attenuate noise on the internal positive voltage reference. Must be connected to the

analog ground through a 0.1µF ceramic capacitor.

18

DS27F4

CS5317

PARAMETER DEFINITIONS

N

Resolution - The number of different output codes possible. Expressed as N, where 2 is the number

of available output codes.

Dynamic Range - The ratio of the largest allowable input signal to the noise floor.

Total Harmonic Distortion - The ratio of the rms sum of all harmonics to the rms value of the largest

allowable input signal. Units in dB’s.

Signal to Intermodulation Distortion - The ratio of the rms sum of two input signals to the rms sum

of all discernible intermodulation and harmonic distortion products.

Linearity Error - The deviation of a code from a straight line passing through the endpoints of the

transfer function after zero- and full-scale errors have been accounted for. "Zero-scale" is a

point 1/2 LSB below the first code transition and "full-scale" is a point 1/2 LSB beyond the

code transition to all ones. The deviation is measured from the middle of each particular code.

Units in %FS.

Differential Nonlinearity - The deviation of a code’s width from the ideal width. Units in LSB’s.

Positive Full Scale Error - The deviation of the last code transition from the ideal, (VREF - 3/2 LSB).

Units in mV.

Positive Full Scale Drift - The drift in effective, positive, full-scale input voltage with temperature.

Negative Full Scale Error - The deviation of the first code transition from the ideal, (-VREF + 1/2

LSB). Units in mV.

Negative Full Scale Drift - The drift in effective, negative, full-scale input voltage with temperature.

Bipolar Offset - The deviation of the mid-scale transition from the ideal. The ideal is defined as the

middle transition lying on a straight line between actual positive full-scale and actual negative

full-scale.

Bipolar Offset Drift - The drift in the bipolar offset error with temperature.

Absolute Group Delay - The delay through the filter section of the part.

Passband Frequency - The upper -3 dB frequency of the CS5317.

DS27F4

19

CS5317

ORDERING GUIDE

Model Number

CS5317-KP

CS5317-KS

Temperature Range

0 to 70°C

Package

18 Pin Plastic DIP

20 Pin Plastic SOIC

0 to 70°C

20

DS27F4

CS5317

APPENDIX A

APPLICATIONS

Figure A1 shows one method of converting the

serial output of the CS5317 into 16-bit, parallel

words. The associated timing is also shown.

+5V

CS5317

DATA

OE2

P

A

D0

D1

D2

D3

D4

D5

D6

D7

A

P

B

CLKOUT

DOUT

P

C

8

P

D

S1

S2

P

E

P

F

P

G

16

Q

H

P

Data

Bus

H

OE1

+5V

CS

OE2 OE1

P

D8

A

P

D9

B

A

P

D10

D11

D12

D13

D14

D15

C

8

P

D

P

E

S1

S2

P

F

P

G

P

H

SET

D

Q

INT

Only needed for level sensitive interrupt driven systems.

CLKOUT

DOUT

15

14

13

2

1

0

DATA

INT

(MSB)

INT Cleared when data read

(CS goes low)

Figure A1. CS5317-to-Parallel Data Bus Interface

DS27F4

21

CS5317

Figure A2 shows the interconnection and timing

details for connecting a CS5317 to a NEC

µPD7730 DSP chip.

Figure A3 shows the interconnection and timing

details for connecting a CS5317 to a Motorola

DSP 56000.

CS5317

CLKOUT

µ

PD77230

Status Register (SR)

SICK

SIEN

SI

Bit Mnemonic Setting Meaning

DOUT

DATA

9

7, 6

3

SCI

SDLI

SIF

0

External Clock

1, 0 16 bit data

MSB First

0

CLKOUT

DOUT

DATA

15

14

13

2

1

0

(MSB)

Figure A2. CS5317-to-NEC µPD77230 Serial Interface

SYNC ASYNC

CLKOUT SCK

SC0

CS5317

CLKOUT

DSP56000

SSI Control Reg. A

CRA (X:FFEC)

PINS DOUT

SC2

SC1

WL1 = 1

16 bits

GCK

0

1

0

-

0

-

SCK, SC0

SC2, SC1

SRD

WL0 = 0

SYN

FSL

DOUT

DATA

SCKD

SCD2

SCD1

SCD0

-

0

-

CLKOUT

DOUT

DATA

15

14

13

2

1

0

(MSB)

Figure A3. CS5317-to-Motorola DSP56000 Serial Interface

22

DS27F4

CS5317

Figure A4 shows the interconnection and timing

details for connecting a CS5317 to a WE DSP16

DSP chip.

Figure A5 shows the interconnection and timing

details for connecting a CS5317 with TMS32020

and TMS320C25 DSP chips.

Serial I/O Control Register (SIOC)

Field Value Meaning

CS5317

DSP16

ICK

MSB

ILD

1

0

MSB input first

ILD is an input

ICK is an input

16 bit input data

CLKOUT

DOUT

ILD

DI

ICK

D

Q

DATA

ILEN

DATA

d

74

CLKOUT

DOUT

DATA

15

14

13

2

1

0

d

(MSB)

Figure A4. CS5317-to-WE DSP16 Serial Interface

TMS32020

CS5317

TMS320C25

TMS32020 Status Register (ST1):

F0 = 0 (16 bit data)

CLKOUT

DOUT

CLKR

FSR

DR

TMS320C25 Status Register (ST1):

F0 = 0 (16 bit data)

DATA

FSM = 1 (Frame Sync used)

CLKOUT

DOUT

DATA

15

14

13

2

1

0

(MSB)

Figure A5. CS5317-to-TMS32020/TMS320C25 Serial Interface

DS27F4

23

CDB5317

Evaluation Board for CS5317

Features

Description

The CDB5317 Evaluation Board is designed to allow the

user to quickly evaluate performance of the CS5317 Del-

ta-Sigma Analog-to-Digital Converter. All that is required

to use this board is an external power supply, a signal

source, a clock source, and an ability to read either serial

or parallel 16bitdata words.

Easy to Use Digital Interface

Parallel 16 Bits With Clock

Serial Output With Clock

Multiple Operating Modes

Including Two PLL Modes

IDC Header used to access Parallel Data,

ORDERING INFORMATION

Serial Data, and Clock Input and Output

CDB5317

Evaluation Board

I

V

L

+5V GND -5V

AIN

CLKOUT

DATA

CLKIN

SERIAL TO PARALLEL

CONVERTER

CLKIN

CS5317

DRDY

DACK

IDC HEADER

D0-D15

Cirrus Logic, Inc.

Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.crystal.com

MAR ‘95

DS27DB3

25

CDB5317

GENERAL DESCRIPTION

Set-up for evaluation is straightforward. First de-

cide the operating mode and place the jumper on

the board for the proper selection. Then decide

whether the filter components for the phase

locked loop are adequate or whether they should

be changed for your evaluation. The PLL will

lock on a steady clock input with the filter as it is.

Connect the necessary 5 V (CMOS compatible)

CLKIN signal for the application. Use the sine-

wave generator to supply the analog signal to the

CDB5317. Apply the analog input and CLKIN

signals only when the evaluation board is pow-

ered up. Converted data will then appear at the

header on the CDB5317. The header should be

connected to the digital data acquisition board in

the PC through an IDC 40 pin connector and ca-

ble. The software routine should collect the data

from the CDB5317 and run a standard 1024 point

Fast Fourier Transform (FFT). Such an analysis

results in a plot similar to Figure 1. This plot re-

sulted from using a 1kHz input signal and a

Blackman-Harris window for the FFT.

The CDB5317 Evaluation Board is a stand-alone

environment for easy lab evaluation of the

CS5317 Delta-Sigma Analog-to-Digital Converter.

Included on the board is a serial-to-parallel con-

verter. The user can access output data in either

parallel or serial form. When supplied with the

necessary +5 V and -5 V power supplies, a

CLKIN signal, and an analog signal source, the

CDB5317 will provide converted data at the 40

pin header.

SUGGESTED EVALUATION METHOD

An efficient evaluation of the CS5317 using the

CDB5317 may be accomplished as described be-

low.

The following equipment will be required for the

evaluation:

• The CDB5317 Evaluation Board.

• A power supply capable of supplying +5V and

-5V.

• A clock source as the CLKIN signal of the

CS5317.

• A spectrally pure sine wave generator such as

the Krohn-Hite Model 4400A "Ultra-Low Distor-

tion Oscillator".

• A PC equipped with a digital data acquisition

board such as the Metrabyte Model PIO12 "24 Bit

Parallel Digital I/O Interface".

The signal to noise and signal to total harmonic

distortion characteristics of the CS5317 may be

easily measured in this way. The signal to total

harmonic distortion value for a particular input is

the ratio of the RMS value of the input signal and

the sum of the RMS values of the harmonics

shown in the diagram. The dynamic range of the

CS5317 can be measured by reducing the input

0dB

• A software routine to collect the data and per-

form a Fast Fourier Transform (FFT).

Sampling Rate: 19.2 kHz

± 2.75 V

Full Scale:

S/(N+D): 81.39 dB

-20dB

-40dB

-60dB

The evaluation board includes filter components

for the on-chip phase locked loop. The compo-

nents are adequate for testing if the CLKIN signal

has little or no phase-jitter. If the CDB5317 board

is being tested as part of a system which generates

a CLKIN which contains jitter, the PLL filter

components may need to be optimized for your

system (see the CS5317 data sheet).

Signal

Amplitude

Relative to

Full Scale

-80dB

-100dB

-120dB

9.6 kHz

1 kHz

dc

Input Frequency

Figure 1. FFT Plot Example

26

DS27DB3

CDB5317

amplitude so that distortion products become neg-

ligible. This allows an accurate measurement of

the noise floor.

are supplied on the board to connect the +5, -5,

and ground power lines. A good quality low rip-

ple, low noise supply will give the best

performance. The +5 V supply can also be used

for VL and should be connected between the VL

board jack and the power supply, as opposed to

connecting the VL jack straight to the +5V jack.

The +5V jack is the positive power source for the

CS5317 IC whereas the VL jack supplies power

to all the digital ICs. Care should be taken that

noise is not coupled between VL and +5V; how-

ever, supply noise is generally not a problem with

the CS5317 since the on-chip decimation filter

will remove any interference outside of its pass-

band. The +5 and -5 V supply lines are filtered on

More complex analysis such as intermodulation

distortion measurements can be accomplished

with the addition of another sine-wave generator.

CIRCUIT DESCRIPTION

Figure 2 illustrates the CS5317 A/D converter IC

circuit connections. The chip operates off of ±5V.

These voltages are supplied from a power source

external to the evaluation board. Binding posts

TP6

V

L

C5

0.1

C4

10

D1

µ

F

µF

R7

10

TP10

D3

+5V

1

2

C9

10

C8

C6

10

C7

+

3

C19

C17

0.22

6.8v

µF

0.1

µF

0.1 µF

µ

F

µ

F

VA+

VD+

R10

10k

R5

17

18

DOE

PHDT

VCOIN

10 k

8

5

6

DOUT (fig. 3)

CLKOUT (fig. 3)

DATA (fig. 3)

DOUT

CLKOUT

R2

200

TP8

9

CLKIN

AIN

CLKIN

DATA

RST

R9

16

R1*

51

CLKIN (fig.6)

R6

10 k

U6

R11

11

12

AIN

CLKG1

CLKG2

CLKOR

C18

0.01

NPO

1.2k

7

4

REFBUF

µF

P2

MODE

C14

CS5317

DGND

0.1

µF

TP7

15

GND

-5V

AGND

C15

C16

C13 C12

+

D2

VA-

14

VD-

10

TP9

10 F

µ

0.1

µ

F

6.8v

0.1

µF

10 µF

R8

10

* Remove for logic gate CLKIN source

Figure 2. Analog-to-Digital Converter

DS27DB3

27

CDB5317

the board and then connected to the V + and V -

supply pins of the chip. The +5 V and -5V are

to the phase detector of the on-chip phase locked

loop of the CS5317.

A

then connected by means of ten Ω resistors to the

Header connector P2 (see Figure 2) is provided to

allow mode selection for the CS5317 chip. The

mode selection works together with the CLKIN

signal to set the sample rate and the output word

rate of the CS5317. See the CS5317 data sheet

for details on mode selection. Two of the avail-

able modes (CLKG1 and CLKG2) utilize the

on-chip phase locked loop to step up the CLKIN

frequency to obtain the necessary sample rate

clock for the A/D converter. Another mode (the

CLKOR mode) does not use the on-chip PLL but

instead drives the sample function directly. The

V + and V - pins respectively. Capacitive filter-

D

ing is provided on all supply pins of the chip. In

addition there is a 0.1 µF filter capacitor con-

nected from the REFBUF pin of the chip to the

V - supply pin.

A

To properly operate, the CS5317 chip requires an

external (5 V CMOS compatible) clock. A BNC

connector labeled CLKIN is provided to connect

the off-board clock signal to the board. The

CLKIN signal is also available on the 40 pin

header connector. The CLKIN signal is one input

DOUT2

(fig. 6)

V

L

C10

V

U5

L

0.1

µ

F

1

3

2

4

14

4

C1

µ

0.1 F

D

TP2

S

2

3

5

6

D

Q

U4

74HC74

14

DRDY

(fig. 6)

12

13

1

2

9

8

DOUT

(fig. 2)

CL

Q

7

10

11

13

GND R

V

L

V

7

L

12

TP3

µ

0.1 F

C11

6

14

DACK

(fig. 6)

5

U5

R4

10k

7

3

4

CLKOUT

(fig. 2)

UNUSED GATES

VL

U1

5

6

8

CLKOUT

(fig. 6)

CLKOUT2

(fig. 6)

10

VL

12

11

9

8

S

Q

D

11

10

9

DATA

(fig. 2)

DATA 1

(fig. 6)

U4

CL

Q

R

DATA

(fig. 6)

VL

13

Figure 3. Buffers and Parallel Handshake Flip-Flop

28

DS27DB3

CDB5317

CLKOUT

DATA

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DOUT

Note: For a complete description of serial timing see the CS5317 Data Sheet

Figure 4 Serial Data Timing

two modes which use the phase locked loop will

require appropriate low pass filter components on

the Evaluation Board. The low pass filter compo-

nents help determine the PLL control loop

response, including its bandwidth and stability

and therefore directly affect the transient response

of the PLL control loop. Appropriate filter compo-

nents should be installed if a particular dynamic

response to changes of the CLKIN signal is de-

sired.

The analog signal to be digitized is input to the

AIN BNC connector. The digital output words

from the CS5317 are buffered by HEX inverters

as shown in Figure 3. The buffered versions of

the CLKOUT and DATA signals are available on

the header connector P1 in Figure 6. The serial

data signals out of the CS5317 are illustrated in

Figure 4. If remote control of the DOE line is

desired, the trace on the PC Board can be opened

and a wire connection can be soldered to the DOE

input line. Remote control of the RST line of the

CS5317 is also available if desired.

The filter components which are installed on the

board have been chosen for the following parame-

ters: MODE: CLKG2; CLKIN: 7,200; N=512;

damping factor: 1.0; Control loop -3 dB band-

width: 2262 radians/second. These parameters

yield R as 10 k Ω and C as 0.22 µF for the filter

components.

Figures 5 and 6 illustrate the serial to parallel shift

registers including timing information. The DATA

output signal from the CS5317 is input to the data

input of the shift register. An inverted version of

the CLKOUT signal is used to clock the DATA

into the shift registers. The two 8-bit shift register

ICs also include output latches. The rising edge

Serial Data

Shifting Out

Serial Data

Shifting Out

Parallel Data Valid

Parallel Data (D0-D15) Valid

DATA

DOUT

DRDY

DACK

Figure 5. Parallel Data Timing

DS27DB3

29

CDB5317

of the DOUT signal from the CS5317 is used to

latch the data once it is input to the shift registers.

The rising edge of DOUT is also used to toggle

the DRDY flip flop (see Figure 3). The flip flop

is used to signal a remote device whenever new

data is latched into the output registers. The

DRDY flip flop is reset whenever DACK occurs.

A component layout of the CDB5317 board is il-

lustrated in Figure 7.

CLKIN

(fig. 2)

CLKOUT2

(fig. 3)

P1

V

L

TP4

CLKIN

CLKOUT

DATA

D15

C2

0.1

µ

F

10 16

RST

DATA1

(fig. 3)

7

QH

D14

6

74HC595

U2

QG

QF

QE

QD

QC

QB

QA

D13

5

TP5

D12

4

D11

12

3

LATCH CLK

SHIFT CLK

D10

2

D9

11

14

1

D8

15

DIN

GND

OE

8

13

V

L

R3

C3

10k

0.1

µ

F

10 16

D7

D6

D5

D4

D3

D2

D1

D0

9

RST

DOUT

7

QH

QG

QF

QE

QD

QC

QB

QA

6

5

74HC595

4

U3

3

12

DOUT2

(fig. 3)

LATCH CLK

2

11

14

1

CLKOUT

(fig. 3)

DATA

(fig. 2)

SHIFT CLK

15

DIN

DACK

DRDY

GND

13

8

DACK

(fig. 3)

DRDY

(fig. 3)

Figure 6.

30

DS27DB3

CDB5317

Figure 7. Bird’s Eye View

DS27DB3

31


型号：	CS5317-KP
厂家：	CIRRUS LOGIC
描述：	16-Bit, 20 kHz Oversampling A/D Converter 16位， 20kHz的过采样A / D转换器转换器
文件：	总32页 (文件大小：355K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS5317-KP [CIRRUS]

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