CS5342-CZZ [CIRRUS]
105 dB, 192 kHz, MULTI-BIT AUDIO A/D CONVERTER; 105分贝， 192千赫，多比特音频A / D转换器
| 型号： | CS5342-CZZ |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 105 dB, 192 kHz, MULTI-BIT AUDIO A/D CONVERTER |
| 文件： | 总22页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS5342
105 dB, 192 kHz, Multi-bit Audio A/D Converter
Features
General Description
The CS5342 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to-
digital conversion and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form at
sample rates up to 200 kHz per channel.
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
Supports all audio sample rates including
192 kHz.
105 dB Dynamic Range at 5 V
-98 dB THD+N
The CS5342 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
High-pass Filter to Remove DC Offsets
Analog/Digital Core Supplies From 3.3 V to 5 V
Supports logic levels between 2.5 V and 5 V.
Low-latency Digital Filter
The CS5342 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
set-top boxes, DVD-karaoke players, DVD recorders,
A/V receivers, and automotive applications.
Automatic Mode Selection
ORDERING INFORMATION
CS5342-CZZ Lead-free -10° to 70° C
CS5342-DZZ Lead-free -40° to 85° C
CDB5342
16-pin TSSOP
16-pin TSSOP
Evaluation Board
Supports 384x MCLK/LRCK Ratios.
VL
2.5V - 5.0V
SCLK
VQ
LRCK SDOUT MCLK
REFGND
RST
M0
Serial Output Interface
FILT+
AINL
Voltage Reference
+
M1
High
Pass
Filter
Digital
Decimation
LP Filter
Q
Q
-
Filter
S/H
DAC
High
Pass
Filter
Digital
Decimation
+
AINR
LP Filter
-
Filter
S/H
DAC
VA
3.3V - 5.0V
GND
VD
3.3V - 5.0V
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
AUG ‘04
DS608PP2
www.cirrus.com
CS5342
TABLE OF CONTENTS
1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG CHARACTERISTICS (CS5342-CZZ) ....................................................................... 5
DIGITAL FILTER CHARACTERISTICS.................................................................................... 7
DC ELECTRICAL CHARACTERISTICS................................................................................. 10
DIGITAL CHARACTERISTICS............................................................................................... 10
THERMAL CHARACTERISTICS............................................................................................ 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT................................................. 11
2 PIN DESCRIPTION ................................................................................................................. 13
3 TYPICAL CONNECTION DIAGRAM ....................................................................................... 14
4 APPLICATIONS ....................................................................................................................... 15
4.1 Single, Double, and Quad Speed Modes ......................................................................... 15
4.2 Operation as Either a Clock Master or Slave ................................................................... 15
4.2.1 Operation as a Clock Master ............................................................................... 16
4.2.2 Operation as a Clock Slave ................................................................................. 16
4.2.3 Master Clock ....................................................................................................... 17
4.3 Serial Audio Interface ....................................................................................................... 17
4.4 Power-up Sequence ........................................................................................................ 18
4.5 Analog Connections ......................................................................................................... 18
4.6 Grounding and Power Supply Decoupling ....................................................................... 18
4.7 Synchronization of Multiple Devices ................................................................................ 19
4.8 Capacitor Size on the Reference Pin (FILT+) .................................................................. 19
5 PARAMETER DEFINITIONS ................................................................................................... 20
6 PACKAGE DIMENSIONS ....................................................................................................... 21
7. REVISION HISTORY .............................................................................................................. 22
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com/
IMPORTANT NOTICE
LEGAL NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc.
and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to
change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of
relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms
and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items,
or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no
license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns
the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your or-
ganization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general
distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SE-
VERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR
WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE
SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND
PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-
STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IM-
PLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY
CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF
CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DI-
RECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS,
THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
2
DS608PP2
CS5342
LIST OF FIGURES
Figure 1. Single Speed Stopband Rejection .................................................................................. 8
Figure 2. Single Speed Stopband Rejection (detail) ...................................................................... 8
Figure 3. Single Speed Transition Band (detail) ............................................................................ 8
Figure 4. Single Speed Passband Ripple ...................................................................................... 8
Figure 5. Double Speed Stopband Rejection ................................................................................. 8
Figure 6. Double Speed Stopband Rejection (detail) ..................................................................... 8
Figure 7. Double Speed Transition Band (detail) ........................................................................... 9
Figure 8. Double Speed Passband Ripple ..................................................................................... 9
Figure 9. Quad Speed Stopband Rejection ................................................................................... 9
Figure 10. Quad Speed Stopband Rejection (detail) ..................................................................... 9
Figure 11. Quad Speed Transition Band (detail) ............................................................................ 9
Figure 12. Quad Speed Passband Ripple ...................................................................................... 9
Figure 13. Master Mode, Left Justified SAI .................................................................................. 12
Figure 14. Slave Mode, Left Justified SAI .................................................................................... 12
2
Figure 15. Master Mode, I S SAI ................................................................................................. 12
2
Figure 16. Slave Mode, I S SAI ................................................................................................... 12
Figure 17. Typical Connection Diagram ....................................................................................... 14
Figure 18. CS5342 Master Mode Clocking .................................................................................. 16
Figure 19. Left-Justified Serial Audio Interface ............................................................................ 17
2
Figure 20. I S Serial Audio Interface ............................................................................................ 17
Figure 21. CS5342 Recommended Analog Input Buffer .............................................................. 18
Figure 22. CS5342 THD+N versus Frequency ............................................................................ 19
LIST OF TABLES
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)........................................ 15
Table 2. CS5342 Mode Control..................................................................................................... 15
Table 3. Master Clock (MCLK) Ratios........................................................................................... 17
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates .......................... 17
Table 5. Revision History .............................................................................................................. 22
DS608PP2
3
CS5342
1
CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at typical supply voltages
and T = 25°C.)
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V, all voltages with respect to 0 V.)
Parameter
Power Supplies (Notes 2, 3)
Symbol
Min
Typ
Max
Unit
Analog
Digital
Logic
VA
VD
VL
3.14
3.14
2.38
(Note 1)
3.3
5.25
5.25
5.25
V
V
V
3.3
Ambient Operating Temperature
Commercial (-CZZ)
T
-10
-
70
°C
AC
Notes: 1. This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics (CS5342-
CZZ) below for details.
2. In Quad-Speed Slave Mode, the CS5342 is only specified for operation with VA and VD at 5 V, 5%.
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 3)
Parameter
Symbol
Min
Max
Units
DC Power Supplies:
Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
+6.0
+6.0
+6.0
V
V
V
Input Current
(Note 4)
(Note 5)
(Note 5)
I
-
GND-0.7
-0.7
10
VA+0.7
VL+0.7
+95
mA
V
in
Analog Input Voltage
Digital Input Voltage
V
IN
V
V
IND
Ambient Operating Temperature (Power Applied)
Storage Temperature
T
-50
°C
°C
A
T
-65
+150
stg
Notes: 3. Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
4. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SRC
latch-up.
5. The maximum over/under voltage is limited by the input current.
4
DS608PP2
CS5342
ANALOG CHARACTERISTICS (CS5342-CZZ) Test conditions (unless otherwise specified):
Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.
Parameter
Symbol
Min
Typ
Max
Unit
VA = 3.3 V
Single Speed Mode
Fs = 48 kHz
A-weighted
unweighted
Dynamic Range
96
93
102
99
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 6) THD+N
-1 dB
-
-
-
-95
-79
-39
-89
-
-
dB
dB
dB
-20 dB
-60 dB
Double Speed Mode
Fs = 96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Dynamic Range
96
93
-
102
99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 6)
-1 dB
THD+N
-
-
-
-
-95
-79
-39
-87
-89
dB
dB
dB
dB
-20 dB
-60 dB
-1 dB
-
-
-
40 kHz bandwidth
Quad Speed Mode (Note 2)
Dynamic Range
Fs = 192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
96
93
-
102
99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 6)
-1 dB
THD+N
-
-
-
-
-95
-79
-39
-87
-89
dB
dB
dB
dB
-20 dB
-60 dB
-1 dB
-
-
-
40 kHz bandwidth
VA = 5.0 V
Single Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
99
96
105
102
-
-
dB
dB
Total Harmonic Distortion + Noise
(Note 6) THD+N
-1 dB
-
-
-
-98
-82
-42
-92
-
-
dB
dB
dB
-20 dB
-60 dB
Double Speed Mode
Fs = 96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Dynamic Range
99
96
-
105
102
99
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 6)
-1 dB
THD+N
-
-
-
-
-98
-82
-42
-95
-92
dB
dB
dB
dB
-20 dB
-60 dB
-1 dB
-
-
-
40 kHz bandwidth
DS608PP2
5
CS5342
Quad Speed Mode (Note 2)
Fs = 192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Dynamic Range
99
96
-
105
102
99
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise
(Note 6)
-1 dB
THD+N
-
-
-
-
-98
-82
-42
-95
-92
dB
dB
dB
dB
-20 dB
-60 dB
-1 dB
-
-
-
40 kHz bandwidth
Dynamic Performance for All Modes
Interchannel Isolation
-
90
-
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Error
-
0.1
-
-
3
-
dB
%
-3
Gain Drift
-
100
ppm/°C
Analog Input Characteristics
Full-scale Input Voltage
0.54*VA
18
0.56*VA
-
Vpp
0.58*VA
-
Input Impedance
kΩ
Note: 6. Referred to the typical full-scale input voltage
6
DS608PP2
CS5342
DIGITAL FILTER CHARACTERISTICS
Parameter (Note 7)
Symbol Min
Typ
Max
Unit
Single Speed Mode
Passband
(-0.1 dB)
0
-0.1
-
0.4896
Fs
dB
Fs
dB
s
Passband Ripple
Stopband
-
0.035
0.5688
70
-
-
-
-
-
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
t
t
t
-
12/Fs
gd
gd
gd
Double Speed Mode
Passband
(-0.1 dB)
0
-0.1
0.5604
69
-
0.4896
Fs
dB
Fs
dB
s
Passband Ripple
Stopband
-
0.058
-
-
-
-
-
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
-
9/Fs
Quad Speed Mode (Note 2)
Passband
(-0.1 dB)
0
-0.1
0.5000
60
-
0.2604
Fs
dB
Fs
dB
s
Passband Ripple
Stopband
-
0.058
-
-
-
-
-
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
-
5/Fs
High Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB
-
1
20
-
-
Hz
Hz
(Note 7)
(Note 7)
Phase Deviation
Passband Ripple
Filter Settling Time
@ 20 Hz
-
-
10
-
-
Deg
dB
s
0
5
10 /Fs
Note: 7. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 1 to 12) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
DS608PP2
7
CS5342
0
0
-10
-10
-20
-20
-30
-40
-30
-40
-50
-60
-50
-60
-70
-80
-70
-80
-90
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
0.0
0 .1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Fre quency (norm alize d to Fs)
Freque ncy (norm alize d to Fs )
Figure 1. Single Speed Stopband Rejection
Figure 2. Single Speed Stopband Rejection (detail)
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0
0.05
0.1 0.15
0.2
0.25 0 .3 0.35 0.4
0.45
0.5
0 .45 0.4 6 0.47 0.48 0.49 0.5
0.51 0.52 0.53 0 .54 0.55
Fre quency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 3. Single Speed Transition Band (detail)
Figure 4. Single Speed Passband Ripple
0
0
-10
-10
-20
-20
-30
-40
-30
-40
-50
-60
-50
-60
-70
-80
-70
-80
-90
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
0.0
0 .1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Fre quency (norm alize d to Fs)
Freque ncy (norm alize d to Fs )
Figure 5. Double Speed Stopband Rejection
Figure 6. Double Speed Stopband Rejection (detail)
DS608PP2
8
CS5342
0
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0 .46
0 .47
0.48
0.49
0.50
0.51
0.52
0 .00 0.05 0.10 0.15 0 .20 0.25 0.30 0.35 0.40 0.45 0.50
Fre quency (norm alized to Fs)
Fre quency (norm alized to Fs)
Figure 7. Double Speed Transition Band (detail)
Figure 8. Double Speed Passband Ripple
0
0
-10
-10
-20
-20
-30
-40
-30
-40
-50
-60
-50
-60
-70
-80
-70
-80
-90
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
0.0
0 .1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Fre quency (norm alize d to Fs)
Fre quency (norm alize d to Fs)
Figure 9. Quad Speed Stopband Rejection
Figure 10. Quad Speed Stopband Rejection (detail)
0
-1
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.10
0 .15
0.20
0.25
0.30
0 .35
0.40
0.45
0.50
Fre quency (norm alized to Fs)
0.00 0.03 0.05 0.08
0.20 0.23 0.25 0.28
Fre que0n.1c0y 0(.n13or0m.15al0iz.1e8 d to Fs )
Figure 11. Quad Speed Transition Band (detail)
Figure 12. Quad Speed Passband Ripple
DS608PP2
9
CS5342
DC ELECTRICAL CHARACTERISTICS (GND = 0 V, all voltages with respect to 0 V.
MCLK=18.432 MHz; Master Mode; refer to Note 2)
Parameter
Symbol
Min
Typ
Max
Unit
DC Power Supplies:
Positive Analog
Positive Digital
Positive Logic
VA
VD
VL
3.14
3.14
2.38
-
-
-
5.25
5.25
5.25
V
V
V
Power Supply Current
(Normal Operation)
VA = 5 V
VA = 3.3 V
VL,VD = 5 V
VL,VD = 3.3 V
I
I
I
I
-
-
-
-
21
18.2
15
23.1
20
16.5
10
mA
mA
mA
mA
A
A
D
D
9
Power Supply Current
(Power-down Mode) (Note 8)
VA = 5 V
VL,VD=5 V
I
I
-
-
1.5
0.4
-
-
mA
mA
A
D
-
-
-
-
-
-
180
90
9.5
198
100
-
mW
mW
mW
Power Consumption
(Normal Operation)
VL, VD, VA = 5 V
VL, VD, VA = 3.3 V
(Power-Down Mode)
PSRR
-
65
-
dB
Power Supply Rejection Ratio (1 kHz)
(Note 9)
V Nominal Voltage
Output Impedance
-
-
VA÷2
-
-
V
kΩ
Q
25
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
-
-
VA
36
0.01
-
-
-
V
kΩ
mA
Notes: 8. Power-down Mode is defined as RST = Low with all clocks and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the “Typical Connection
Diagram”.
DIGITAL CHARACTERISTICS
Parameter
Symbol
Min
70%
-
Typ
Max
Units
High-level Input Voltage
Low-level Input Voltage
(% of VL)
(% of VL)
(% of VL)
V
-
-
-
-
30%
-
V
V
V
IH
V
IL
V
70%
High-level Output Voltage at I = 100 µA
OH
o
V
I
-
-
-
-
15%
10
V
Low-level Output Voltage at I =100 µA
(% of VL)
OL
in
o
Input Leakage Current
µA
THERMAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
-
Max
135
-
Unit
°C
°C/W
Allowable Junction Temperature
-
-
Junction-to-ambient Thermal Impedance
θJA
75
10
DS608PP2
CS5342
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL, C = 20 pF)
L
Parameter
Symbol
Min
Typ
Max
Unit
MCLK Specifications
MCLK Period
t
26
52
40
-
-
-
31
1303
60
ns
ns
%
clkw
MCLK Pulse Duty Cycle
Master Mode
SCLK falling to LRCK
SCLK falling to SDOUT valid
SCLK Duty Cycle
t
-20
-
-
-
20
32
ns
ns
mslr
t
sdo
Single-Speed
Double-Speed
Quad-Speed
-
-
-
50
50
33
-
-
-
%
%
%
Slave Mode
Single Speed*
LRCK Duty Cycle
40
290
45
10
5
-
-
-
-
-
-
60
-
%
ns
%
SCLK Period
t
t
t
sclkw
SCLK Duty Cycle
55
-
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Double Speed*
t
t
ns
ns
ns
stp
-
hld
t
-20
20
slrd
LRCK Duty Cycle
40
193
45
10
5
-
-
-
-
-
-
60
-
%
ns
%
SCLK Period (Note 9)
SCLK Duty Cycle
sclkw
55
-
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Quad Speed* (Note 2)
LRCK Duty Cycle
t
t
ns
ns
ns
stp
-
hld
t
-20
20
slrd
40
104
40
10
5
-
-
-
-
-
-
60
-
%
ns
%
SCLK Period (Note 9)
SCLK Duty Cycle
sclkw
50
-
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
t
t
ns
ns
ns
stp
-
hld
t
-8
8
slrd
* For a description of Speed Modes, please refer to Table 1 on page 15
Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.
DS608PP2
11
CS5342
LRCK input
SCLK input
LRCK output
SCLK output
SDOUT
t
t
t
sclkw
mslr
slrd
t
t
t
hld
stp
sdo
MSB-1
MSB
MSB
MSB-1
SDOUT
Figure 13. Master Mode, Left Justified SAI
Figure 14. Slave Mode, Left Justified SAI
LRCK input
LRCK output
t
t
t
sclkw
slrd
mslr
SCLK input
SDOUT
SCLK output
SDOUT
t
t
t
hld
stp
sdo
MSB
MSB-1
MSB
2
2
Figure 15. Master Mode, I S SAI
Figure 16. Slave Mode, I S SAI
12
DS608PP2
CS5342
2
PIN DESCRIPTION
M0
MCLK
VL
SDOUT
GND
VD
SCLK
LRCK
M1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FILT+
REFGND
VA
AINR
VQ
AINL
RST
Pin Name
M0
#
Pin Description
1
16
Mode Selection (Input) - Determines the operational mode of the device.
M1
MCLK
VL
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Logic Power (Input) - Positive power for the digital input/output.
2
3
4
5
6
7
8
SDOUT
GND
VD
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
Ground (Input) - Ground reference. Must be connected to analog ground.
Digital Power (Input) - Positive power supply for the digital section.
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
SCLK
LRCK
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently
active on the serial audio data line.
RST
Reset (Input) - The device enters a low power mode when low.
9
AINL
AINR
Analog Input (Input) - The full scale analog input level is specified in the Analog Charac-
teristics specification table.
10
12
VQ
Quiescent Voltage (Output) - Filter connection for the internal quiescent
reference voltage.
11
VA
13
14
15
Analog Power (Input) - Positive power supply for the analog section.
REFGND
FILT+
Reference Ground (Output) - Ground reference for the internal sampling circuits.
Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits.
DS608PP2
13
CS5342
3
TYPICAL CONNECTION DIAGRAM
3.3V to 5V4
+
+
2.5V to 5V
µ
µ
1 F
0.1 F
+
µ
µ
1 F
0.1 F
2
3.3V to 5V4
µ
1 F
µ
Ω
5.1
µ
0.1 F
0.1 F
D
V
L
V
VA
FILT+
3
+
µ
µ
0.1 F
1 F
REFGND
VQ
µ
F
1 µ
0.1 F
+
RST
Power Down
and Mode
Settings
M0
M1
CS5342
1
VL or GND
A/D CONVERTER
10 kΩ
AINL
AINR
Audio Data
Processor
SDOUT
Analog Input Buffer
Figure 15
MCLK
LRCK
Timing Logic
and Clock
SCLK
1Pull-up to VL for I2S
3Capacitor value affects
Pull-down to GND for LJ
low frequency distortion
performance as described
in Section 4.8
2Resistor may only be
used if VD is derived from
VA. If used, do not drive any
other logic from VD
GND
4See Note 2 on page 4
Figure 17. Typical Connection Diagram
14
DS608PP2
CS5342
4 APPLICATIONS
4.1 Single, Double, and Quad Speed Modes
The CS5342 can support output sample rates from 2 kHz to 200 kHz. The proper speed mode can be determined
by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.
MCLK/LRCK
Speed Mode
Single Speed Mode
Ratio
768x
384x
384x
192x
192x
96x*
Output Sample Rate Range (kHz)
43 - 54
2 - 54
Double Speed Mode
Quad Speed Mode
86 - 108
50 - 108
172 - 200
100 - 200
* Quad Speed Mode, 96x only available in Master Mode.
Table 1. Speed Modes and the Associated Output Sample Rates (Fs)
4.2 Operation as Either a Clock Master or Slave
The CS5342 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are
outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK
pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master
or slave is made via the Mode pins as shown in Table 2.
M1 (Pin 16) M0 (Pin 1)
MODE
0
0
1
1
0
1
0
1
Clock Master, Single Speed Mode
Clock Master, Double Speed Mode
Clock Master, Quad Speed Mode
Clock Slave, All Speed Modes
Table 2. CS5342 Mode Control
DS608PP2
15
CS5342
4.2.1 Operation as a Clock Master
As a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from
the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18.
Single
Speed
÷ 256
÷ 128
÷ 64
00
Double
Speed
LRCK Output
(Equal to Fs)
01
10
Quad
Speed
÷ 1.5
÷ 3
0
1
MCLK
M[1:0]
00
Single
Speed
÷ 4
÷ 2
÷ 1
Auto-Select
Double
Speed
SCLK Output
01
10
Quad
Speed
Figure 18. CS5342 Master Mode Clocking
4.2.2 Operation as a Clock Slave
LRCK and SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and equal to 48x Fs or 64x Fs in Single-Speed Mode. In Double-
Speed and Quad-Speed Modes the serial clock must be derived synchronously from the master clock and equal to
48x Fs. Additionally, Quad-Speed Slave Mode is only specified for operation with a VA and VD at 5 V, 5%.
A unique feature of the CS5342 is the automatic selection of either Single, Double or Quad speed mode when op-
erating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond
to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200 kHz.
However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast
MCLK (768x, 384x, and 192x for Single, Double, and Quad Speed Modes respectively). Please refer to Table 1 on
page 15 for supported sample rate ranges.
16
DS608PP2
CS5342
4.2.3 Master Clock
The CS5342 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters. There is also
an internal MCLK divider which is automatically activated based on the frequency of the MCLK. Table 3 shows a list-
ing of the external MCLK/LRCK ratios that are required. Table 4 lists some common audio output sample rates and
the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with
a fast MCLK (768x, 384x, 192x for Single, Double, and Quad Speed Modes respectively).
Single Speed Mode
Double Speed Mode
Quad Speed Mode
MCLK/LRCK Ratio
384x, 768x
192x, 384x
96x*, 192x
* Quad Speed, 96x only available in Master Mode.
Table 3. Master Clock (MCLK) Ratios
SAMPLE RATE (kHz)
MCLK (MHz)
12.288
32
44.1
16.9344
33.8688
18.432
48
36.864
64
12.288
88.2
16.9344
33.8688
18.432
96
36.864
192
36.864
Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates
4.3 Serial Audio Interface
2
The CS5342 supports both I S and Left Justified serial audio formats. Upon start-up, the CS5342 will detect the logic
2
level on SDOUT (pin 4). A 10 kΩ pull-up resistor to VL is needed to select I S format, and a 10 kΩ pull-down resistor
to GND is needed to select Left Justified format. Please see Figures 13 through 16 on page 12, for more information
on the required timing for the two serial audio interface formats.
LRCK
SCLK
Left Channel
Right Channel
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
Figure 19. Left-Justified Serial Audio Interface
LRCK
SCLK
Left Channel
Right Channel
SDATA
23 22
9
8
7
6
5
4
3
2
1
0
23 22
9
8
7
6
5
4
3
2
1
0
23 22
2
Figure 20. I S Serial Audio Interface
DS608PP2
17
CS5342
4.4 Power-up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and config-
uration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies drop below the
minimum specified operating voltages to prevent power glitch related issues.
4.5 Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the
filter. However, there is no rejection for input signals which are multiples of the input sampling frequency
(n × 6.144 MHz), where n=0,1,2,... Refer to Figure 15 which shows the suggested filter that will attenuate any noise
energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The use of capac-
itors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can
degrade signal linearity.
634 Ω
VA
470 pF
COG
100 kΩ
91 Ω
4.7 uF
CS5342 AINL
AINL
100 kΩ
2200 pF
VA
100 kΩ
100 kΩ
4.7 uF
91 Ω
AINL
CS5342 AINL
2200 pF
COG
470 pF
634 Ω
Figure 21. CS5342 Recommended Analog Input Buffer
4.6 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5342 requires careful attention to power supply and grounding arrange-
ments if its potential performance is to be realized. Figure 17 shows the recommended power arrangements, with
VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from the system logic supply
or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from
VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being
the nearest. All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid un-
wanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be po-
sitioned to minimize the electrical path from FILT+ and REF_GND. The CDB5342 evaluation board demonstrates
the optimum layout and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only
to CMOS inputs.
18
DS608PP2
CS5342
4.7 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure
synchronous sampling, the MCLK and LRCK must be the same for all of the CS5342’s in the system.
4.8 Capacitor Size on the Reference Pin (FILT+)
The CS5342 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decou-
pling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor val-
ues used to optimize low frequency distortion performance. The THD+N curves in Figure 22 were measured with
VA = VD = VL = 5 V in Single-Speed Master Mode using a 1 kHz input tone of magnitude -1 dB Full-Scale.
1 uF
2.2 uF
3.3 uF
4.7 uF
5.6 uF
6.8 uF
10 uF
22 uF
47 uF
100 uF
Figure 22. CS5342 THD+N versus Frequency
DS608PP2
19
CS5342
5
PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not affect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
20
DS608PP2
CS5342
6 PACKAGE DIMENSIONS
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
NOM
--
0.004
MAX
0.043
0.006
0.037
0.012
0.201
0.256
0.177
--
MIN
--
NOM
--
--
MAX
1.10
0.15
0.95
0.30
5.10
6.50
4.50
--
--
0.002
0.03346
0.00748
0.193
0.248
0.169
--
0.05
0.85
0.19
4.90
6.30
4.30
--
0.0354
0.0096
0.1969
0.2519
0.1732
0.026 BSC
0.024
0.90
0.245
5.00
6.40
4.40
0.065 BSC
0.60
4°
2,3
1
1
0.020
0°
0.028
8°
0.50
0°
0.70
8°
4°
∝
JEDEC #: MO-153
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS608PP2
21
CS5342
7. REVISION HISTORY
Release
A1
Date
Changes
April 2003
July 2003
-Initial Advance Release.
A2
-Modify serial port timing specs.
-Add Applications section on speed mode detect.
PP1
August 2004
-Change 2700 pF capacitors to 2200 pF in analog input buffer diagram.
-Update Output Sample Range table.
-Add new Applications section about capacitor on FILT+ pin.
-Correct Max MCLK period under “Switching Characteristics.”
-Replace MCLK low/high timing specifications with duty cycle specification.
-Redefine slave mode timing specifications under “Switching Characteristics.”
-Add requirement of SCLK/LRCK = 48x in Double and Quad Speed Modes.
-Increase minimum VL specification from 1.7 V to 2.38 V.
-Specify VA and VD at 5 V, 5% for Quad-Speed Slave Mode.
-Reduce gain error specification under Analog Characteristics.
-Improve minimum and maximum specifications for full-scale input voltage.
-Initial Preliminary Release.
PP2
Aug 2004
Update to include lead-free device ordering information.
Table 5. Revision History
22
DS608PP2
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