CS5343_07_技术文档

CS5343/4

98 dB, 96 kHz, Multi-Bit Audio A/D Converter

Features

General Description

Advanced Multi-Bit ΔΣ Architecture

24-bit Conversion

The CS5343/4 is a complete analog-to-digital converter

for digital audio systems. It performs sampling, analog-

to-digital conversion, and anti-alias filtering, generating

24-bit values for both left and right inputs in serial form

at sample rates up to 108 kHz per channel.

Supports Audio Sample Rates Up to 108 kHz

98 dB Dynamic Range at 5 V

The CS5343/4 uses a 3rd-order, multi-bit Delta-Sigma

modulator followed by a digital filter, which removes the

need for an external anti-alias filter.

-92 dB THD+N at 5 V

Low-Latency Digital Filter

The CS5343/4 also features a high-impedance sam-

pling network which eliminates costly external

components such as op-amps.

High-Pass Filter to Remove DC Offsets

Single +3.3 V or +5 V Power Supply

Power Consumption < 40 mW at 3.3 V

Master or Slave Operation

The CS5343/4 is available in a 10-pin TSSOP package

for both Commercial (-40° to +85° C) and Automotive

grades (-40° to +105° C). The CDB5343 Customer

Demonstration Board is also available for device evalu-

ation and implementation suggestions. Please refer to

the “Ordering Information” on page 21 for complete

details.

Slave Mode Speed Auto-Detect

Master Mode Default Settings

256x or 384x MCLK/LRCK Ratio

CS5343 Supports I²S Audio Format

CS5344 Supports Left-Justified Audio Format

The CS5343/4 is ideal for audio systems requiring wide

dynamic range, negligible distortion and low noise, such

as set-top boxes, DVD-karaoke players, DVD record-

ers, A/V receivers, and automotive applications.

VA

3.3 V to 5 V

High-Z

Sampling

Network

Single-Ended

Analog Input

Low-Latency

Digital Filters

Master

Clock

Auto-detect

MCLK Divider

AINL

High-Pass

Filter

FILT+

VQ

Internal

Reference

Voltages

SCLK

LRCK

Slave Mode

Auto-detect

High-Z

Sampling

Network

Single-Ended

Analog Input

Low-Latency

Digital Filters

AINR

SDOUT

High-Pass

Filter

MARCH '07

DS687F1

http://www.cirrus.com

CS5343/4

TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 4

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5

RECOMMENDED OPERATING CONDITIONS ..................................................................................... 5

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 5

ANALOG CHARACTERISTICS - COMMERCIAL GRADE (-CZZ) ......................................................... 6

ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (-DZZ) ......................................................... 7

DIGITAL FILTER CHARACTERISTICS ................................................................................................ 8

DC ELECTRICAL CHARACTERISTICS ................................................................................................ 8

DIGITAL CHARACTERISTICS ............................................................................................................... 9

SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE ................................................................... 10

3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12

4. APPLICATIONS ................................................................................................................................... 13

4.1 Operation as Clock Master or Slave ............................................................................................... 13

4.1.1 Slave Mode Operation ........................................................................................................... 13

4.1.2 Master Mode Operation ......................................................................................................... 14

4.1.2.1 Master Mode Speed Selection ................................................................................... 14

4.1.3 Master Clock ......................................................................................................................... 14

4.2 Serial Audio Interface ..................................................................................................................... 15

4.3 Digital Interface ............................................................................................................................... 15

4.4 Analog Connections ....................................................................................................................... 15

4.4.1 Component Values ................................................................................................................ 16

4.5 Grounding and Power Supply Decoupling ...................................................................................... 16

4.6 Synchronization of Multiple Devices ............................................................................................... 17

5. FILTER PLOTS .................................................................................................................................... 17

6. PARAMETER DEFINITIONS ................................................................................................................ 19

7. PACKAGE DIMENSIONS .................................................................................................................... 20

THERMAL CHARACTERISTICS .......................................................................................................... 20

8. ORDERING INFORMATION ................................................................................................................ 21

9. REVISION HISTORY ............................................................................................................................ 21

LIST OF FIGURES

Figure 1. CS5343 I²S Serial Audio Interface.............................................................................................. 11

Figure 2. CS5344 Left-Justified Serial Audio Interface .............................................................................. 11

Figure 3. Typical Connection Diagram....................................................................................................... 12

Figure 4. CS5343 I²S Serial Audio Interface.............................................................................................. 15

Figure 5. CS5344 Left-Justified Serial Audio Interface .............................................................................. 15

Figure 6. CS5343/4 Analog Input Network................................................................................................. 15

Figure 7. CS5343/4 Example Analog Input Network.................................................................................. 16

Figure 8. Single-Speed Mode Stopband Rejection.................................................................................... 17

Figure 9. Single-Speed Mode Transition Band .......................................................................................... 17

Figure 10. Single-Speed Mode Transition Band (Detail)............................................................................ 17

Figure 11. Single-Speed Mode Passband Ripple ...................................................................................... 17

Figure 12. Double-Speed Mode Stopband Rejection................................................................................. 18

Figure 13. Double-Speed Mode Transition Band....................................................................................... 18

Figure 14. Double-Speed Mode Transition Band (Detail) .......................................................................... 18

Figure 15. Double-Speed Mode Passband Ripple..................................................................................... 18

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CS5343/4

LIST OF TABLES

Table 1. Master/Slave Mode Selection ...................................................................................................... 13

Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode......................................... 13

Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode....................................... 14

Table 4. Speed Mode Selection in Master Mode ....................................................................................... 14

Table 5. Common MCLK Frequencies in Master and Slave Modes .......................................................... 14

Table 6. Analog Input Design Parameters ................................................................................................. 16

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CS5343/4

1. PIN DESCRIPTIONS

VA

SDOUT

SCLK

LRCK

MCLK

FILT+

10

9

1

2

3

4

5

GND

AINR

8

VQ

7

AINL

6

Pin Name Pin #

Pin Description

Serial Audio Data Output (Output) - Output for two’s complement serial audio data. Also selects Master

or Slave Mode; See Section 4.1 on page 13 for details.

SDOUT

SCLK

1

2

3

Serial Clock (Input/Output) - Serial clock for the serial audio interface.

Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

LRCK

MCLK

FILT+

4

5

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

AINL

AINR

6

8

Analog Input (Input) - The full-scale analog input level is specified in the Analog Characteristics specifi-

cation table.

VQ

7

9

Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

Ground (Input) - Ground reference. Must be connected to analog ground.

GND

VA

10 Power (Input) - Positive power supply for the digital and analog sections.

4

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CS5343/4

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

GND = 0 V, all voltages with respect to GND.

Parameter

Symbol

Min

Typ

Max

Unit

Power Supplies

3.1

4.75

3.3

5.0

3.5

5.25

V

VA

Ambient Operating Temperature

Commercial (-CZZ)

Automotive (-DZZ)

T_AC

T_AD

-40

-

85

105

°C

ABSOLUTE MAXIMUM RATINGS

GND = 0 V, all voltages with respect to GND. (Note 1)

Parameter

DC Power Supplies

Symbol

VA

Min

Max

Unit

V

-0.3

-10

-0.7

-50

-65

+6.0

+10

Input Current

(Note 2)

(Note 3)

I_in

mA

V

Input Voltage

V_IN

VA+0.7

+115

+150

Ambient Operating Temperature (Power Applied)

Storage Temperature

T_A

°C

T_stg

Notes:

1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

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CS5343/4

ANALOG CHARACTERISTICS - COMMERCIAL GRADE (-CZZ)

Test conditions (unless otherwise specified): T = 25° C; Input test signal is a 997 Hz sine wave through recom-

A

mended inputs as seen in Figure 6 on page 15; source impedance less than or equal to 2.5 kΩ; valid with FILT+

and VQ components as shown in Figure 3 on page 12; measurement bandwidth is 10 Hz to 20 kHz; Fs = 48 kHz

or 96 kHz.

Dynamic Performance for Commercial Grade

VA = 3.3 V

Typ

VA = 5.0 V

Typ

Symbol

Min

Max

Min

Max

Unit

Dynamic Range

A-weighted

unweighted

91

88

94

91

-

95

92

98

95

-

dB

Total Harmonic Distortion + Noise

(Note 4)

-1 dB

-

-89

-71

-31

-86

-

-92

-75

-35

-89

-

dB

THD+N

-20 dB

-60 dB

VA = 3.3 V and VA = 5.0 V

Dynamic Performance for Commercial Grade

Min

Typ

Max

Unit

Interchannel Isolation

DC Accuracy

-

90

-

dB

Interchannel Gain Mismatch

Gain Error

-

-3

-

0.1

+3

-

dB

%

-

Gain Drift

100

ppm/°C

Analog Input Characteristics

Full-scale Input Voltage

Input Impedance

VA = 3.3 V nom

VA = 5 V nom

0.560*VA

0.552*VA

-

0.568*VA

0.559*VA

7.5

0.575*VA

0.567*VA

-

Vpp

MΩ

Notes:

4. Referred to the typical full-scale input voltage

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CS5343/4

ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (-DZZ)

Test conditions (unless otherwise specified): T = -40° C to 85° C; Input test signal is a 997 Hz sine wave through

A

recommended inputs as seen in Figure 6 on page 15; source impedance less than or equal to 2.5 kΩ; valid with

FILT+ and VQ components as shown in Figure 3 on page 12; measurement bandwidth is 10 Hz to 20 kHz;

Fs = 48 kHz or 96 kHz.

Dynamic Performance for Automotive Grade

VA = 3.1 to 3.5 V

VA = 4.75 to 5.25 V

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

Dynamic Range

A-weighted

unweighted

86

83

94

91

-

90

87

98

95

-

dB

Total Harmonic Distortion + Noise

(Note 5)

-1 dB

-

-88

-71

-31

-76

-

-91

-75

-35

-84

-

dB

THD+N

-20 dB

-60 dB

VA = 3.1 V to 3.5 V and VA = 4.75 V to 5.25 V

Dynamic Performance for Automotive Grade

Min

Typ

Max

Unit

Interchannel Isolation

DC Accuracy

-

90

-

dB

Interchannel Gain Mismatch

Gain Error

-

-3

-

0.1

+3

-

dB

%

-

Gain Drift

100

ppm/°C

Analog Input Characteristics

Full-scale Input Voltage

Input Impedance

VA = 3.1 V to 3.5 V

0.523*VA

0.543*VA

-

0.567*VA

0.560*VA

7.5

0.612*VA

0.573*VA

-

Vpp

MΩ

VA = 4.75 V to 5.25 V

Notes:

5. Referred to the typical full-scale input voltage

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CS5343/4

DIGITAL FILTER CHARACTERISTICS

Parameter

Symbol

Min

0

Typ

Max

Unit

Fs

Passband

(-0.1 dB)

-

0.489

Passband Ripple

Stopband

-0.025

0.560

69

0.025

dB

-

Fs

Stopband Attenuation

Single-Speed Mode

dB

Fs = 4 - 54 kHz

Total Group Delay (Fs = Output Sample Rate)

t_gd

-

12/Fs

9/Fs

-

s

Double-Speed Mode

Fs = 86 - 108 kHz

Total Group Delay (Fs = Output Sample Rate)

High-Pass Filter Characteristics

t_gd

Frequency Response

-3.0 dB

1

20

-

Hz

-0.13 dB

(Note 6)

Phase Deviation

Passband Ripple

@ 20 Hz

-

10

-

Deg

dB

0

Notes:

6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.

DC ELECTRICAL CHARACTERISTICS

GND = 0 V, all voltages with respect to 0 V. MCLK=12.288 MHz; Master Mode.

VA = 3.3 V

VA = 5.0 V

Parameter

Symbol Min Typ Max Min Typ

Max Unit

Power Supply Current

Power Consumption

(Normal Operation)

I_A

-

11

10

15

-

12

40

17

-

mA

uA

(Power-Down Mode) (Note 7)

(Normal Operation)

(Power-Down Mode) (Note 7)

-

36

<1

50

-

60

<1

85

-

mW

Parameter

Symbol

Min

Typ

65

Max

Unit

PSRR

-

dB

Power Supply Rejection Ratio (1 kHz)

(Note 8)

V_QNominal Voltage

Output Impedance

-

0.44xVA

25

-

V

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

-

VA

220

2.5

-

V

kΩ

uA

Notes:

7. Device enters power-down mode when MCLK is held static.

8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

8

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CS5343/4

DIGITAL CHARACTERISTICS

Parameter

High-Level Input Voltage

Symbol

V_IH

Min

60

-

Typ

Max

Units

%

(% of VA)

-

Low-Level Input Voltage

V_IL

30

%

High-Level Output Voltage at I_o= 500 μA

(% of VA)

V_OH

70

-

%

V_OL

I_in

-

15

10

%

Low-Level Output Voltage at I_o=500 μA

Input Leakage Current

-10

μA

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CS5343/4

SYSTEM CLOCKING AND SERIAL AUDIO INTERFACE

Logic “0” = GND = 0 V; Logic “1” = VA, C = 20 pF.

L

Parameter

Symbol

Min

Typ

Max

Unit

Master Mode

MCLK Period

(Double-Speed, 384x Mode)

(Double-Speed, 192x Mode)

(Double-Speed, 256x Mode)

(Double-Speed, 128x Mode)

(Single-Speed, 768x Mode)

(Single-Speed, 384x Mode)

(Single-Speed, 512x Mode)

(Single-Speed, 256x Mode)

t_clkw

24

48

36

72

24

48

36

72

40

-

30

60

ns

%

-

45

-

90

-

325

651

488

976

60

-

MCLK Duty Cycle

50

Output Sample Rate

(Single-Speed)

(Double-Speed)

4

86

-

54

108

kHz

Fs

LRCK Duty Cycle

-

50

-

%

SCLK Duty Cycle

-

SDOUT valid before SCLK rising

SDOUT valid after SCLK rising

SCLK falling to LRCK edge

Slave Mode

t_stp

t_hld

t_slrd

10

40

-20

-

ns

-

20

MCLK Period

(Double-Speed, 384x Mode)

(Double-Speed, 192x Mode)

(Double-Speed, 256x Mode)

(Double-Speed, 128x Mode)

(Single-Speed, 768x Mode)

(Single-Speed, 384x Mode)

(Single-Speed, 512x Mode)

(Single-Speed, 256x Mode)

t_clkw

24

48

36

72

24

48

36

72

40

-

30

60

ns

%

-

45

-

90

-

325

651

488

976

60

-

MCLK Duty Cycle

Input Sample Rate

50

(Single-Speed)

(Double-Speed)

4

86

-

54

108

kHz

Fs

LRCK Duty Cycle

SCLK Period

40

50

60

-

%

t_sclkw

1

-

ns

------------------

64 × Fs

SCLK Duty Cycle

45

10

50

-

55

-

%

ns

SDOUT valid before SCLK rising

SDOUT valid after SCLK rising

SCLK falling to LRCK edge

t_stp

t_hld

t_slrd

40

-

-20

-

20

10

DS687F1

CS5343/4

t_slrd

LRCK

SCLK

t_sclkw

SDOUT

MSB

MSB-1

t_stp

t_hld

Figure 1. CS5343 I²S Serial Audio Interface

t^slrd

LRCK

SCLK

t_sclkw

SDOUT

MSB

MSB-1

t_stp

t_hld

Figure 2. CS5344 Left-Justified Serial Audio Interface

DS687F1

11

CS5343/4

3. TYPICAL CONNECTION DIAGRAM

3.3 V to 5 V

0.1 µF 1 µF

VA or

GND

10

VA

5

FILT+

CS5343/4

1 µF 0.1 µF

9

7

GND

VQ

1

SDOUT

2

Audio

SCLK

Processor/

System

3

LRCK

6

AINL

AINR

Clocks

Analog Input

Conditioning

4

MCLK

See Figure 6 on

page 15

1

Pull-up to VA for Master Mode

Pull-down to GND for Slave Mode

8

2

Optional pull-up resistor for configur-

ing clocks in Master Mode as

described in the “Master Mode Speed

Selection” section on page 14

Figure 3. Typical Connection Diagram

12

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CS5343/4

4. APPLICATIONS

4.1

Operation as Clock Master or Slave

The CS5343/4 supports operation as either a clock master or slave. As a clock master, the left/right and

serial clocks are synchronously generated on-chip and output on the LRCK and SCLK pins, respectively.

As a clock slave, the LRCK and SCLK pins are always inputs and require external generation of the left/right

and serial clocks. The selection of clock master or slave is made via a 10 kΩ pull-up resistor from SDOUT

to VA for Master Mode selection or via a 10 kΩ pull-down resistor from SDOUT to GND for Slave Mode se-

lection, as shown in Table 1.

Mode

Selection

Master Mode

Slave Mode

10 kΩ pull-up resistor from SDOUT to VA

10 kΩ pull-down resistor from SDOUT to GND

Table 1. Master/Slave Mode Selection

4.1.1

Slave Mode Operation

A unique feature of the CS5343/4 is the automatic selection of either Single- or Double-Speed Mode when

acting as a clock slave. The auto-mode selection feature supports all standard audio sample rates from

4 to 108 kHz. Please refer to Table 2 for supported sample rate ranges in Slave Mode.

MCLK/LRCK

Ratio

SCLK/LRCK

Ratio

Speed Mode

Input Sample Rate Range (kHz)

256x

512x

384x

768x

128x

256x

192x

384x

64

4 - 54

Single-Speed Mode

48, 64

64

4 - 54

86 - 108

64

Double-Speed Mode

48, 64

Table 2. Speed Modes and the Associated Sample Rates (Fs) in Slave Mode

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CS5343/4

4.1.2

Master Mode Operation

As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip. Table 3 shows the

available sample rates and associated clock ratios in Master Mode.

MCLK/LRCK

Ratio

SCLK/LRCK

Ratio

Speed Mode

Input Sample Rate Range (kHz)

256x

512x

384x

768x

128x

256x

192x

384x

64

4 - 54

Single-Speed Mode

4 - 54

86 - 108

Double-Speed Mode

Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode

4.1.2.1 Master Mode Speed Selection

During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the

output clock ratio. The LRCK pin is pulled low internally to select Single-Speed Mode by default, but Dou-

ble-Speed Mode is accessed with a 10 kΩ pull-up resistor from LRCK to VA as shown in Table 4. Simi-

larly, the SCLK pin is internally pulled-low by default to select a 256x/512x MCLK/LRCK ratio, but a

MCLK/LRCK ratio of 348x/768x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in

Table 4. Following the power-up routine, the LRCK and SCLK pins become clock outputs.

Resistor Option

Clock Configuration

Single-Speed Mode (default)

Double-Speed Mode

Internal Pull-Down to GND (100 kΩ)

External Pull-Up to VA (10 kΩ)

Internal Pull-Down to GND (100 kΩ)

External Pull-Up to VA (10 kΩ)

LRCK

128x/256x/512x MCLK/LRCK (default)

192x/384x/768x MCLK/LRCK

SCLK

Table 4. Speed Mode Selection in Master Mode

4.1.3

Master Clock

The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.

There is an internal automatic MCLK divider which is activated based on the input frequency of MCLK.

This divider selection allows the high and low MCLK speeds in a given speed mode (i.e. 256x and 512x

in SSM). Table 4 lists some common audio output sample rates and the required MCLK frequency.

Master and Slave Mode

MCLK(MHz)

MCLK (MHz)

Sample Rate (kHz)

Speed Mode

256x

512x

384x

768x

32

44.1

48

SSM

8.912

11.289

12.288

16.384

22.579

24.576

12.288

16.934

18.432

24.576

33.868

36.864

MCLK(MHz)

MCLK (MHz)

Sample Rate (kHz)

Speed Mode

128x

11.289

12.288

256x

22.579

24.576

192x

384x

88.2

96

DSM

16.934

18.432

33.868

36.864

Table 5. Common MCLK Frequencies in Master and Slave Modes

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CS5343/4

4.2

Serial Audio Interface

The CS5343 output is serial data in I²S audio format and the CS5344 output is serial data in Left-Justified

audio format. Figures 4 and 5 show the I²S and Left-Justified data relative to SCLK and LRCK. Additionally,

Figures 1 and 2 display more information on the required timing for the serial audio interface format. For an

overview of serial audio interface formats, please refer to Cirrus Application Note AN282.

LRCK

Left Channel

Right Channel

SCLK

SDATA

23 22

9

8

7

6

5

4

3

2

1

0

23 22

9

8

7

6

5

4

3

2

1

0

23 22

Figure 4. CS5343 I²S Serial Audio Interface

LRCK

SCLK

Left Channel

Right Channel

SDATA

23 22

9

8

7

6

5

4

3

2

1

0

23 22

9

8

7

6

5

4

3

2

1

0

23 22

Figure 5. CS5344 Left-Justified Serial Audio Interface

4.3

Digital Interface

VA supplies power to both the analog and digital sections of the ADC, and also powers the serial port. Con-

sequently, the digital interface logic level must equal VA to within the limits specified under “Digital Charac-

teristics” on page 9.

4.4

Analog Connections

The analog modulator samples the input signal at half of the internal master clock rate, or 6.144 MHz when

MCLK = 12.288 MHz. The digital filter will reject signals within the stopband of the filter. However, there is

^{no rejection for input signals which are multiples of the input sampling frequency (n}× 6.144 MHz), where

n=0,1,2,... Refer to Figure 6 which shows the recommended topology of the analog input network. The ex-

ternal shunt capacitor and internal input impedance form a single-pole RC filter to provide the appropriate

filtering of noise at the modulator sampling frequency. Additionally, the 180 pF capacitor acts as a charge

source for the internal sampling circuits. Capacitors of NPO or other high-quality dielectric will produce the

best results while capacitors with a large voltage coefficient (such as general-purpose ceramics) can de-

grade signal linearity.

CS5343/4

1 µF

R1

Input

AIN

180pF

C0G

R2

Figure 6. CS5343/4 Analog Input Network

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CS5343/4

4.4.1

Component Values

Three parameters determine the values of resistors R1 and R2 as shown in Figure 6: source impedance,

attenuation, and input impedance. Table 6 shows the design equation used to determine these values.

•

Source Impedance: Source impedance is defined as the impedance as seen from the ADC looking

back into the signal network. The ADC achieves optimal THD+N performance with a source imped-

ance less than or equal to 2.5 kΩ.

•

Attenuation: The required attenuation factor depends on the magnitude of the input signal. The full-

scale input voltage is specified under “Analog Characteristics - Commercial Grade (-CZZ)” on page 6.

The user should select values for R1 and R2 such that the magnitude of the incoming signal multiplied

by the attenuation factor is less than or equal to the full-scale input voltage of the device.

•

Input Impedance: Input impedance is the impedance from the signal source to the ADC analog input

pins, including the ADC. Because the ADC’s input impedance (see the “Analog Characteristics - Com-

mercial Grade (-CZZ)” table on page 6) is several orders of magnitude larger than the resistor values

typically used for the input attenuator, its contribution can be neglected when calculating the input im-

pedance. Table 6 shows the input parameters and the associated design equations for the input at-

tenuator.

(R1 × R2)

Source Impedance

------------------------

R1 + R2

(R2)

Attenuation Factor

Input Impedance

------------------------

(R1 + R2)

Table 6. Analog Input Design Parameters

Figure 7 illustrates an example configuration using two 4.99 kΩ resistors in place of R1 and R2. Based on

the discussion above, this circuit provides an optimal interface for both the ADC and the signal source.

First, consumer equipment frequently requires an input impedance of 10 kΩ, which the 4.99 kΩ resistors

provide. Second, this circuit will attenuate a typical line level voltage, 2 Vrms, to the full-scale input of the

ADC, 1 Vrms when VA = 5 V. Finally, at 2.5 kΩ, the source impedance optimizes analog performance of

the ADC.

CS5343/4

4.99 kΩ

1 µF

Input

AIN

180pF

C0G

Figure 7. CS5343/4 Example Analog Input Network

4.5

Grounding and Power Supply Decoupling

As with any high-resolution converter, designing with the CS5343/4 requires careful attention to power sup-

ply and grounding arrangements if its potential performance is to be realized. Figure 3 shows the recom-

mended power arrangements, with VA connected to a clean supply. Decoupling capacitors should be as

near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially

clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the mod-

ulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize

the electrical path from FILT+ to GND. The CDB5343 evaluation board demonstrates the optimum layout

and power supply arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS

inputs.

16

DS687F1

CS5343/4

4.6

Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To

ensure synchronous sampling, the MCLK, SCLK, and LRCK signals must be the same for all of the CS5343

and CS5344 devices in the system.

5. FILTER PLOTS

0

-10

0

-10

-20

-30

-40

-50

-20

-30

-40

-50

-60

-70

-60

-70

-80

-90

-100

-110

-120

-130

-140

-80

-90

-100

-110

-120

-130

-140

0.0

0.1

0.2

0.3

0.4

0.5 0.6

0.7 0.8

0.9

1.0

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Figure 8. Single-Speed Mode Stopband Rejection

Figure 9. Single-Speed Mode Transition Band

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Figure 10. Single-Speed Mode Transition Band (Detail)

Figure 11. Single-Speed Mode Passband Ripple

DS687F1

17

CS5343/4

0

-10

0

-10

-20

-30

-40

-50

-20

-30

-40

-50

-60

-70

-60

-70

-80

-90

-100

-110

-120

-130

-140

-80

-90

-100

-110

-120

-130

-140

0.0

0.1

0.2

0.3

0.4

0.5 0.6

0.7 0.8

0.9

1.0

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Figure 12. Double-Speed Mode Stopband Rejection

Figure 13. Double-Speed Mode Transition Band

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Figure 14. Double-Speed Mode Transition Band (Detail)

Figure 15. Double-Speed Mode Passband Ripple

18

DS687F1

CS5343/4

6. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with

a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This

technique ensures that the distortion components are below the noise level and do not affect the measure-

ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,

and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at

1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-

bels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog input for a full-scale digital output.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

DS687F1

19

CS5343/4

7. PACKAGE DIMENSIONS

10LD TSSOP (3 mm BODY) PACKAGE DRAWING (Note 1)

N

D

E1¹

c

E

A2

A

∝

A1

e

b

L

END VIEW

SEATING

PLANE

L1

SIDE VIEW

1

2

3

TOP VIEW

INCHES

MILLIMETERS

NOTE

DIM

A

MIN

--

NOM

--

MAX

0.0433

0.0059

0.0374

0.0118

0.0091

--

MIN

--

NOM

--

MAX

1.10

0.15

0.95

0.30

0.23

--

A1

A2

b

0

--

0

--

0.0295

--

0.75

0.15

0.08

--

0.0059

--

4, 5

2

c

0.0031

--

D

--

0.1181 BSC

0.1929 BSC

0.1181 BSC

0.0197 BSC

0.0236

3.00 BSC

4.90 BSC

3.00 BSC

0.50 BSC

0.60

E

--

E1

e

--

3

--

L

0.0157

--

0.0315

--

0.40

--

0.80

--

L1

µ

0.0374 REF

--

0.95 REF

--

0°

8°

0°

8°

Controlling Dimension is Millimeters

Notes:

1. Reference document: JEDEC MO-187

2. D does not include mold flash or protrusions, which is 0.15 mm max. per side.

3. E1 does not include inter-lead flash or protrusions, which is 0.15 mm max per side.

4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.

5. Exceptions to JEDEC dimension.

THERMAL CHARACTERISTICS

Parameter

Allowable Junction Temperature

Symbol

Min

Typ

Max

Unit

T_J

-

135

°C

Junction to Ambient Thermal Impedance

(4-layer PCB)

(2-layer PCB)

θ_JA-4

θ_JA-2

-

100

170

-

°C/W

20

DS687F1

CS5343/4

8. ORDERING INFORMATION

Product

Description

98 dB, Multi-Bit Audio

A/D Converter,

I²S Audio Format

98 dB, Multi-Bit Audio

A/D Converter,

I²S Audio Format

98 dB, Multi-Bit Audio

A/D Converter,

Package Pb-Free

Grade

Temp Range Container

Order #

CS5343-CZZ

Rail

CS5343

10-TSSOP

Yes

Commercial -40° to +85° C

Automotive -40° to +105° C

Commercial -40° to +85° C

Automotive -40° to +105° C

Tape & Reel CS5343-CZZR

Rail

Tape & Reel CS5343-DZZR

Rail CS5344-CZZ

Tape & Reel CS5344-CZZR

Rail CS5344-DZZ

Tape & Reel CS5344-DZZR

CDB5343

CS5343-DZZ

CS5343

CS5344

Left-Justified Audio Format

98 dB, Multi-Bit Audio

A/D Converter,

10-TSSOP

-

Yes

No

Left-Justified Audio Format

CDB5343 CS5343 Evaluation Board

-

9. REVISION HISTORY

Release

Changes

Corrected MCLK timing specifications on page 10

Corrected “Typical Connection Diagram” on page 12

A4

Corrected Table 3, “Speed Modes and the Associated Sample Rates (Fs) in Master Mode,” on page 14

Updated “Recommended Operating Conditions” on page 5

Updated specifications and limits for “Analog Characteristics - Commercial Grade (-CZZ)” on page 6

Updated specifications and limits for “Analog Characteristics - Automotive Grade (-DZZ)” on page 7

Corrected “Power Supply Current (Normal Operation)” on page 8

Increased specification for Slave-Mode “SDOUT valid after SCLK rising” on page 10

Corrected Section 4.1.2.1 on page 14

F1

Updated Section 4.1.3 on page 14

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject

to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale

supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third

parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,

copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-

sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent

does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE

IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-

VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD

TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED

IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA-

TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER

AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH

THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

DS687F1

21


型号：	CS5343_07
厂家：	CIRRUS LOGIC
描述：	98 dB, 96 kHz, Multi-Bit Audio A/D Converter 98分贝， 96千赫，多比特音频A / D转换器转换器
文件：	总21页 (文件大小：331K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS5343_07 [CIRRUS]

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