CS61535A-IP1 [CIRRUS]
T1/E1 LINE INTERFACE; T1 / E1线路接口
| 型号： | CS61535A-IP1 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | T1/E1 LINE INTERFACE |
| 文件： | 总48页 (文件大小：663K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS61535A
T1/E1 Line Interface
Features
General Description
The CS61535A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
Provides Analog PCM Line Interface
for T1 and E1 Applications
•
The device features a transmitter jitter attenuator mak-
ing it ideal for use in asynchronous multiplexor systems
with gapped transmit clocks. The CS61535A provides a
matched, constant impedance output stage to insure
signal quality on mismatched, poorly terminated lines.
Provides Line Driver, and Data and
Clock Recovery Functions
•
Transmit Side Jitter Attenuation
Starting at 6 Hz, with > 300 UI of Jitter
Tolerance
•
Both ICs use a digital Delay-Locked-Loop clock and
data recovery circuit which is continuously calibrated
from a crystal reference to provide excellent stability
and jitter tolerance.
Applications
Low Power Consumption
(typically 175 mW)
•
• Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross connect.
B8ZS/HDB3/AMI Encoders/Decoders
•
•
•
• Interfacing customer premises equipment to a CSU.
• Interfacing to E1 links.
14 dB of Transmitter Return Loss
Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous
Muxes
Ordering Information
CS61535A-IP1 28 Pin Plastic DIP
CS61535A-IL1 28 Pin PLCC (j-leads)
[ ] = Pin Function in
Extended Hardware Mode
(CLKE) (INT) (SDI) (SDO)
( ) = Pin Function in Host Mode
XTALIN XTALOUT MODE TAOS LEN0 LEN1 LEN2
TGND TV+
9
10
5
28
23
24
25
14
15
13
16
TTIP
2
TCLK
JITTER
ATTENUATOR
PULSE
SHAPER
CONTROL
3
4
TRING
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
LINE DRIVER
AMI,
B8ZS,
HDB3
LINE RECEIVER
19
RTIP
8
CLOCK &
DATA
CODER
20
17
7
RECOVERY
RRING
RPOS
[RDATA]
RNEG
LOOP
BACK
6
MTIP
SIGNAL
QUALITY
MONITOR
[RCODE]
MRING
[PCS]
DPM
[BPV]
DRIVER
MONITOR
18
11
26
27
1
12
21
22
[AIS]
RLOOP LLOOP
(CS) (SCLK)
ACLKI LOS
RV+ RGND
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
MAY ’96
DS40F2
1
Copyright Crystal Semiconductor Corporation 1996
(All Rights Reserved)
CS61535A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min
Max
Units
DC Supply
(referenced to RGND,TGND=0V)
RV+
TV+
-
-
6.0
(RV+) + 0.3
V
V
Input Voltage, Any Pin
Input Current, Any Pin
Ambient Operating Temperature
Storage Temperature
(Note 1)
(Note 2)
Vin
Iin
TA
RGND-0.3
-10
(RV+) + 0.3
V
10
85
mA
°C
°C
-40
Tstg
-65
150
WARNING:Operations at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Units
DC Supply
Ambient Operating Temperature
Power Consumption
(Note 3) RV+, TV+
TA
4.75
-40
5.0
25
5.25
85
V
°C
mW
mW
(Notes 4, 5)
(Notes 4, 6)
PC
PC
-
-
290
175
350
-
Power Consumption
Notes: 3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF load.
5. Assumes 100% ones density and maximum line length at 5.25V.
6. Assumes 50% ones density and 300ft. line length at 5.0V.
2
DS40F2
CS61535A
DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
Pins 1-4, 17, 18, 23-28
Low-Level Input Voltage
Pins 1-4, 17, 18, 23-28
(Notes 7, 8, 9)
(Notes 7, 8, 9)
(Notes 7, 8, 10)
(Notes 7, 8, 10)
VIH
VIL
2.0
-
-
-
-
-
0.8
-
V
V
V
High-Level Output Voltage (I
= -40 µA)
OUT
VOH
VOL
4.0
Pins 6-8, 11, 12, 25
Low-Level Output Voltage (I
= 1.6 mA)
OUT
Pins 6-8, 11, 12, 23, 25
-
-
-
-
-
-
-
0.4
±10
0.2
-
V
µA
V
V
V
Input Leakage Current (Except Pin 5)
Low-Level Input Voltage, Pin 5
High-Level Input Voltage, Pin 5
Mid-Level Input Voltage, Pin 5
VIL
VIH
VIM
-
(RV+) - 0.2
2.3
(Note 11)
2.7
Notes: 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40µA).
8. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output.
9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode.
10. Output drivers will drive CMOS logic levels into a CMOS load.
11. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
(Note 12)
-
6
-
Hz
T1 Jitter Attenuation in Remote Loopback
(Note 13)
Jitter Freq. [Hz]
10
100
500
1k
10k, 40k
Amplitude [UIpp]
10
10
10
5
3.0
20
35
40
40
6.0
30
35
50
50
-
-
-
-
-
dB
dB
dB
dB
dB
0.3
E1 Jitter Attenuation in Remote Loopback
(Note 14)
Jitter Freq. [Hz]
Amplitude [UIpp]
10
100
400
1k
1.5
1.5
1.5
1.5
0.2
3.0
20
30
35
35
6.0
32
43
50
50
-
-
-
-
-
dB
dB
dB
dB
dB
10k, 100k
Attenuator Input Jitter Tolerance
(Note 15)
12
23
-
UI
Notes: 12. Not production tested. Parameters guaranteed by design and characterization.
13. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of
measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000
Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 215-1 PRBS data pattern.
Crystal must meet specifcations in CXT6176/8192 datasheet.
14. Jitter measured at the demodulator output of an HP3785A using a measurement
bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 215-1 PRBS data pattern.
Crystal must meet specifications in CXT6176/8192 datasheet.
15. Output jitter increases significantly when attenuator input jitter tolerance is exceeded.
DS40F2
3
CS61535A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Transmitter
AMI Output Pulse Amplitudes
E1, 75 Ω
(Note 16)
(Note 17)
(Note 18)
(Note 19)
(Note 20)
2.14
2.7
2.7
2.37
3.0
3.0
2.6
3.3
3.3
3.6
V
V
V
V
E1, 120 Ω
T1, FCC Part 68
T1, DSX-1
2.4
3.0
E1 Zero (space) level (LEN2/1/0 = 0/0/0)
75Ω application
-0.237
-0.3
-
-
0.237
0.3
V
V
(Note 17)
(Note 18)
120Ω application
Recommended Output Load at TTIP and TRING
-
75
-
Ω
Jitter Added During Remote Loopback
10Hz - 8kHz
(Note 21)
-
-
-
-
0.005
0.008
0.010
0.015
0.02
0.025
0.025
0.05
UI
UI
UI
UI
8kHz - 40kHz
10Hz - 40kHz
Broad Band
Power in 2kHz band about 772kHz
Power in 2kHz band about 1.544MHz
(Notes 12, 16)
(Notes 12, 16)
12.6
-29
15
-38
17.9
-
dBm
dB
(referenced to power in 2kHz band at 772kHz)
Positive to Negative Pulse Imbalance
T1, DSX-1
(Notes 12, 16)
-
-5
-5
0.2
-
-
0.5
5
5
dB
%
%
E1 amplitude at center of pulse
E1 pulse width at 50% of nominal amplitude
Transmitter Return Loss
(Notes 12, 16, 22)
8
14
10
-
-
-
-
-
-
dB
dB
dB
51 kHz to 102 kHz
102 kHz to 2.048 MHz
2.048 MHz to 3.072 MHz
Transmitter Short Circuit Current
(Notes 12, 23)
-
-
50
mA RMS
Notes: 16. Using a 0.47 µF capacitor in series with the primary of a transformer recommended
in the Applications Section.
17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a
75 Ω load for line length setting LEN2/1/0 = 0/0/0.
18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a
120 Ω load for line length setting LEN2/1/0 = 0/0/0.
19. Amplitude measured at the transformer (CS61535A-1:1.15) output across a
100 Ω load for line length setting LEN2/1/0 = 0/1/0.
20. Amplitude measured across a 100 Ω load at the DSX-1 cross-connect for line length settings
LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 AWG ABAM equivalent cable
specified in Table 3. The CS61535A requires a 1:1.15 transformer.
21. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
22. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and
z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0
and a 1:1 transformer terminated with a 75Ω load, or a 1:1.26 transformer terminated with a
120Ω load.
23. Measured broadband through a 0.5 Ω resistor across the secondary of a 1:1.26 transformer
during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0.
4
DS40F2
CS61535A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Driver Performance Monitor
MTIP/MRING Sensitivity:
Differential Voltage Required for Detection
-
0.60
-
V
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
-
50k
-
-
-
Ω
dB
-13.6
Data Decision Threshold
T1, DSX-1
60
53
45
65
65
50
70
77
55
% of peak
% of peak
% of peak
(Note 24)
(Note 25)
(Note 26)
T1, DSX-1
T1, FCC Part 68 and E1
Data Decision Threshold
T1
E1
-
-
65
50
-
-
% of peak
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
10kHz - 100kHz
2kHz
(Note 27)
0.4
6.0
300
-
-
-
-
-
-
UI
UI
UI
10Hz and below
Loss of Signal Threshold
(Note 28)
0.25
0.30
0.50
V
Notes: 24. For input amplitude of 1.2 Vpk to 4.14 Vpk.
25. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
26. For input amplitude of 1.05 Vpk to 3.3 Vpk.
27. Jitter tolerance increases at lower frequencies. See Figure 11.
28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and
RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data
decision threshold. The analog input squelch circuit operates when the input signal amplitude above
ground on the RTIP and RRING pins falls within the squelch range long enough for the internal
slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on
RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses
greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones
density reaches 12.5% (based upon 175 bit periods starting with a one and containing
less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993.
DS40F2
5
CS61535A
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
(Note 29)
fc
-
40
-
-
-
6.176000
-
60
-
-
-
MHz
%
MHz
%
%
t
pwh3/tpw3
faclki
pwh1/tpw1
-
(Note 30)
(Notes 31, 32)
1.544
78
29
t
RCLK Cycle Width
(Note 32)
tpw1
tpwh1
tpwl1
320
130
100
648
190
458
980
240
850
ns
ns
ns
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
TCLK Frequency
(Note 33)
(Note 33)
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
-
-
25
25
150
150
150
150
150
150
-
-
-
-
85
85
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
-
(Note 34)
(Note 35)
(Note 31)
(Note 34)
(Note 35)
(Note 31)
274
274
274
274
274
274
1.544
-
-
TCLK Pulse Width
(Notes 12, 31, 34, 36, 37)
(Notes 35, 36, 37)
80
150
-
-
500
500
Notes: 29. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
30. ACLKI provided by an external source or TCLK, but not RCLK.
31. Hardware Mode, or Host Mode (CLKE = 0).
32. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case
jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
33. At max load of 1.6 mA and 50 pF.
34. Host Mode (CLKE = 1).
35. Extended Hardware Mode.
36. The maximum TCLK burst rate is 5 MHz and tpw2(min) = 200 ns. The maximum gap size that can
be tolerated on TCLK is 12 VI.
37. The transmitted pulse width does not depend on the TCLK duty cycle.
t
pw1
EXTENDED
HARDWARE
MODE OR
RCLK
HOST MODE
(CLKE = 1)
t
t
pwh1
pwl1
t
t
h1
su1
RPOS
RNEG
RDATA
BPV
HARDWARE
MODE OR
HOST MODE
(CLKE = 0)
RCLK
Figure 1. Recovered Clock and Data Switching Characteristics
6
DS40F2
CS61535A
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
RCLK Cycle Width
(Note 29)
fc
-
40
-
8.192000
-
60
-
MHz
%
MHz
%
ns
ns
ns
t
pwh3/tpw3
faclki
pwh1/tpw1
tpw1
tpwh1
tpwl1
-
(Note 30)
(Notes 31, 32)
(Note 32)
2.048
29
488
140
348
t
-
-
310
90
120
670
190
500
RCLK Cycle Width
(Note 32)
tpw1
tpwh1
tpwl1
320
-
100
488
348
140
670
-
-
ns
ns
ns
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
TCLK Frequency
(Note 33)
(Note 33)
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
-
-
25
25
100
100
100
100
100
100
-
-
-
-
85
85
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
-
(Note 34)
(Note 35)
(Note 31)
(Note 34)
(Note 35)
(Note 31)
194
194
194
194
194
194
2.048
-
-
TCLK Pulse Width
(Notes 31, 34, 36, 37)
(Notes 35, 36, 37)
80
150
-
-
340
340
t
t
r
f
90%
90%
10%
Figure 2. Signal Rise and Fall Characteristics
Any Digital Output
10%
t
pw2
t
t
pwh2
su2
t
pw3
TCLK
t
t
pwh3
h2
TPOS/TNEG
ACLKI
Figure 3b. Alternate External Clock Characteristics
Figure 3a. Transmit Clock and Data Switching
Characteristics
DS40F2
7
CS61535A
SWITCHING CHARACTERISTICS (TA = -40° to 85°C; TV+, RV+ = ±5%;
Inputs: Logic 0 = 0V, Logic 1 = RV+)
Parameter
Symbol
Min
Typ
Max
Units
SDI to SCLK Setup Time
SCLK to SDI Hold Time
SCLK Low Time
tdc
tcdh
tcl
tch
tr, tf
tcc
tcch
tcwh
tcdv
tcdz
tsu4
th4
50
50
240
240
-
50
50
250
-
-
-
-
-
-
-
-
-
-
-
-
-
50
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK High Time
SCLK Rise and Fall Time
CS to SCLK Setup Time
SCLK to CS Hold Time
CS Inactive Time
SCLK to SDO Valid
CS to SDO High Z
Input Valid To PCS Falling Setup Time
PCS Rising to Input Invalid Hold Time
PCS Active Low Time
Notes: 38. For CLKE = 0, CS must remain low at least 50 ns after the 16th falling edge of SCLK.
39. Output load capacitance = 50pF.
(Note 38)
(Note 39)
-
200
-
100
-
-
-
-
50
50
250
-
-
-
tpcsl
t
cwh
CS
t
t
cch
ch
t
cc
t
cl
SCLK
SDI
t
t
cdh
cdh
t
dc
LSB
LSB
MSB
CONTROL BYTE
DATA BYTE
Figure 4. Serial Port Write Timing Diagram
8
DS40F2
CS61535A
CS
t
cdz
SCLK
t
cdv
SDO
HIGH Z
CLKE = 1
Figure 5. Serial Port Read Timing Diagram
PCS
t
t
h4
su4
t
pcsl
LEN0/1/2, TAOS,
RLOOP, LLOOP,
RCODE, TCODE
VALID INPUT DATA
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
DS40F2
9
CS61535A
THEORY OF OPERATION
as shown in Tables 1 and 2, Figure 7, and Figures
A1-A3 of the Applications section.
Enhancements in CS61535A
The CS61535A modes are Hardware Mode, Ex-
tended Hardware Mode, and Host Mode. In
Hardware and Extended Hardware Modes, discrete
pins are used to configure and monitor the device.
The Extended Hardware Mode provides a parallel
chip select input which latches the control inputs
allowing individual ICs to be configured using a
common set of control lines. In the Host Mode, an
external processor monitors and configures the de-
vice through a serial interface. There are thirteen
multi-function pins whose functionality is deter-
mined by the operating mode (see Table 2).
The CS61535A provides higher performance and
more features than the CS61535 including:
•
•
50% lower power consumption,
Internally matched transmitter output imped-
ance for improved signal quality,
•
Optional AMI, B8ZS, HDB3 encoder/decoder
or external line coding support,
•
•
Receiver AIS (unframed all ones) detection,
ANSI T1.231-1993 compliant receiver Loss
of Signal (LOS) handling,
•
•
•
Transmitter TTIP and TRING outputs are
forced low when TCLK is static,
The Driver Performance Monitor operates
over a wider range of input signal levels.
Elimination of the requirement that a refer-
ence clock be input on the ACLKI pin.
Transmitter
The transmitter takes data from a T1 (or E1) ter-
minal, attenuates jitter, and produces pulses of
appropriate shape. The transmit clock, TCLK,
and transmit data, TPOS & TNEG or TDATA, are
supplied synchronously. Data is sampled on the
falling edge of the input clock, TCLK.
Existing designs using the CS61535 can be converted
to the higher performance, pin-compatible CS61535A
if the transmit transformer is replaced by a pin-com-
patible transformer with a new turns ratio and the 4.4
Ω resistor used in E1 75 Ω applications is shorted.
Either T1 (DSX-1 or Network Interface) or E1
G.703 pulse shapes may be selected. Pulse shap-
ing and signal level are determined by "line
length select" inputs as shown in Table 3. The
Introduction to Operating Modes
The CS61535A supports three operating modes
which are selected by the level of the MODE pin
MODE
MODE
EXTENDED
FUNCTION
PIN HARDWARE
HOST
TPOS
TNEG
RNEG
RPOS
DPM
MTIP
MRING
-
HARDWARE
TDATA
TCODE
BPV
EXTENDED
HARDWARE
HARDWARE
<0.2V
HOST
3
TPOS
TNEG
RNEG
RPOS
DPM
TRANSMITTER
MODE-PIN
INPUT LEVEL
FLOAT, or
2.5V
4
>(RV+) - 0.2V
6
INDIVIDUAL
CONTROL
LINES &
PARALLEL
CHIP
7
RDATA
AIS
RECEIVER/DPM
SERIAL
µ-PROCESSOR
PORT
INDIVIDUAL
CONTROL
LINES
11
17
18
18
23
24
25
26
27
28
CONTROL
METHOD
MTIP
MRING
-
RCODE
-
SELECT
PCS
LINE CODE
ENCODER &
DECODER
AMI,
B8ZS,
HDB3
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
LEN0
INT
NONE
NO
NONE
NO
LEN1
SDI
CONTROL
LEN2
SDO
CS
AIS DETECTION
YES
RLOOP
LLOOP
TAOS
DRIVER
PERFORM-
SCLK
CLKE
YES
NO
YES
ANCE MONITOR
Table 1. Differences in Operating Modes
Table 2. Pin Definitions
10
DS40F2
CS61535A
HARDWARE MODE
TAOS LLOOP RLOOP
LEN0/1/2
CONTROL
TPOS
TNEG
TTIP
JITTER
ATTENUATOR
TRANSMIT
TRANSFORMER
LINE DRIVER
DRIVER MONITOR
LINE RECEIVER
TRING
MRING
MTIP
CS62180B
FRAMER
CIRCUIT
CS61535A
DPM
RTIP
RPOS
RNEG
RECEIVE
TRANSFORMER
RRING
EXTENDED HARDWARE MODE
TCODE RCODE
TAOS LLOOP RLOOP PCS LEN0/1/2
CONTROL
TTIP
JITTER
TDATA
TRANSMIT
TRANSFORMER
LINE DRIVER
ATTENUATOR
TRING
AMI
HIGH
SPEED
MUX
CS61535A
B8ZS,
HDB3,
CODER
RTIP
(e.g., M13)
AIS
RECEIVE
TRANSFORMER
RDATA
LINE RECEIVER
DETECT
RRING
BPV
AIS
HOST MODE
CLKE
P SERIAL PORT
5
µ
CONTROL
CONTROL
TPOS
TNEG
TTIP
TRANSMIT
TRANSFORMER
JITTER
ATTENUATOR
LINE DRIVER
TRING
CS62180B
FRAMER
CIRCUIT
MRING
MTIP
CS61535A
DRIVER MONITOR
DPM
RTIP
RPOS
RNEG
RECEIVE
TRANSFORMER
LINE RECEIVER
RRING
Figure 7. Overview of Operating Modes
DS40F2
11
CS61535A
LEN2 LEN1 LEN0 OPTION SELECTED
APPLICATION
width will meet the G.703 pulse shape template
shown in Figure 9, and specified in Table 4.
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
0-133 FEET
133-266 FEET
266-399 FEET
399-533 FEET
533-655 FEET
DSX-1
ABAM
(AT&T 600B
or 600C)
For E1 applications, the CS61535A driver pro-
vides 14 dB of return loss during the transmission
of both marks and spaces. This improves signal
quality by minimizing reflections off the trans-
mitter. Similar levels of return loss are provided
for T1 applications.
AT&T CB113
(CS61535A only)
0
0
1
REPEATER
0
0
0
0
1
1
0
0
1
CCITT G.703
2.048 MHz E1
FCC Part 68, Option A CSU NETWORK
INTERFACE
ANSI T1.403
Table 3. Line Length Selection
The CS61535A transmitter will detect a failed
TCLK, and will force the TTIP and TRING out-
puts low.
CS61535A line driver is designed to drive a 75 Ω
equivalent load.
For T1 DSX-1 applications, line lengths from 0 to
655 feet (as measured from the transmitter to the
DSX-1 cross connect) are selectable. The five
partition arrangement meets ANSI T1.102-1993
requirements when using ABAM cable. A typical
output pulse is shown in Figure 8. These pulse
settings can also be used to meet CCITT pulse
shape requirements for 1.544 MHz operation.
NORMALIZED
AMPLITUDE
1.0
AT&T CB 119
SPECIFICATION
0.5
For T1 Network Interface applications, additional
options are provided. Note that the optimal pulse
width for Part 68 (324 ns) is narrower than the
optimal pulse width for DSX-1 (350 ns). The
CS61535A automatically adjusts the pulse width
based upon the "line length " selection made.
0
CS61535A
OUTPUT
PULSE SHAPE
-0.5
0
250
750
500
TIME (nanoseconds)
1000
The E1 G.703 pulse shape is supported with line
length selection LEN2/1/0=0/0/0. The pulse
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
For coaxial cable, For shielded twisted
75Ω
load
and pair, 120Ω load and
transformer specified transformer specified
in Application Section. in Application Section.
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal pulse width
2.37 V
3 V
0 ±0.237 V
0 ±0.30 V
244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05*
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05*
* When configured with a 0.47 µF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
12
DS40F2
CS61535A
0
Percent of
nominal
peak
a) Minimum Attenuation Limit
10
20
30
40
50
60
269 ns
voltage
AT&T 62411
Requirements
120
110
100
90
244 ns
194 ns
b) Maximum
Attenuation
Limit
80
Measured Performance
50
1
10
100
1 k
10 k
Frequency in Hz
Figure 10. Typical Jitter Attenuation Curve
10
0
Nominal Pulse
tal to set its oscillation frequency to the average
of the TCLK frequency. Signal jitter is absorbed
in the FIFO.
-10
-20
219 ns
488 ns
Jitter Tolerance of Jitter Attenuator
Figure 9 . Mask of the Pulse at the 2048 kbps Interface
The FIFO in the jitter attenuator is designed to
neither overflow nor underflow. If the jitter am-
plitude becomes very large, the read and write
pointers may get very close together. Should the
pointers attempt to cross, the oscillator’s divide
by four circuit adjusts by performing a divide by
3 1/2 or divide by 4 1/2 to prevent the overflow
or underflow. When a divide by 3 1/2 or 4 1/2
occurs, the data bit will be driven on to the line
either an eighth bit period early or an eighth bit
period late.
When any transmit control pin (TAOS, LEN0-2
or LLOOP) is toggled, the transmitter stabilizes
within 22 bit periods. The transmitter will take
longer to stabilize when RLOOP is selected be-
cause the timing circuitry must adjust to the new
frequency.
Jitter Attenuator
The jitter attenuator is designed to reduce wander
and jitter in the transmit clock signal. It consists
of a 32 bit FIFO, a crystal oscillator, a set of load
capacitors for the crystal, and control logic. The
jitter attenuator exceeds the jitter attenuation re-
quirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 10.
When the TCLK frequency is close to the center
frequency of the crystal oscillator, the high fre-
quency jitter tolerance is 23 UI before the divide
by 3 1/2 or 4 1/2 circuitry is activated. As the
center frequency of the oscillator and the TCLK
frequency deviate from one another, the jitter tol-
erance is reduced. As this frequency deviation
becomes large, the maximum jitter tolerance at
high frequencies is reduced to 12 UI before the
underflow/overflow circuitry is activated. In ap-
plication, it is unlikely that the oscillator center
frequency will be precisely aligned with the
The jitter attenuator works in the following man-
ner. Data on TPOS and TNEG (or TDATA) are
written into the jitter attenuator’s FIFO by TCLK.
The rate at which data is read out of the FIFO and
transmitted is determined by the oscillator. Logic
circuits adjust the capacitive loading on the crys-
DS40F2
13
CS61535A
RTIP
Data
Sampling
&
Clock
Extraction
RPOS
RNEG
RCLK
1 : 2
Data
Level
Slicer
RRING
Clock
Phase
Selector
Edge
Detector
ACLKI or
Continuously
Calibrated
Delay Line
Oscillator in Jitter
Attenuator
Figure 11. Receiver Block Diagram
TCLK frequency due to allowable TCLK toler-
ance, part to part variations, crystal to crystal
variations, and crystal temperature drift. The os-
cillator tends to track low frequency jitter so jitter
tolerance increases as jitter frequency decreases.
not available on the CS61535A when ACLKI is
grounded.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of cable
lengths and requires no equalization or ALBO
(Automatic Line Build Out) circuits. The signal is
received on both ends of a center-tapped, center-
grounded transformer. The transformer is
center-tapped on the IC side. The clock and data
recovery circuit exceeds the jitter tolerance speci-
fications of Publications 43802, 43801, 62411
amended, TR-TSY-000170, and CCITT REC.
G.823.
The crystal frequency must be 4 times the nomi-
nal signal frequency: 6.176 MHz for 1.544 MHz
operation; 8.192 MHz for 2.048 MHz applica-
tions. Internal capacitors load the crystal,
controlling the oscillation frequency. The crystal
must be designed so that over operating tempera-
ture, the oscillator frequency range exceeds the
system frequency tolerance. Crystal Semiconduc-
tor offers the CXT6176 & CXT8192 crystals,
which yield optimum performance with the
CS61535A.
Transmit All Ones Select
A block diagram of the receiver is shown in Fig-
ure 11. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0).
The transmitter provides for all ones insertion at
the frequency of ACLKI. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. A TAOS
request will be ignored if remote loopback is in
effect. ACLKI jitter will be attenuated. TAOS is
14
DS40F2
CS61535A
The receiver uses an edge detector and a continu-
ously calibrated delay line to generate the
recovered clock. The delay line divides its refer-
ence clock, ACLKI or the jitter attenuator’s
oscillator, into 13 equal divisions or phases. Con-
tinuous calibration assures timing accuracy, even
if temperature or power supply voltage fluctuate.
the Host Mode, CLKE determines the clock po-
larity for which output data is stable and valid as
shown in Table 5.
MODE
(pin 5)
CLKE
(pin 28)
DATA
CLOCK Clock Edge for
Valid Data
LOW
(<0.2V)
X
RPOS
RNEG
RCLK
RCLK
Rising
Rising
HIGH
(>(V+) - 0.2V)
LOW
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Rising
Rising
Falling
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recover the data. The jitter
tolerance of the receiver exceeds that shown in
Figure 12.
HIGH
(>(V+) - 0.2V)
HIGH
X
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Falling
Falling
Rising
MIDDLE
(2.5V)
RDATA
RCLK
Falling
X = Don’t care
Table 5. Data Output/Clock Relationship
Jitter and Recovered Clock
The CS61535A are designed for error free clock
and data recovery from an AMI encoded data
stream in the presence of more than 0.4 unit inter-
vals of jitter at high frequency. The clock
recovery circuit is also tolerant of long strings of
zeros. The edge of an incoming data bit causes
the circuitry to choose a phase from the delay line
which most closely corresponds with the arrival
time of the data edge, and that clock phase trig-
gers a pulse which is typically 140 ns in duration.
This phase of the delay line will continue to be
selected until a data bit arrives which is closer to
another of the 13 phases, causing a new phase to
be selected. The largest jump allowed along the
delay line is six phases.
300
100
28
PEAK
TO
PEAK
JITTER
10
(unit intervals)
1
.4
.1
0
10
100 300 700 1k
10k
100k
JITTER FREQUENCY (Hz)
Figure 12. Input Jitter Tolerance of Receiver
The CS61535A outputs a clock immediately upon
power-up. The clock recovery circuit is cali-
brated, and the device will lock onto the AMI
data input immediately. If loss of signal occurs,
the RCLK frequency will equal the ACLKI fre-
quency.
When an input signal is jitter free, the phase se-
lection will occasionally jump between two
adjacent phases resulting in RCLK jitter with an
amplitude of 1/13 UIpp. These single phase
jumps are due to differences in frequency of the
incoming data and the calibration clock input to
ACLKI. For T1 operation of the CS61535A, the
instantaneous period can be 14/13 * 648 ns = 698
ns (1,662,769 Hz) or 12/13 * 648 ns = 598 ns
(1,425,231 Hz) when adjacent clock phases are
chosen. As long as the same phase is chosen, the
In the Hardware Mode, data at RPOS and RNEG
is stable and may be sampled on the rising edge
of the recovered clock. In the Extended Hardware
Mode, data at RDATA is stable and may be sam-
pled on the falling edge of the recovered clock. In
DS40F2
15
CS61535A
period will be 648 ns. Similar calculations hold
for the E1 rate.
ceived, or when the received signal amplitude
drops below a 0.3 V peak threshold.
The clock recovery circuit is designed to accept at
least 0.4 UI of jitter at the receiver. Since the data
stream contains information only when ones are
transmitted, a clock/data recovery circuit must as-
sume a zero when no signal is measured during a
bit period. Likewise, when zeros are received, no
information is present to update the clock recov-
ery circuit regarding the trend of a signal which is
jittered. The result is that two ones that are sepa-
rated by a string of zeros can exhibit maximum
deviation in pulse arrival time. For example, one
half of a period of jitter at 100 kHz occurs in 5
µs, which is 7.7 T1 bit periods. If the jitter ampli-
tude is 0.4 UI, then a one preceded by seven zeros
can have maximum displacement in arrival time,
i.e. either 0.4 UI too early or 0.4 UI too late. For
the CS61535A, the data recovery circuit correctly
assigns a received bit to its proper clock period if
it is displaced by less than 6/13 of a bit period
from its optimal location. Theoretically, this
would give a jitter tolerance of 0.46 UI. The ac-
tual jitter tolerance of the CS61535A is only
slightly less than the ideal.
The receiver reports loss of signal by setting the
Loss of Signal pin, LOS, high. If the serial inter-
face is used, the LOS bit will be set and an
interrupt issued on INT. LOS will go low (and
flag the INT pin again if serial I/O is used) when
a valid signal is detected. Note that in the Host
Mode, LOS is simultaneously available from both
the register and pin 12.
In a loss of signal state, the RCLK frequency will
be equal to the ACLKI frequency since ACLKI is
being used to calibrate the clock recovery circuit.
Received data is output on RPOS and RNEG (or
RDATA) regardless of LOS status. The LOS re-
turns to logic zero when the ones density reaches
12.5% (based upon 175 bit periods staring with a
one and containing less than 100 consecutive ze-
ros) as prescribed in ANSI T1.231-1993. A
power-up or manual reset will also set LOS high.
Local Loopback
The local loopback mode takes clock and data
presented on TCLK, TPOS, and TNEG (or
TDATA) and outputs it at RCLK, RPOS and
RNEG (or RDATA). Local loopback is selected
by taking pin 27 high, or LLOOP may be selected
using the serial interface. The data on the trans-
mitter inputs is transmitted on the line unless
TAOS is selected to cause the transmission of an
all ones signal instead. Receiver inputs are ig-
nored when local loopback is in effect. The jitter
attenuator is not included in the local loopback
data path. Selection of local loopback overrides
the chip’s loss of signal response.
In the event of a maximum jitter hit, the RCLK
clock period immediately adjusts to align itself
with the incoming data and prepare to accurately
place the next one, whether it arrives one period
later, or after another string of zeros and is dis-
placed by jitter. For a maximum early jitter hit,
RCLK will have a period of 7/13 * 648 ns = 349
ns (2,865,961 Hz). For a maximum late jitter hit,
RCLK will have a period of 19/13 * 648 ns = 947
ns (1,055,880 Hz).
Loss of Signal
Remote Loopback
Receiver loss of signal is indicated upon receiv-
ing 175 consecutive zeros. A digital counter
counts received zeros based on RCLK cycles. A
zero input is determined either when zeros are re-
In remote loopback, the recovered clock and data
input on RTIP and RRING are sent through the
jitter attenuator and back out on the line via TTIP
and TRING. The recovered incoming signals are
also sent to RCLK, RPOS and RNEG (or
16
DS40F2
CS61535A
RDATA). Remote loopback is selected by taking
pin 26 high, or RLOOP may be selected using the
serial interface. Simultaneous selection of local
and remote loopback modes is not valid (see Re-
set).
Line Code Encoder/Decoder
In Extended Hardware Mode, three line codes are
available: AMI, B8ZS and HDB3. The input to
the encoder is TDATA. The outputs from the de-
coder are RDATA and BPV (Bipolar Violation
Strobe). The encoder and decoder are selected us-
ing pins LEN2, LEN1, LEN0, TCODE and
RCODE as shown in Table 6.
In the CS61535A Extended Hardware Mode, re-
mote loopback occurs before the line code
encoder/decoder, insuring that the transmitted sig-
nal matches the received signal, even in the
presence of received bipolar violations. The re-
covered data will also be decoded and output on
RDATA if RCODE is low.
LEN 2/1/0
000
010-111
TCODE
(Transmit
Encoder
Selection)
HDB3
Encoder
AMI
Encoder
HDB3
Decoder
B8ZS
Encoder
LOW
HIGH
LOW
HIGH
Driver Performance Monitor
RCODE
(Receiver
Decoder
Selection)
B8ZS
Decoder
AMI
Decoder
To aid in early detection and easy isolation of
nonfunctioning links, the Hardware and Host
Modes of the CS61535A are able to monitor
transmit drive performance and report when the
driver is no longer operational. This feature can
be used to monitor either the device’s perform-
ance or the performance of a neighboring driver.
The driver performance monitor indicator is nor-
mally at a low (zero) logic level, and goes to high
level upon detecting driver failure. In the Host
Mode, DPM is available from both the register
and pin 11.
Table 6. Selection of Encoder/Decoder
Alarm Indication Signal
In Extended Hardware Mode, the receiver sets the
output pin AIS high when less than 9 zeros are
detected out of 8192 bit periods. AIS returns low
when 9 or more zeros are detected out of 8192
bits.
Parallel Chip Select
The driver performance monitor consists of an ac-
tivity detector that monitors the transmitted signal
when MTIP is connected to TTIP and MRING is
connected to TRING. DPM will go high if the
absolute difference between MTIP and MRING
does not transition above or below a threshold
level within a time-out period.
In Extended Hardware Mode, PCS can be used to
gate the digital control inputs: TCODE, RCODE,
LEN0, LEN1, LEN2, RLOOP, LLOOP and
TAOS. Inputs are accepted on these pins only
when PCS is low. Changes in inputs will immedi-
ately change the operating state of the device.
Therefore, when cycling PCS to update the oper-
ating state, the digital control inputs should be
stable for the entire PCS low period. The control
inputs are ignored when PCS is high.
Whenever more than one line interface IC resides
on the same circuit board, the effectiveness of the
driver performance monitor can be maximized by
having each IC monitor performance of a neigh-
boring device, rather than having it monitor its
own performance.
Power On Reset / Reset
Upon power-up, the CS61535A is held in a static
state until the supply crosses a threshold of ap-
DS40F2
17
CS61535A
CS
SCLK
SDI
R/W
0
0
0
0
1
0
0
D0
D0
D1
D1
D2
Data Input/Output
D2 D3 D4
D3
D4
D5
D5
D6
D7
Address/Command Byte
D6 D7
SDO
Figure 13. Input/Output Timing
proximately three Volts. When this threshold is
crossed, the device will delay for about 10 ms to
allow the power supply to reach operating voltage.
After this delay, calibration of the delay lines used
in the transmit and receive sections commences.
The delay lines can be calibrated only if a refer-
ence clock is present. The reference clock for the
receiver is provided by ACLKI (or by the crystal
oscillator if ACLKI is not present). The reference
clock for the transmitter is provided by TCLK. The
initial calibration should take less than 20 ms.
acteristics and monitor device status. The serial
port read/write timing is independent of the sys-
tem transmit and receive timing.
Data transfers are initiated by taking the chip se-
lect input, CS, low (CS must initially be high).
SCLK may be either high or low when CS in-
itially goes low. Address and input data bits are
clocked in on the rising edge of SCLK. Data on
SDO is valid and stable on the falling edge of
SCLK when CLKE is low, and on the rising edge
of SCLK when CLKE is high. Data transfers are
terminated by setting CS high. CS may go high
no sooner than 50 ns after the rising edge of the
SCLK cycle corresponding to the last write bit.
For a serial data read, CS may go high any time
to terminate the output.
In operation, the delay lines are continuously cali-
brated, making the performance of the device
independent of power supply or temperature vari-
ations. The continuous calibration function
foregoes any requirement to reset the line inter-
face when in operation. However, a reset function
is available which will clear all registers.
Figure 13 shows the timing relationships for data
transfers when CLKE = 1. When CLKE = 0, data
output from the serial port, SDO, is valid on the
falling edge of SCLK. For CLKE = 1, data bit D7
is held to the falling edge of the 16th clock cycle;
for CLKE = 0, data bit D7 is held to the rising
edge of the 17th clock cycle. SDO goes to a high
In the Hardware and Extended Hardware modes, a
reset request is made by simultaneously setting both
RLOOP and LLOOP high for at least 200 ns. Reset
will initiate on the falling edge of the reset request
(falling edge of RLOOP and LLOOP). In the Host
Mode, a reset is initiated by simultaneously writing
RLOOP and LLOOP to the register. In either mode,
a reset will set all registers to 0 and set LOS high.
Read/Write Select; 0 = write, 1 =
read
LSB, first bit
0
R/W
1
2
3
4
5
6
ADD0 LSB of address, Must be 0
ADD1 Must be 0
Serial Interface
ADD2 Must be 0
ADD3 Must be 0
In the Host Mode, pins 23 through 28 serve as a
microprocessor/microcontroller interface. One
eight-bit register can be written to via the SDI pin
or read from the SDO pin at the clock rate deter-
mined by SCLK. Through this register, a host
controller can be used to control operational char-
ADD4 Must be 1
-
Reserved - Must be 0
Table 7. Address/Command Byte
18
DS40F2
CS61535A
impedance state either after bit D7 is output or at
the end of the hold period of data bit D7.
LSB: first bit in
0
1
2
3
4
LOS Loss of Signal
DPM Driver Performance Monitor
LEN0 Bit 0 - Line Length Select
LEN1 Bit 1 - Line Length Select
LEN2 Bit 2 - Line Lenght Select
An address/command byte, shown in Table 7,
precedes a data register. The first bit of the ad-
dress/command byte determines whether a read
or a write is requested. The next six bits contain
the address. The CS61535A responds to address
16 (0010000). The last bit is ignored.
Table 9. Output Data Bits 0 - 4
Bits
5 6 7
Status
The data register, shown in Table 8, can be writ-
ten to the serial port. Data is input on the eight
clock cycles immediately following the ad-
dress/command byte. Bits 0 and 1 are used to
clear an interrupt issued from the INT pin, which
occurs in response to a loss of signal or a problem
with the output driver. If bits 0 or 1 are true, the
corresponding interrupt is suppressed. So if a loss
of signal interrupt is cleared by writing a 1 to bit
0, the interrupt will be reenabled by writing a 0 to
bit 0. This holds for DPM as well.
Reset has occurred or no program input.
TAOS in effect.
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
LLOOP in effect.
TAOS/LLOOP in effect.
RLOOP in effect
DPM changed state since last "clear DPM"
occured.
LOS changed state since last "clear LOS"
occured.
LOS and DPM have changed state since
last "clear LOS" and "clear DPM".
1 1 0
1 1 1
Table 10. Coding for Serial Output Bits 5, 6, 7
LSB: first bit in
0
1
2
3
4
5
6
7
clr LOS Clear Loss of Signal
clr DPM Clear Driver Performance Monitor
LEN0 Bit 0 - Line Length Select
LEN1 Bit 1 - Line Length Select
LEN2 Bit 2 - Line Lenght Select
RLOOP Remote Loopback
Writing a "0" to either "Clear LOS" or "Clear
DPM" enables the corresponding interrupt for
LOS or DPM.
LLOOP Local Loopback
MSB: last bit in
TAOS Transmit All Ones Select
Output data from the serial interface is presented
as shown in Tables 9 and 10. Bits 2, 3 and 4 can
be read to verify line length selection. Bits 5, 6
and 7 must be decoded. Codes 101, 110 and 111
(bits 5, 6 and 7) indicate LOS and DPM state
changes. Writing a "1" to the "Clear LOS" and/or
"Clear DPM" bits in the register also resets status
bits 5, 6, and 7.
Table 8. Input Data Register
Writing a "1" to either "Clear LOS" or "Clear
DPM" over the serial interface has three effects:
1) the current interrupt on the serial interface
will be cleared. (Note that simply reading the
register bits will not clear the interrupt),
SDO goes to a high impedance state when not in
use. SDO and SDI may be tied together in appli-
cations where the host processor has a
bidirectional I/O port.
2) output data bits 5, 6 and 7 will be reset as
appropriate,
3) future interrupts for the corresponding LOS
or DPM will be prevented from occuring).
DS40F2
19
CS61535A
Power Supply
The device operates from a single +5 Volt supply.
Separate pins for transmit and receive supplies
provide internal isolation. These pins should be
connected externally near the device and decou-
pled to their respective grounds. TV+ must not
exceed RV+ by more than 0.3V.
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
Decoupling and filtering of the power supplies is
crucial for the proper operation of the analog cir-
cuits in both the transmit and receive paths. A 1.0
µF capacitor should be connected between TV+
and TGND, and a 0.1 µF capacitor should be con-
nected between RV+ and RGND. Use mylar or
ceramic capacitors and place them as closely as
possible to their respective power supply pins. A
68 µF tantalum capacitor should be added close
to the RV+/RGND supply. Wire wrap bread-
boarding of the line interface is not recommended
because lead resistance and inductance serve to
defeat the function of the decoupling capacitors.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
20
DS40F2
CS61535A
PIN DESCRIPTIONS
Hardware Mode
ACLKI
TCLK
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
RRING
RTIP
MRING
MTIP
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT 10
DPM 11
LOS 12
TTIP
TGND
13
TRING
TV+
14
ACLKI
TCLK
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
DPM
4
5
3
2
1
28 27 26
25
24
23
22
21
20
19
6
7
top
view
8
9
10
11
RRING
RTIP
12 13 14 15 16 17 18
LOS
MRING
MTIP
TTIP
TGND
TRING
TV+
DS40F1
21
CS61535A
Extended Hardware Mode
ACLKI
TCLK
TDATA
TCODE
MODE
BPV
RDATA
RCLK
XTALIN
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
RRING
RTIP
PCS
RCODE
TRING
TV+
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
XTALOUT 10
AIS 11
LOS 12
TTIP
TGND
13
14
ACLKI
TCLK
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
TDATA
TCODE
MODE
BPV
4
5
3
2
1
28 27 26
25
24
23
22
21
20
19
6
RDATA
RCLK
XTALIN
XTALOUT
AIS
7
top
view
8
9
10
11
RRING
RTIP
12 13 14 15 16 17 18
LOS
PCS
TTIP
RCODE
TRING
TV+
TGND
22
DS40F1
CS61535A
Host Mode
ACLKI
TCLK
CLKE
SCLK
CS
SDO
SDI
INT
RGND
RV+
RRING
RTIP
MRING
MTIP
TRING
TV+
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT 10
DPM 11
LOS 12
TTIP
TGND
13
14
ACLKI
TCLK
CLKE
SCLK
CS
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
DPM
SDO
SDI
4
5
3
2
1
28 27 26
25
24
23
22
21
20
19
6
INT
7
top
view
8
RGND
RV+
9
10
11
RRING
RTIP
MRING
MTIP
TRING
TV+
12 13 14 15 16 17 18
LOS
TTIP
TGND
DS40F1
23
CS61535A
Power Supplies
RGND - Ground, Pin 22.
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
RV+ - Power Supply, Pin 21.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
TGND - Ground, Transmit Driver, Pin 14.
Power supply ground for the transmit driver; typically 0 Volts.
TV+ - Power Supply, Transmit Driver, Pin 15.
Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than
0.3 V.
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or
2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying
XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10.
Overdriving the oscillator with an external clock is not supported.
Control
ACLKI - Alternate External Clock Input, Pin 1.
The CS61535A does not require a clock signal to be input on ACLKI when a crystal is connected
between pins 9 and 10. If a clock is not provided on ACLKI, this input must be grounded. If
ACLKI is grounded, the oscillator in the jitter attenuator is used to calibrate the clock recovery
circuit and TAOS is not available.
CLKE - Clock Edge, Pin 28. (Host Mode)
Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and
SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS
and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of
SCLK.
CS - Chip Select, Pin 26. (Host Mode)
This pin must transition from high to low to read or write the serial port.
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing
"Clear LOS" or "Clear DPM" to the register. INT is an open drain output and should be tied to
the power supply through a resistor.
24
DS40F1
CS61535A
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
Determines the shape and amplitude of the transmitted pulse to accommodate several cable types
and lengths. See Table 3 for information on line length selection. Also controls the receiver
slicing level and the line code in Extended Hardware Mode.
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
Setting LLOOP to a logic 1 routes the transmit clock and data through to the receive clock and
data pins. TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request.
Inputs on RTIP and RRING are ignored.
MODE - Mode Select, Pin 5.
Driving the MODE pin high puts the CS61535A line interface in the Host Mode. In the host
mode, a serial control port is used to control the CS61535A line interface and determine its status.
Grounding the MODE pin puts the CS61535A line interface in the Hardware Mode, where
configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to
+2.5 V puts the CS61535A in Extended Hardware Mode, where configuration and status are
controlled by discrete pins. When floating MODE, there should be no external load on the pin.
MODE defines the status of 13 pins (see Table 2).
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
Setting PCS high causes the CS61535A line interface to ignore the TCODE, RCODE, LEN0,
LEN1, LEN2, RLOOP, LLOOP and TAOS inputs.
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting
RCODE high enables the AMI receiver decoder (see Table 8).
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter
attenuator (if active) and through the driver back to the line. The recovered signal is also sent to
RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored.
Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset.
SCLK - Serial Clock, Pin 27. (Host Mode)
Clock used to read or write the serial port registers. SCLK can be either high or low when the line
interface is selected using the CS pin.
SDI - Serial Data Input, Pin 24. (Host Mode)
Data for the on-chip register. Sampled on the rising edge of SCLK.
SDO - Serial Data Output, Pin 25. (Host Mode)
Status and control information from the on-chip register. If CLKE is high SDO is valid on the
rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to
a high-impedance state when the serial port is being written to or after bit D7 is output.
DS40F1
25
CS61535A
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)
Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined
by ACLKI.
TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)
Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting
TCODE high enables the AMI transmitter encoder .
Data
RCLK - Recovered Clock, Pin 8.
The receiver recovered clock is output on this pin.
RDATA - Receive Data - Pin 7. (Extended Hardware Mode)
Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the
line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK.
RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and
Host Modes)
The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS
and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines
the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse
(with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive
pulse received on the RRING pin generates a logic 1 on RNEG.
RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.
The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up
transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data
and clock are recovered and output on RCLK and RPOS/RNEG or RDATA.
TCLK - Transmit Clock, Pin 2.
The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are
sampled on the falling edge of TCLK.
TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)
Transmitter NRZ input data which passes through the line code encoder, and is then driven on to
the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK.
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)
Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and
TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a
positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.
The AMI signal is driven to the line through these pins. In the CS61535A, this output is designed
to drive a 75 Ω load. A 1:1, 1:1.15 or 1:1.26 transformer is required as shown in Figure A1.
26
DS40F1
CS61535A
Status
AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)
AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection
criteria of less than three zeros out of 2048 bit periods.
BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)
BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3)
zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been
enabled.
DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)
DPM goes high if no activity is detected on MTIP and MRING.
LOS - Loss of Signal, Pin 12.
LOS goes high when 175 consecutive zeros have been received. For the CS61535A, LOS returns
low when the ones density reaches 12.5% (based upon 175 bit periods starting with a one and
containing less than 100 consecutive zeros) as prescribed by ANSI T1.231-1993.
MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)
These pins are normally connected to TTIP and TRING and monitor the output of a CS61535A.
If the INT pin in the host mode is used, and the monitor is not used, writing "Clear DPM" to the
serial interface will prevent an interrupt from the driver performance monitor.
DS40F1
27
CS61535A
MILLIMETERS
MIN NOM MAX MIN NOM MAX
INCHES
15
14
28
1
DIM
A
28 pin
Plastic DIP
E1
3.94 4.32
A1 0.51 0.76
0.200
0.040
0.022
0.065
0.015
1.465
0.560
0.105
0.625
0.150
15°
5.08 0.155 0.170
1.02 0.020 0.030
0.56 0.014 0.018
1.65 0.040 0.050
0.38 0.008 0.010
37.21 1.435 1.450
14.22 0.540 0.550
2.67 0.095 0.100
B
B1
C
D
E1
e1
0.36 0.46
1.02 1.27
0.20 0.25
36.45 36.83
13.72 13.97
2.41 2.54
D
A
SEATING
PLANE
L
A1
eA
L
15.24
3.18
0°
-
-
-
15.87 0.600
3.81 0.125
15°
-
-
-
e1
C
B1
B
eA
0°
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
28-pin PLCC
28
MILLIMETERS
INCHES
E
E1
DIM MIN NOM MAX MIN NOM MAX
A
4.20 4.45 4.57 0.165 0.175 0.180
2.29 2.79 3.04 0.090 0.110 0.120
0.33 0.41 0.53 0.013 0.016 0.021
12.32 12.45 12.57 0.485 0.490 0.495
11.43 11.51 11.58 0.450 0.453 0.456
9.91 10.41 10.92 0.390 0.410 0.430
1.19 1.27 1.35 0.047 0.050 0.053
A1
B
D/E
D1/E1
D2/E2
e
D1
D
e
B
A1
A
D2/E2
28
DS40F1
CS61535A
APPLICATIONS
+5V
F
+
+
68
µ
F
0.1
µ
1.0
µF
+5V
100 k
Ω
RGND
TGND
21
RV+
15
TV+
27
26
23
24
25
28
CLKE
ACLKI
LOS
SCLK
CS
1
12
11
Control
P
µ
&
INT
Serial
Port
Monitor
DPM
SDI
SDO
RV+
5
7
6
8
MODE
RPOS
RNEG
RCLK
CS61535A
IN
HOST
MODE
CT 2:1
19
RTIP
R1
R2
RECEIVE
LINE
Frame
Format
Encoder/
Decoder
20
RRING
3
4
2
TPOS
TNEG
TCLK
17
18
16
MTIP
MRING
TRING
0.47
F
µ
9
XTALIN
TRANSMIT
LINE
XTL
10
13
XTALOUT
TTIP
RGND TGND
22 14
DEVICE
FREQUENCY
MHz
CABLE
R1&2
Ω
Transmit
Transformer
Ω
1.544
2.048
2.048
100
120
75
200
240
150
1:1.15
1:1.26
1:1
CS61535A
Figure A1. Host Mode Configuration
Line Interface
core of the transformer due to any DC imbalance
that may be present at the differential outputs,
TTIP and TRING. If DC saturates the trans-
former, a DC offset will result during the
transmission of a space (zero) as the transformer
tries to dump the charge and return to equilib-
rium. The blocking capacitor will keep DC
current from flowing in the transformer.
Figures A1-A3 show the typical configurations
for interfacing the I.C. to a line through transmit
and receive transformers.
The receiver transformer is center tapped and
center grounded with resistors between the center
tap and each leg on the I.C. side. These resistors
provide the termination for the line.
Selecting an Oscillator Crystal
Specific crystal parameters are required for
proper operation of the CS61535A. It is recom-
mended that the CXT6176 from Crystal
Figures A1-A3 show a 0.47 µF capacitor in series
with the transmit transformer primary. This ca-
pacitor is needed to prevent any buildup in the
DS40F2
29
CS61535A
+5V
F
+
+
68
F
0.1
1.0 F
µ
µ
µ
RGND
28
TGND
21
RV+
15
TV+
TAOS
ACLKI
RLOOP
LLOOP
LOS
1
26
27
12
11
23
24
25
Control
&
Monitor
LEN0
LEN1
LEN2
Line
Length
Setting
DPM
CT 2:1
5
19
20
CS61535A
IN
HARDWARE
MODE
MODE
RTIP
R1
R2
RECEIVE
LINE
7
6
8
RPOS
RNEG
RCLK
RRING
Frame
Format
Encoder/
Decoder
3
4
2
17
18
16
TPOS
TNEG
TCLK
MTIP
MRING
TRING
0.47 µF
TRANSMIT
LINE
13
TTIP
9
XTALIN
XTL
10
XTALOUT
RGND TGND
22 14
Figure A2. Hardware Mode Configuration
+5V
+
+
68
F
0.1
F
µ
1.0 F
µ
µ
RGND
TGND
21
RV+
15
TV+
17
RCODE
PCS
18
6
23
BPV
LEN0
LEN1
LEN2
Line
28
1
24
25
TAOS
ACLKI
RLOOP
LLOOP
LOS
Length
Setting
Control
&
26
27
12
11
5
Monitor
CT 2:1
CS61535A
IN
EXTENDED
HARDWARE
MODE
19
20
RTIP
R1
R2
RECEIVE
LINE
AIS
MODE
TCODE
4
RRING
7
8
3
2
RDATA
RCLK
Frame
Format
Encoder/
Decoder
0.47 µF
TDATA
TCLK
16
13
TRING
TTIP
TRANSMIT
LINE
9
XTALIN
XTL
10
XTALOUT
RGND TGND
22 14
Figure A3. Extended Hardware Mode Configuration
30
DS40F2
CS61535A
Semiconductor be used for T1 applications, and
that the CXT8192 be used for E1 applications.
ing applications where eight bits can be dropped
from the clock/data stream at once. Similarly,
these parts can be used in SONET applications
with the addition of some external circuitry.
Interfacing The CS61535A With the CS62180B
T1 Transceiver
The main differences of the CS61535A relative
to the CS61534 is:
To interface with the CS62180B, connect the de-
vices as shown in Figure A4. In this case, the
CS61535A and CS62180B are in Host Mode con-
trolled by a microprocessor serial interface. If the
CS61535A is used in Hardware Mode, then the
CS61535A RCLK output must be inverted before
being input to the CS62180B. If the CS61535A is
used in Extended Hardware Mode, the CS61535A
RCLK output does not need to be inverted before
being input to the CS62180B.
1) On the CS61535A, selection of LEN 2/1/0 =
0/0/0 changes the voltage at which the receiver
accepts an input as a pulse (slicing level) from
65% to 50% of the peak pulse amplitude. Lower-
ing the data slicing level will improve receiver
sensitivity at long cable lengths when the data is
jittered. A 50% slicing level will also improve
crosstalk sensitivity for channels where received
pulses do not have undershoot.
2) There are differences in the functionality of the
ACLKI (ACLK) input on the CS61534 and
CS61535A. ACKLI (ACLK) is used as the trans-
mit clock in the transmit all ones (TAOS) mode.
On the CS61535A, ACLKI is used as a calibra-
tion reference for the receiver clock recovery
circuit and therefore may not be supplied by
RCLK. On the CS61534, ACLK may be supplied
by RCLK . If an external clock is not provide on
the ACLKI input of the CS61535A, the crystal
oscillator is used to calibrate the receiver clock
recovery circuit.
TO HOST CONTROLLER
V+
100k
1.544 MHz
CLOCK
SIGNAL
ACLKI
TCLK
CLKE
SCLK
TCLK
SCLK
SDO
SDI
TPOS
TNEG
CS
TPOS
TNEG
V+
SDO
SDI
100k
V+
22k
68uF
MODE
CS
RNEG
RNEG
RPOS
RCLK
INT
RGND
RV+
0V 0.1uF
+5V
RPOS
RCLK
+
CS62180B
CS61535A
3) On the CS61535A, the Host Mode status regis-
ter bits 5, 6 and 7 are encoded so that state
changes on LOS and DPM may be reported.
Figure A4. Interfacing the CS61535A with the
CS62180B (Host Mode)
4) RCLK on the CS61534 has a 50% duty cycle,
while RCLK on the CS61535A has a duty cycle
which is typically 30% or 70%. Also, the
CS61535A RCLK duty cycle and instantaneous
frequency vary with received jitter and may ex-
hibit 1/13 UIpp quantization jitter even when the
incoming signal is jitter free.
CS61534 Compatibility
The CS61535A is pin compatible with the
CS61534. The CS61535A has greater jitter toler-
ance for both transmitter and receiver, and it
provides more jitter attenuation starting at jitter
frequencies of 6 Hz. The greater jitter tolerance
and attenuation in the transmit path makes the
CS61535A more suitable for CCITT demultiplex-
5) The CS61535A requires 25 ns of setup time on
TPOS and TNEG before the falling edge of
TCLK and 25 ns of hold time on these inputs af-
DS40F2
31
CS61535A
ter the falling edge of TCLK. The CS61534 re-
quires 50 ns of hold time on TPOS and TNEG
after the falling edge of TCL, and 0 ns of setup
time.
30 frame (256 bits per frame) has its data mapped
into the 6480 bit SONET frame. The mapping
does not result in a uniform spacing between
sucessive T1 (or E1) bits. Rather, for locked VT
applications, gaps as large as 24 T1 bit periods or
32 E1 bit periods can exist between successive
bits. With floating VTs, the gaps can be even
larger.
6) LOS occurs after 31 consecutive zeros on the
CS61534. For the CS61535A LOS occurs after
175 zeros.
7) Since the CS61535A receivers are continu-
ously calibrated, there is no need to issue a reset
to initialize the receiver timing as with the
CS61534.
The circuit in Figure A5 eliminates the demulti-
plexing jitter in a two-step approach. The first
step uses a FIFO which is filled at a 51.84 MHz
rate (when T1 or E1 bits are present), and which
is emptied at a sub-multiple of the 51.84 rate. The
FIFO is emptied only when it contains data.
When the FIFO is empty the output clock is not
pulsed.
Using the CS61535A for SONET
The CS61535A can be applied to SONET VT1.5
and VT2.0 interface circuits as shown in Fig-
ure A5. The SONET data rate is 51.84 MHz, and
has 6480 bits per frame (125 us per frame). An
individual T1 frame (193 bits per frame) or PCM-
The sub-multiple rate chosen should be slightly
faster than the target rate (1.544 or 2.048 MHz),
but as close to the target rate as possible. For
51.84 MHz
Div By
Write
Clock
Empty
FIFO
TCLK2
TPOS
TNEG
Jitter
Attenuator
TCLK1
TSER
RSER
Driver
TSER
6480 to
193 bit
(or 256 bit)
Mapping
Circuit
CS62180B
CS61535A
RSER
FIFO
RPOS
RNEG
Receiver
RCLK2
RCLK1
RCLK2
Figure A5. SONET Application
32
DS40F2
CS61535A
locked VT operation, Table A1 shows potential
sub-multiple data rates, and the impact on those
rates on the maximum gap in the output clock of
the FIFO, and depth of FIFO required. FIFO
depth will have to be increased for floating VT
operation, with 8 bits of FIFO depth being added
for each pointer alignment change that can occur.
Transformers
Recommended transmitter and receiver trans-
former specifications for the CS61535A are
shown in Table A2. The transformers in Table A3
have been tested and recommended for use with
the CS61535A. Refer to the "Telecom Trans-
former Selection Guide" for detailed schematics
which show how to connect the line interface IC
with a particular transformer.
The objective that should be met in picking a
FIFO depth and clock divider is keep the maxi-
mum gap on the output of the FIFO at 12 bits or
less. Twelve bits is the maximum jitter which can
be input to the CS61535A’s jitter attenuator with-
out causing the overflow/undeflow protection
circuit to operate. The CS61535A then removes
the remaining jitter from the signal.
In applications with the CS61535A where it is ad-
vantageous to use a single transmitter transformer
for both 75Ω and 120Ω E1 applications, a 1:1.26
transforer may be used. Although transmitter re-
turn loss will be reduced for 75Ω applications, the
pulse amplitude will be correct across a 75 Ω
load.
The receive path also requires a bit mapping
(from 193 or 256 bits to 6480 bits). This mapping
requires an input buffer with the same depth as
use on the transmit path. This buffer also absorbs
the output jitter generated by the CS61535A’s
digital clock recovery.
Target Rate
(MHz)
Clock
Divider
Resultant
Rate (MHz)
Maximum Gap
FIFO Depth
Required
bits
(µs)
6.2
3.9
3.4
1.544
1.544
2.048
32
33
25
1.620
1.571
2.074
10
6
21
26
34
7
Table A1. Locked VT FIFO Analysis
Parameter
CS61535A Receiver
CS61535A Transmitter
Turns Ratio
1:2 CT ± 5%
1:1 ± 1.5 % for 75 Ω E1
1:1.15 ± 5 % for 100 Ω T1
1:1.26 ± 1.5 % for 120 Ω E1
Primary Inductance
Primary Leakage Inductance
Secondary Leakage Inductance
Interwinding Capacitance
ET-constant
1.5 mH min. @ 772 kHz
0.3 µH max. @ 772 kHz
0.4 µH max. @ 772 kHz
18 pF max.
600 µH min. @ 772 kHz
1.3 µH max. @ 772 kHz
0.4 µH max. @ 772 kHz
23 pF max.
16 V-µs min. for T1
12 V-µs min. for E1
16 V-µs min. for T1
12 V-µs min. for E1
Table A2. Transformer Specifications
DS40F2
33
CS61535A
Application
Turns
Manufacturer
Part Number
Package Type
Ratio(s)
RX:
T1 & E1
1:2CT
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
PE-65351
67129300
0553-0013-HC
PE-65388
67129310
0553-0013-RC
PE-65389
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, single
TX:
T1
1:1.15
TX:
1:1.26
1:1
E1 (75 & 120 Ω)
67129320
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
0553-0013-SC
PE-65565
0553-0013-7J
PE-65566
RX &TX:
T1
1:2CT
1:1.15
1.5 kV through-hole, dual
1.5 kV through-hole, dual
RX &TX:
E1 (75 & 120 Ω)
1:2CT
1:1.26
1:1
0553-0013-8J
RX &TX:
T1
1:2CT
1:1.15
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
PE-65765
S553-0013-06
PE-65766
1.5 kVsurface-mount, dual
1.5 kV surface-mount, dual
RX &TX:
E1 (75 & 120 Ω)
1:2CT
1:1.26
1:1
S553-0013-07
RX :
T1 & E1
TX:
1:2CT
Pulse Engineering
Pulse Engineering
PE-65835
PE-65839
3 kV through-hole, single
EN60950, EN41003 approved
3 kV through-hole, single
EN60950, EN41003 approved
1:1.26
1:1
E1 (75 & 120 Ω)
Table A3. Recommended Transformers For The CS61535A
34
DS40F2
CDB61534, CDB61535, CDB61535A, CDB6158,
CDB6158A, CDB61574, CDB61574A, CDB61575,
CDB61577, CDB615304A, & CDB61305A
Line Interface Evaluation Board
Features
General Description
The evaluation board includes a socketed line interface
device and all support components necessary for
evaluation. The board is powered by an external 5 Volt
supply.
Socketed Line Interface Device
•
•
All Required Components for Complete
Line Interface Evaluation
The board may be configured for 100 Ω twisted-pair
T1, 75 Ω coax E1, or 120 Ω twisted-pair E1 operation.
Binding posts are provided for line connections. Sev-
eral BNC connectors are available to provide system
clocks and data I/O. Two LED indicators monitor de-
vice alarm conditions. The board supports all line
interface operating modes.
Configuration by DIP Switch or Serial
Interface
•
LED Status Indicators for Alarm
Conditions
•
ORDERING INFORMATION:
CDB61534, CDB61535. CDB61535A,
Support for Host, Hardware, and
Extended Hardware Modes
•
CDB6158,
CDB6158A, CDB61574,
CDB61574A, CDB61575, CDB61577,
CDB61304A, CDB61305A
+5V
0V
Mode Select
Circuit
Reset
Circuit
TTIP
Serial Interface
Control Circuit
TRING
CS61534,
CS61535,
CS61535A,
CS6158,
CS6158A,
CS61574,
CS61574A,
CS61575,
CS61577,
CS61304A
or
Hardware
Control Circuit
LED Status
Indicators
RTIP
ACLKI
RRING
TCLK
TPOS
CS61305A
(TDATA)
TNEG
(TCODE)
XTL
RCLK
RPOS
(RDATA)
RNEG
(BPV)
Crystal Semiconductor Corporation
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
SEP ’95
DS40DB3
35
LINE INTERFACE EVALUATION BOARD
POWER SUPPLY
Table 1 explains how to configure the evaluation
board jumpers depending on the device installed
and the desired operating mode. Mode selection
is accomplished with slide switch SW1 and jump-
ers JP2, JP6, and JP7. The CS61535A,
CS61574A, CS61575, CS61577, CS61304A, and
CS61305A support the Hardware, Extended
Hardware, and Host operating modes. The
CS61534, CS61535, and CS61574 support the
Hardware and Host operating modes. The
CS6158 and CS6158A only support the Hardware
operating mode.
As shown on the evaluation board schematic in
Figure 1, power is supplied to the evaluation
board from an external +5 Volt supply connected
to the two binding posts labeled +5V and GND.
Transient suppressor D10 protects the compo-
nents on the board from over-voltage damage and
reversed supply connections. The recommended
power supply decoupling is provided by C1, C2
and C3. Ceramic capacitor C1 and electrolytic ca-
pacitor C2 are used to decouple RV+ to RGND.
Capacitor C3 decouples TV+ to TGND. The TV+
and RV+ power supply traces are connected at the
device socket U1. A ground plane on the compo-
nent side of the evaluation board insures optimum
performance.
Hardware Mode
In the Hardware operating mode, the line inter-
face is configured using DIP switch S2. The digi-
tal control inputs to the device selected by S2 in-
clude: transmit all ones (TAOS), local loopback
(LLOOP), remote loopback (RLOOP), and trans-
mit line length selection (LEN2,LEN1,LEN0).
Closing a DIP switch on S2 towards the label sets
the device control pin of the same name to logic 1
(+5 Volts). Note that S2 switch positions TCODE
and RCODE have no function in Hardware mode.
In addition, the host processor interface connector
JP1 should not be used in the Hardware mode.
BOARD CONFIGURATION
Pins on line interface device U1 with more than
one pin name have different functions depending
on the operating mode selected. Pin names not
enclosed in parenthesis or square brackets de-
scribe the Hardware mode pin function. Pin
names enclosed in parenthesis describe the Ex-
tended Hardware mode pin function. Pin names
enclosed in square brackets describe the Host
mode pin function.
Two LED status indicators are provided in Hard-
ware mode. The LED labeled DPM (AIS) illumi-
nates when the line interface asserts the Driver
JUMPER
POSITION
-
FUNCTION SELECTED
JP1
Connector for external processor in Host operating mode.
A-A
B-B
IN
Extended Hardware operating mode.
JP2, JP6, JP7
Hardware or Host operating modes.
Hardware or Extended Hardware operating modes.
JP3
JP4
JP5
JP8
OUT
C-C
D-D
E-E
F-F
Host operating mode.
Connects the ACLKI BNC input to pin 1 of device.
Grounds the ACLKI BNC input through 51Ω resistor R1.
Transmit line connection for all applications except those listed for "F-F" on the next line.
75Ω coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1.
Shorts resistor R2 for all applications except those listed for "OUT" on the next line.
Inserts resistor R2 for 75Ω coax E1 applications using the CS61534, 35, 58, 74, or 77.
IN
OUT
Table 1. Evaluation Board Jumper Settings
36
DS40DB3
LINE INTERFACE EVALUATION BOARD
RV+
RV+
+5V
C2
0.1 F
µ
D10
P6KE
Prototyping
Area
C1
68
GND
(0V)
C3
µ
F
1
F
µ
+
RV+
15
TV+
14
22
21
R13 (only included for CS6158/58A)
1k
TGND RGND RV+
Ω
Pin 6
9
6
RNEG
(BPV)
XTALIN
RNEG (BPV)
RCLK
E1: CXT8192
T1: CXT6176
(not included for CS6158/58A)
{CS6158/58A: RT}
RCLK
TCLK
Pin 3
8
2
3
RCLK
10
19
XTALOUT
TCLK
RTIP
Change R9 and R10 for E1 operation
{CS6158/58A: NC}
TCLK
T2
(see Table 2)
2:1
TPOS
(TDATA)
TPOS (TDATA)
RTIP
RTIP
R10
Pin 7
7
200
Ω
RPOS (RDATA)
RPOS
ACLKI
D
(RDATA)
JP4
R1 51.1
Ω
D
U1
R9
200
1
4
RRING
20
RV+
ACLKI
Ω
ACLKI
TNEG
C
B
C
Pin 4
R15
100
RRING
TTIP
JP2
RRING
TTIP
B
A
TNEG (TCODE)
TTIP
Pin 18
Ω
13
18
A
S2
JP6
B
B
A
RCODE
MRING (PCS)
0.47
C5
F
µ
TCODE
JP5
A
TRING
16
E
E
LEN0/INT
LEN1/SDI
23
24
25
26
27
28
LEN0 [INT]
TRING
LEN1 [SDI]
Pin 17
F F
LEN2/SD0
RLOOP/CS
JP7
JP8
LEN2 [SD0]
RLOOP [CS]
LLOOP [SCLK]
TAOS [CKLE]
17
B
B
A
MTIP (RCODE)
T1
(see Table 2)
LLOOP/SCLK
TAOS/CLKE
A
TRING
R2
INT
SDI
4.4
Ω
SDO
CS
SCLK
(Used only for E1 75
Ω
MODE DPM (AIS)
11
LOS
12
applications with the CS61534,
CS61535, CS6158, CS61574,
OR CS61577)
5
RV+
RV+
DPM
(AIS)
D8
D9
1N914
LOS
JP1
R14
4.7k
Ω
Q2
Q1
S1
RESET
R4
221k
2N2222
2N2222
SIP
U1: CS61534, CS61535,
CS61535A, CS6158,
CS6158A, CS61574,
CS61574A, CS61575,
CS61577, CS61304A,
OR CS61305A
LED
D2
LED
D3
C4 0.047 F
µ
MODE
6
Ω
3
R5
R6
470Ω
MODE
SW1
470Ω
8
7
5
1
2
4
R17
10k
R18
R16
HOST:3-1,6-8
EXT HW: 3-2, 6-7
HW: 3-4, 6-5
RV+
Ω
10k
Ω
1k
Ω
Figure 1. Evaluation Board Schematic
DS40DB3
37
LINE INTERFACE EVALUATION BOARD
Performance Monitor alarm. The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.
terface signals. Resistor R15 is a current limiting
resistor that prevents the serial interface signals
from being shorted directly to the +5 Volt supply
if any S2 switch, other than CLKE, is closed.
Jumper JP3 should be out so the INT pin may be
externally pulled-up at the host processor inter-
rupt pin.
Extended Hardware Mode
In the Extended Hardware operating mode, the
line interface is configured using DIP switch S2.
The digital control inputs to the device selected
by S2 include: transmit all ones (TAOS), local
loopback (LLOOP), remote loopback (RLOOP),
transmit line length selection (LEN2, LEN1,
LEN0), transmit line code (TCODE), and receive
line code (RCODE). Closing a DIP switch (mov-
ing it towards the S2 label) sets the device control
pin of the same name to logic 1 (+5 Volts). Note
that the TCODE and RCODE options are active
low and are enabled when the switch is moved
away from the S2 label. The parallel chip select
input PCS is tied to ground in Extended Hard-
ware mode to enable the device to be reconfig-
ured when S2 is changed. In addition, the host
processor interface connector JP1 should not be
used in Extended Hardware mode.
Two LED status indicators are provided in Host
mode. The LED labeled DPM (AIS) illuminates
when the line interface asserts the Driver Per-
formance Monitor alarm. The LED labeled LOS
illuminates when the line interface receiver has
detected a loss of signal.
Manual Reset
A manual reset circuit is provided that can be
used in Hardware and Extended Hardware
modes. The reset circuit consists of S1, R4, R16,
C4, D8, and D9. Pressing switch S1 forces both
LLOOP and RLOOP to a logic 1 and causes a
reset. A reset is only necessary for the CS61534
device to calibrate the center frequency of the re-
ceiver clock recovery circuit. All other line inter-
face units use a continuously calibrated clock re-
covery circuit that eliminates the reset require-
ment.
Two LED status indicators are provided in Ex-
tended Hardware mode. The LED labeled DPM
(AIS) illuminates when the line interface detects
the receive blue alarm (AIS). The LED labeled
LOS illuminates when the line interface receiver
has detected a loss of signal.
TRANSMIT CIRCUIT
The transmit clock and data signals are supplied
on BNC inputs labeled TCLK, TPOS(TDATA),
and TNEG. In the Hardware and Host operating
modes, data is supplied on the TPOS(TDATA)
and TNEG connectors in dual NRZ format. In the
Extended Hardware operating mode, data is sup-
plied in NRZ format on the TPOS(TDATA) con-
nector and TNEG is not used.
Host Mode
In the Host operating mode, the line interface is
configured using a host processor connected to
the serial interface port JP1. The S2 switch posi-
tion labeled CLKE selects the active edge of
SCLK and RCLK. Closing the CLKE switch se-
lects RPOS and RNEG to be valid on the falling
edge of RCLK and SDO to be valid on the rising
edge of SCLK as required by the CS2180B T1
framer.
The transmitter output is transformer coupled to
the line through a transformer denoted as T1 in
Figure 1. The signal is available at the TTIP and
TRING binding posts. Capacitor C5 is the recom-
mended 0.47 µF DC blocking capacitor.
All other DIP switch positions on S2 should be
open (logic 0) to prevent shorting of the serial in-
38
DS40DB3
LINE INTERFACE EVALUATION BOARD
The recovered clock and data signals are avail-
able on BNC outputs labeled RCLK,
RPOS(RDATA), and RNEG(BPV). In the Hard-
ware and Host operating modes, data is output on
the RPOS(RDATA) and RNEG(BPV) connectors
in dual NRZ format. In the Extended Hardware
operating mode, data is output in NRZ format on
the RPOS(RDATA) connector and bipolar viola-
tions are reported on the RNEG(BPV) connector.
The evaluation board supports 100Ω twisted-pair
T1, 75Ω coax E1, and 120Ω twisted-pair E1 op-
eration. The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 are supplied from
the factory with a 1:2 transmit transformer that
may be used for all T1 and E1 applications. The
CDB61535A, CDB6158A, CDB61574A,
CDB61575, CDB61304A, and CDB61305A are
supplied with a 1:1.15 transmit transformer in-
stalled for T1 applications. An additional 1:1:1.26
transformer for E1 applications is provided with
the board. This transformer requires JP5 to be
jumpered across F-F for 75Ω coax E1 applica-
tions.
QUARTZ CRYSTAL
A quartz crystal must be installed in socket Y1 for
all devices except the CS6158 and CS6158A. A
Crystal Semiconductor CXT6176 crystal is rec-
ommended for T1 operation and a CXT8192 is
recommended for E1 operation. The evaluation
board has a CXT6176 installed at the factory and
a CXT8192 is also provided with the board.
The CDB61534, CDB61535, CDB6158,
CDB61574, and CDB61577 require the JP8
jumper to be out for 75Ω coax E1 applications.
This inserts resistor R2 to reduce the transmit
pulse amplitude and meet the 2.37 V nominal
pulse amplitude requirement in CCITT G.703. In
addition, R2 increases the equivalent load imped-
ance across TTIP and TRING.
The CDB6158 and CDB6158A have resistor R13
installed instead of a crystal. This connects the RT
pin of the device to the +5 Volt supply.
ALTERNATE CLOCK INPUT
RECEIVE CIRCUIT
The ACLKI BNC input provides the alternate
clock reference for the line interface device
(ACLK for the CS61534) when JP4 is jumpered
across C-C. This clock is required for the
CS61534, CS61535, CS6158, and CS6158A op-
eration but is optional for all other line interface
devices. If ACLKI is provided, it may be desir-
able to connect both C-C and D-D positions on
JP4 to terminate the external clock source provid-
ing ACLKI with the 51Ω resistor R1. If ACLKI is
optional and not used, connector JP4 should be
jumpered across D-D to ground pin 1 of the de-
vice through resistor R1.
The receive line interface signal is input at the
RTIP and RRING binding posts. The receive sig-
nal is transformer coupled to the line interface de-
vice through a center-tapped 1:2 transformer. The
transformer produces ground referenced pulses of
equal amplitude and opposite polarity on RTIP
and RRING.
The receive line interface is terminated by resis-
tors R9 and R10. The evaluation boards are sup-
plied from the factory with 200Ω resistors for ter-
minating 100Ω T1 twisted-pair lines. Resistors
R9 and R10 should be replaced with 240Ω resis-
tors for terminating 120Ω E1 twisted-pair lines or
150Ω resistors for terminating 75Ω E1 coaxial
lines. Two 243Ω resistors and two 150Ω resistors
are included with the evaluation board for this
purpose.
TRANSFORMER SELECTION
To permit the evaluation of other transformers,
Table 2 lists the transformer and line interface de-
vice combinations that can be used in T1 and E1
DS40DB3
39
LINE INTERFACE EVALUATION BOARD
applications. A letter at the intersection of a row
and column in Table 2 indicates that the selected
transformer is supported for use with the device.
The transformer is installed in the evaluation
board with pin 1 positioned to match the letter
illustrated on the drawing in Table 2. For exam-
ple, the Pulse Engineering PE-65388 transformer
may be used with the transmitter of the CS61575
device for 100Ω T1 applications only (as indi-
cated by note 3) when installed in transformer
socket T1 with pin 1 at position D (upper right).
4. To avoid damage to the external host controller
connected to JP1, all S2 switch positions (except
CLKE) should be open. In the Host operating
mode, the CLKE switch selects the active edge of
SCLK and RCLK.
PROTOTYPING AREA
A prototyping area with power supply and ground
connections is provided on the evaluation board.
This area can be used to develop and test a vari-
ety of additional circuits like a data pattern gener-
ator, CS2180B framer, system synchronizer PLL,
or specialized interface logic.
EVALUATION HINTS
1. Properly terminate TTIP/TRING when evaluat-
ing the transmit output signal. For more informa-
tion concerning pulse shape evaluation, refer to
the Crystal application note entitled "Measure-
ment and Evaluation of Pulse Shapes in T1/E1
Transmission Systems."
2. Change the receiver terminating resistors R9
and R10 when evaluating E1 applications. Resis-
tors R9 and R10 should be replaced with 240Ω
resistors for terminating 120Ω E1 twisted-pair
lines or 150Ω resistors for terminating 75Ω E1
coaxial lines. Two 243Ω resistors and two 150Ω
resistors are included with the evaluation board
for this purpose.
3. Closing a DIP switch on S2 towards the label
sets the device control pin of the same name to
logic 1 (+5 Volts).
40
DS40DB3
LINE INTERFACE EVALUATION BOARD
LINE INTERFACE UNIT
TRANSFORMER
(Turns Ratio)1,2
’304A,
’305A
’34
’35
’35A
’58
’58A ’74,’77 ’74A
’75
RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX
PE-65351 (1:2CT)
Schott 12930 (1:2CT)
A
B
D
C
A
B
D
C
A
B
A
B
D
C
A
B
A
B
D
C
A
B
A
B
A
B
PE-65388 (1:1.15)
Schott 12931 (1:1.15)
PE-65389 (1:1:1.26)
Schott 12932 (1:1:1.26)
D3
C3
D4
C4
D3
C3
D4
C4
D3
C3
D4
C4
D3
C3
D4
C4
D3,5
C3,5
D4,5
C4,5
PE-64951 (dual 1:2CT)
E
E
E
E
E
E
E
E
Schott 11509 (dual 1:2CT)
PE-65565 (dual 1:1.15 & 1:2CT)
Schott 12531 (dual 1:1.15 & 1:2CT)
PE-65566 (dual 1:1:1.26 & 1:2CT)
Schott 12532 (dual 1:1:1.26 & 1:2CT)
E3
E3
E3
E3
E3,5
E3
E4
E4
E3
E4
E4
E3
E4
E4
E3
E4
E4
E3,5
E4,5
E4,5
NOTES:
1. A letter at the intersection of a row and column in Table 2 indicates
that the selected transformer is supported for use with the device.
The transformer is installed in the evaluation board with pin 1 po-
sitioned to match the letter illustrated in the drawing to the left.
T2
T2
B
2. The receive transformer (RX) is soldered at location T2 on the
evaluation board and is used for all applications. The transmit
transformer (TX) is socketed at location T1 on the evaluation
board and may be changed according to the application.
D
3. For use in 100Ω T1 twisted-pair applications only.
A
4. For use in 75Ω and 120Ω E1 applications only. Place jumper JP5
in position F-F for 75Ω E1 applications requiring a 1:1 turns ratio.
5. Transmitter return loss improves when using a 1:2 turns ratio trans-
former with the appropriate transmit resistors.
C
E
T1
T1
Table 2. Transformer Applications
DS40DB3
41
LINE INTERFACE EVALUATION BOARD
Figure 2. Silk Screen Layer (NOT TO SCALE)
42
DS40DB3
LINE INTERFACE EVALUATION BOARD
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
DS40DB3
43
LINE INTERFACE EVALUATION BOARD
Figure 4. Bottom Trace Layer (NOT TO SCALE)
44
DS40DB3
• Notes •
• Notes •
• Notes •
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation
相关型号：
©2020 ICPDF网 联系我们和版权申明