WM8215CSEFL [CIRRUS]
Analog Circuit, 1 Func, CMOS, PQCC32, QFN-32;
| 型号： | WM8215CSEFL |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Analog Circuit, 1 Func, CMOS, PQCC32, QFN-32 |
| 文件： | 总31页 (文件大小：639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8215
w
60MSPS 10-bit 3-Channel CCD Digitiser
DESCRIPTION
FEATURES
10-bit ADC
The WM8215 is a 10-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 60MSPS.
60MSPS conversion rate
Low power – 400mW typical
3.3V single supply operation
3 channel operation
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. The output from each of these
channels is time multiplexed into a single high-speed 10-bit
Analogue to Digital Converter. The digital output data is
available in 10-bit wide parallel format.
Correlated double sampling
Programmable gain (9-bit resolution)
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Programmable clamp voltage
Internally generated voltage references
32-lead QFN package
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used to reference CIS signals, in
non-CDS mode or to clamp CCD signals during Reset Level
Clamping. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Serial control interface
APPLICATIONS
Digital Copiers
Using an analogue supply voltage of 3.3V and a digital
interface supply of 3.3V, the WM8215 typically only
consumes 400mW.
USB2.0 compatible scanners
Multi-function peripherals
High-speed CCD/CIS sensor interface
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
Production Data, September 2012, Rev 4.3
Copyright 2012 Wolfson Microelectronics plc.
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews
WM8215
Production Data
TABLE OF CONTENTS
DESCRIPTION....................................................................................................... 1
FEATURES............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
BLOCK DIAGRAM ................................................................................................ 1
TABLE OF CONTENTS......................................................................................... 2
PIN CONFIGURATION.......................................................................................... 3
ORDERING INFORMATION.................................................................................. 3
PIN DESCRIPTION................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS........................................................................ 5
RECOMMENDED OPERATING CONDITIONS..................................................... 5
THERMAL PERFORMANCE................................................................................. 5
ELECTRICAL CHARACTERISTICS ..................................................................... 6
INPUT VIDEO SAMPLING .............................................................................................. 8
SERIAL INTERFACE..................................................................................................... 10
INTERNAL POWER ON RESET CIRCUIT.......................................................... 11
DEVICE DESCRIPTION ...................................................................................... 13
INTRODUCTION ........................................................................................................... 13
INPUT SAMPLING ........................................................................................................ 13
RESET LEVEL CLAMPING (RLC) ................................................................................ 14
CDS/NON-CDS PROCESSING..................................................................................... 16
OFFSET ADJUST AND PROGRAMMABLE GAIN........................................................ 16
ADC INPUT BLACK LEVEL ADJUST ........................................................................... 17
OVERALL SIGNAL FLOW SUMMARY ......................................................................... 18
CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT ...................................... 19
REFERENCES .............................................................................................................. 20
POWER MANAGEMENT .............................................................................................. 20
LINE-BY-LINE OPERATION ......................................................................................... 20
CONTROL INTERFACE................................................................................................ 20
NORMAL OPERATING MODES ................................................................................... 22
DEVICE CONFIGURATION................................................................................. 23
REGISTER MAP............................................................................................................ 23
REGISTER MAP DESCRIPTION.................................................................................. 24
APPLICATIONS INFORMATION ........................................................................ 28
RECOMMENDED EXTERNAL COMPONENTS ........................................................... 28
RECOMMENDED EXTERNAL COMPONENT VALUES .............................................. 28
PACKAGE DIMENSIONS.................................................................................... 29
IMPORTANT NOTICE ......................................................................................... 30
ADDRESS: .................................................................................................................... 30
REVISION HISTORY ........................................................................................... 31
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PIN CONFIGURATION
ORDERING INFORMATION
MOISTURE
SENSITIVITY
TEMPERATURE
PEAK SOLDERING
TEMPERATURE
DEVICE
RANGE
PACKAGE
LEVEL
32-lead QFN
(5x5x0.9mm)
(Pb-free)
0 to 70oC
0 to 70oC
MSL1
260C
260C
WM8215CSEFL
32-lead QFN
(5x5x0.9mm)
WM8215CSEFL/R
MSL1
(Pb-free, tape and reel)
Note:
Reel quantity = 3,500
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PIN DESCRIPTION
PIN
1
NAME
RSMP
MCLK
DGND
SEN
TYPE
DESCRIPTION
Reset sample pulse (when CDS=1) or clamp control
Master (ADC) clock. This clock determines the ADC conversion rate.
Digital ground.
Digital input
Digital input
Supply
2
3
Enables the serial interface when high.
Digital supply, all digital I/O pins.
Serial data input.
4
Digital input
Supply
5
DVDD2
SDI
6
Digital input
Digital input
No connect
No connect
Serial clock.
7
SCK
No internal connection.
8
NC
No internal connection.
9
NC
Digital output data bus. ADC output data (d9:d0) is available in 10-bit parallel
format.
d0 (LSB)
10
11
12
13
14
15
16
17
18
19
OP[0]
OP[1]
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d1
d2
OP[2]
d3
OP[3]
d4
OP[4]
d5
OP[5]
d6
OP[6]
d7
OP[7]
d8
OP[8]
d9 (MSB)
OP[9]/SDO
Alternatively, pin OP[9]/SDO may be used to output register read-back data when
OEB=0, OPD(register bit)=0 and SEN has been pulsed high. See Serial Interface
description in Device Description section for further details.
Analogue supply. This must be operated at the same potential as DVDD1.
Analogue ground.
20
21
22
AVDD
AGND1
VRB
Supply
Supply
Lower reference voltage.
Analogue output
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
23
24
25
VRT
VRX
Analogue output
Analogue output
Analogue I/O
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
VRLC/VBIAS
Blue channel input video.
Green channel input video.
Red channel input video.
Analogue ground.
26
27
28
29
30
BINP
GINP
Analogue input
Analogue input
Analogue input
Supply
RINP
AGND2
DVDD1
Digital supply for logic and clock generator. This must be operated at the same
potential as AVDD.
Supply
Output Hi-Z control. All digital outputs set to high-impedance state when input pin
OEB=1 or register bit OPD=1.
31
32
OEB
Digital input
Digital input
Video sample pulse.
VSMP
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN
MAX
Analogue supply voltage: AVDD
Digital supply voltages: DVDD1 2
Digital ground: DGND
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND - 0.3V
GND + 4.2V
GND + 4.2V
GND + 0.3V
GND + 0.3V
DVDD2 + 0.3V
AVDD + 0.3V
AVDD + 0.3V
Analogue grounds: AGND1 2
Digital inputs, digital outputs and digital I/O pins
Analogue inputs (RINP, GINP, BINP)
Other pins
Operating temperature range: TA
Storage temperature after soldering
Notes:
0 C
+70 C
-65 C
+150 C
1.
2.
GND denotes the voltage of any ground pin.
AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages
between these pins will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
SYMBOL
TA
MIN
0
TYP
MAX
70
UNITS
Operating temperature range
Analogue supply voltage
Digital core supply voltage
Digital I/O supply voltage
Notes:
C
V
AVDD
DVDD1
DVDD2
2.97
2.97
2.97
3.3
3.3
3.3
3.63
3.63
3.63
V
V
1. DVDD2 should be operated at the same potential as DVDD1 ± 0.3V.
THERMAL PERFORMANCE
PARAMETER
Performance
SYMBOL
RθJC
TEST CONDITIONS
MIN
TYP
10.27
29.45
MAX
UNIT
°C/W
°C/W
Thermal resistance – junction to
case
Tambient = 25°C
Thermal resistance – junction to
ambient
RθJA
Notes:
1. Figures given are for package mounted on 4-layer FR4 according to JESD51-5 and JESD51-7.
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ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate
60
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
Full-scale input voltage range
(see Note 1)
LOWREFS=0, Max Gain
LOWREFS=0, Min Gain
LOWREFS=1, Max Gain
LOWREFS=1, Min Gain
0.25
3.03
0.15
1.82
Input signal limits (see Note 2)
Input capacitance
VIN
AGND-0.3
AVDD+0.3
10
45
20
pF
Input switching impedance
Full-scale transition error
Gain = 0dB;
mV
PGA[8:0] = 14(hex)
Zero-scale transition error
Gain = 0dB;
20
mV
PGA[8:0] = 14(hex)
Differential non-linearity
Integral non-linearity
DNL
INL
0.75
2
LSB
LSB
Channel to channel gain matching
Output noise
1%
0.2
2.15
%
Min Gain
Max Gain
LSB rms
LSB rms
References
Upper reference voltage
VRT
VRB
LOWREFS=0
LOWREFS=1
LOWREFS=0
LOWREFS=1
1.95
0.95
2.05
1.85
1.05
1.25
1.25
1.0
2.25
1.25
V
V
V
V
V
V
V
Lower reference voltage
Input return bias voltage
VRX
VRTB
Diff. reference voltage (VRT-VRB)
LOWREFS=0
LOWREFS=1
0.95
0.57
1.10
0.68
0.6
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
1
45
2
mA
3
VRLC Hi-Z leakage current
RLCDAC resolution
VRLC = 0 to AVDD
1
A
4
bits
V/step
RLCDAC step size, RLCDACRNG
= 0
VRLCSTEP
0.173
RLCDAC step size, RLCDACRNG
= 1
LOWREFS = 0
LOWREFS = 1
0.11
0.10
VRLCSTEP
V/step
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCBOT
VRLCBOT
0.4
V
V
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
LOWREFS = 0
LOWREFS = 1
0.4
3.0
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
VRLCTOP
V
V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
LOWREFS = 0
LOWREFS = 1
2.05
1.85
RLCDAC
RLCDAC
Notes:
DNL
INL
-0.5
+0.5
LSB
LSB
+/-0.5
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
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2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
LSB
Differential non-linearity
Integral non-linearity
Step size
DNL
INL
0.15
0.4
LSB
2.00
-255
+255
mV/step
mV
Output voltage
Code 00(hex)
Code FF(hex)
mV
Programmable Gain Amplifier
Resolution
Gain
9
bits
V/V
7.34
0.66
* PGA[8 : 0]
511
Max gain, each channel
Min gain, each channel
Gain error, each channel
Analogue to Digital Converter
Resolution
GMAX
GMIN
8
V/V
V/V
%
0.66
3
10
bits
MSPS
V
Speed
60
Full-scale input range
(2*(VRT-VRB))
LOWREFS=0
LOWREFS=1
1.9
2
2.2
1.2
V
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
VIH
VIL
IIH
0.7 DVDD2
V
0.2 DVDD2
V
1
1
A
A
pF
IIL
CI
5
Digital Outputs
High level output voltage
Low level output voltage
High impedance output current
Digital IO Pins
VOH
VOL
IOZ
IOH = 1mA
IOL = 1mA
DVDD2 - 0.5
V
V
0.5
1
A
Applied high level input voltage
Applied low level input voltage
High level output voltage
Low level output voltage
Low level input current
High level input current
Input capacitance
VIH
VIL
VOH
VOL
IIL
0.7 DVDD2
V
V
0.2 DVDD2
IOH = 1mA
IOL = 1mA
DVDD2 - 0.5
V
0.5
1
V
A
A
pF
A
IIH
1
CI
5
High impedance output current
Supply Currents
IOZ
1
Total supply current active
116
105
mA
Analogue supply current – active
(three channel mode)
mA
Digital supply current – active
(three channel mode)
11
20
mA
Supply current full power down
A
mode
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INPUT VIDEO SAMPLING
Figure 1 Three-channel CDS Input Video Timing (CDS=1)
Figure 2 Two-channel CDS Operation (CDS=1)
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Figure 3 One-channel CDS Operation (CDS=1)
Notes:
1. The relationship between input video signal and sample points is controlled by VSMP and RSMP.
2. When VSMP is high the input video signal is connected to the Video sampling capacitors.
3. When RSMP is high the input video signal is connected to the Reset sampling capacitors.
4. RSMP must not go high before the first falling edge of MCLK after VSMP goes low.
5. It is required that the falling edge of VSMP should occur before the rising edge of MCLK.
6. In 1-channel CDS mode it is not possible to have an equally spaced Video and Reset sample points with a 45MHz
MCLK.
7. Non-CDS operation is also possible; RSMP is not required in this mode but can be used to control input clamping.
Timing constraints between vsmp and mclk remain unchanged for non-CDS operation.
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 60MHz for 3 and 2-channel mode and 45MHz
for 1-channel mode unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
16.6
22.2
6.7
TYP
MAX
UNITS
MCLK period – 2/3 channel mode
1 channel mode
tPER
ns
MCLK high period – 2/3 channel mode
1 channel mode
tMCLKH
tMCLKL
8.3
11.1
8.3
ns
ns
MCLK low period – 2/3 channel mode
1 channel mode
6.7
11.1
RSMP pulse high time
tRSD
tVSD
5
5
0
ns
ns
ns
VSMP pulse high time
RSMP falling to VSMP rising time
tRSFVSR
MCLK rising to VSMP rising time
MCLK falling to VSMP falling time
tMRVSR
tMFVSF
tMFVSF
3
0
7
ns
ns
ns
MCLK falling to VSMP falling time in 1
channel mode
VSMP falling to MCLK rising time
tVSFMR
tMF1RS
0
1
ns
ns
1st MCLK falling edge after VSMP falling to
RSMP rising time
3-channel mode pixel period
2-channel mode pixel period
tPR3
tPR2
50
ns
ns
33.3
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PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
1-channel mode pixel period
tPR1
22.2
ns
Output propagation delay
tPD
5
7
10
ns
Output latency. From 1st rising edge of
MCLK after VSMP falling to data output
LAT
MCLK
periods
Notes:
1.
2.
Parameters are measured at 50% of the rising/falling edge.
In 1-channel mode, if tMFVSF is less than 9.5ns, the output amplitude of the WM8215 will decrease.
SERIAL INTERFACE
Figure 4 Serial Interface Timing
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 45MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SCK period
tSPER
83.3
ns
SCK high
tSCKH
tSCKL
tSSU
37.5
37.5
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK low
SDI set-up time
SDI hold time
tSH
6
SCK Rising to SEN Rising
SCK Falling to SEN Falling
SEN to SCK set-up time
SEN pulse width
tSCRSER
tSCFSEF
tSEC
37.5
12
12
tSEW
60
SEN low to SDO = Register data
SCK low to SDO = Register data
SCK low to SDO = ADC data
tSERD
tSCRD
tSCRDZ
30
30
30
Note: 1.
Parameters are measured at 50% of the rising/falling edge
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INTERNAL POWER ON RESET CIRCUIT
Figure 5 Internal Power On Reset Circuit Schematic
The WM8215 includes an internal Power-On-Reset Circuit, as shown in Figure 5, which is used to
reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors DVDD1. It asserts PORB low if AVDD or DVDD1 is below a minimum threshold.
The power supplies can be brought up in any order but is important that either AVDD is brought up
and is stable before DVDD comes up or vice versa as shown in Figure 6 and Figure 7.
Figure 6 Typical Power up Sequence where AVDD is Powered before DVDD1
Figure 6 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above
the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted
low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now
AVDD is at full supply level. Next DVDD1 rises to Vpord_on and PORB is released high and all
registers are in their default state and writes to the control interface may take place.
On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the
minimum threshold Vpora_off.
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Figure 7 Typical Power up Sequence where DVDD1 is Powered before AVDD
Figure 7 shows a typical power-up sequence where DVDD1 comes up first. First it is assumed that
DVDD1 is already up to specified operating voltage. When AVDD goes above the minimum threshold,
Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held
in reset. In this condition, all writes to the control interface are ignored. When AVDD rises to
Vpora_on, PORB is released high and all registers are in their default state and writes to the control
interface may take place.
On power down, where DVDD1 falls first, PORB is asserted low whenever DVDD1 drops below the
minimum threshold Vpord_off.
SYMBOL
Vpora
TYP
0.6
1.2
0.6
0.7
0.6
UNIT
V
V
V
V
V
Vpora_on
Vpora_off
Vpord_on
Vpord_off
Table 1 Typical POR Operation (typical values, not tested)
Note: It is recommended that every time power is cycled to the WM8215 a software reset is written to
the software register to ensure that the contents of the control registers are at their default values
before carrying out any other register writes.
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DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on the front page of this
datasheet.
The WM8215 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then
processes the sampled video signal with respect to the video reset level or an internally/externally
generated reference level using between one and three processing channels.
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and a 9-bit
Programmable Gain Amplifier (PGA).
The processing channel outputs are switched alternately by a 3:1 multiplexer to the ADC input.
The ADC then converts each resulting analogue signal to a 10-bit digital word. The digital output from
the ADC is presented in parallel on the 10-bit wide output bus, OP[9:0]. The ten output pins can be
set to a high impedance state using either the OEB control pin or the OPD register bit.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial interface.
INPUT SAMPLING
The WM8215 can sample and process up to three inputs through one to three processing channels
as follows:
Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for
each pixel and a separate channel processes each input. The signals are then multiplexed into the
ADC, which converts all three inputs within the pixel period.
Two Channel Pixel-by-pixel: Two input channels (RINP and GINP) are simultaneously sampled for
each pixel and a separate channel processes each input. The signals are then multiplexed into the
ADC, which converts both inputs within the pixel period. The unused Blue channel is powered down
when this mode is selected.
Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the
corresponding channel, and converted by the ADC. The choice of input and channel can be changed
via the control interface, e.g. on a line-by-line basis if required. The unused channels are powered
down when this mode is selected.
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RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8215 lies within the supply voltage range (0V to AVDD)
the output signal from a CCD is usually level shifted by coupling through a capacitor, CIN. The RLC
circuit clamps the WM8215 side of this capacitor to a suitable voltage through a CMOS switch during
the CCD reset period (pixel clamping) or during the black pixels (line clamping). In order for clamping
to produce correct results the input voltage during the clamping must be a constant value.
The WM8215 allows the user to control the RLC switch in a variety of ways as illustrated in Figure 8
This figure shows a single channel, however all 3 channels are identical, each with its own clamp
switch controlled by the common CLMP signal.
The method of control chosen depends upon the characteristics of the input video. The RLCEN
register bit must be set to 1 to enable clamping, otherwise the RLC switch cannot be closed (by
default RLCEN=1).
Note that unused inputs should be left floating, or grounded through a decoupling capacitor, if reset
level clamping is used.
Figure 8 RLC Clamp Control Options
When an input waveform has a stable reference level on every pixel it may be desirable to clamp
every pixel during this period. Setting CLAMPCTRL=0 means that the RLC switch is closed
whenever the RSMP input pin is high, as shown in Figure 9.
reference
("black") level
INPUT VIDEO
SIGNAL
video level
MCLK
VSMP
RSMP
Video sample taken on
fallling edge of VSMP
Reset/reference sample taken
on fallling edge of RSMP
RLC switch closed
when RSMP=1
RLC switch control
"CLMP"
(RLCEN=1,CLMPCTRL=0)
Figure 9 Reset Level Clamp Operation (CLAMPCTRL=0), CDS operation shown, non-CDS also possible
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In situations where the input video signal does not have a stable reference level it may be necessary
to clamp only during those pixels which have a known state (e.g. the dummy, or “black” pixels at the
start or end of a line on most image sensors). This is known as line-clamping and relies on the input
capacitor to hold the DC level between clamp intervals. In non-CDS mode (CDS=0) this can be done
directly by controlling the RSMP input pin to go high during the black pixels only.
Alternatively it is possible to use RSMP to identify the black pixels and enable the clamp at the same
time as the input is being sampled (i.e. when VSMP is high and RSMP is high). This mode is enabled
by setting CLAMPCTRL=1 and the operation is shown in Figure 10.
unstable
reference level
dummy or
"black" pixel
INPUT VIDEO
SIGNAL
MCLK
VSMP
RSMP
video level
Video and reference sample
taken on fallling edge of VSMP
RLC switch closed when RSMP=1 &&
VSMP=1 (during "black" pixels)
RLC switch control,
"CLMP"
(RLCEN=1,CLMPCTRL=1)
Figure 10 Reset Level Clamp Operation (CLAMPCTRL=1), non-CDS mode only
RLCEN
CLAMPCTRL
OUTCOME
USE
RLC is not enabled. RLC switch is always open.
When input is DC coupled and within supply
rails.
0
X
RLC switch is controlled directly from RSMP input
pin:
When user explicitly provides a reset sample
signal and the input video waveform has a
suitable reset level.
1
1
0
1
RSMP=0: switch is open
RMSP=1: switch is closed
VSMP applied as normal, RSMP is used to
indicate the location of black pixels
When clamping during the video period of black
pixels or there is no stable per-pixel reference
level.
RLC switch is controlled by logical combination of
RSMP and VSMP:
This method of operation is generally only
sensible in non-CDS mode.
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
Table 2 Reset Level Clamp Control Summary
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CDS/NON-CDS PROCESSING
For CCD type input signals, containing a fixed reference/reset level, the signal may be processed
using Correlated Double Sampling (CDS), which will remove pixel-by-pixel common mode noise. With
CDS processing the input waveform is sampled at two different points in time for each pixel, once
during the reference/reset level and once during the video level. To sample using CDS, register bit
CDS must be set to 1 (default). This causes the signal reference to come from the video reference
level as shown in Figure 11.
The video sample is always taken on the falling edge of the input VSMP signal (VS). In CDS-mode
the reset level is sampled on the falling edge of the RSMP input signal (RS).
For input signals that do not contain a reference/reset level (e.g. CIS sensor signals), non-CDS
processing is used (CDS=0). In this case, the video level is processed with respect to the voltage on
pin VRLC/VBIAS. The VRLC/VBIAS voltage is sampled at the same time as VSMP samples the
video level in this mode.
Figure 11 CDS/non-CDS Input Configuration
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by a 9-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[8:0].
The gain characteristic of the WM8215 PGA is shown in Figure 12. Figure 13 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (default=2V).
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3.5
3
8
Max i/p Voltage
LOWREFS=0
7
6
5
4
3
2
1
Max i/p Voltage
LOWREFS=1
2.5
2
1.5
1
0.5
0
0
0
128
256
384
512
0
128
256
384
512
Gain Code (PGA[8:0])
Gain Code (PGA[8:0])
Figure 12 PGA Gain Characteristic
Figure 13 Peak Input Voltage to Match ADC Full-scale Range
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA can be offset to match the full-scale range of the differential ADC (2*[VRT-
VRB]).
For negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. This will give an output
code of 3FF (hex) from the WM8215 for zero input. If code zero is required for zero differential input
then the INVOP bit should be set.
For positive going input signals the black level should be offset to the bottom of the ADC range by
setting PGAFS[1:0]=11. This will give an output code of 000 (hex) from the WM8215 for zero input.
Figure 14 ADC Input Black Level Adjust Settings
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OVERALL SIGNAL FLOW SUMMARY
Figure 15 represents the processing of the video signal through the WM8215.
OUTPUT
INVERT
BLOCK
INPUT
SAMPLING
BLOCK
OFFSET DAC PGA
ADC BLOCK
BLOCK
BLOCK
D2
x (1023/VFS
)
V1
V2
V3
D1
+0 if PGAFS[1:0]=11
+1023 if PGAFS[1:0]=10
X
OP[9:0]
+
+
VIN
digital
analog
+
-
CDS = 1
CDS = 0
D2 = D1 if INVOP = 0
PGA gain
A= 0.66+PGA[8:0]x7.34/511
D2 = 1023-D1 if INVOP = 1
VRESET
VVRLC
Offset
DAC
255mV*(DAC[7:0]-127.5)/127.5
VIN is RINP, GINP or BINP
VRESET is VIN sampled during reset clamp
VRLC is voltage applied to VRLC/VBIAS pin
CDACPD=1
CDACPD=0
CDS, CDACPD,CDAC[3:0], DAC[7:0],
PGA[8:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
RLC
DAC
See parametrics for
DAC voltages.
Figure 15 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally
set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 10-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
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CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8215.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video, VIN (= RINP, GINP or BINP).
V1
=
VIN - VRESET
Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1
=
VIN - VVRLC
Eqn. 2
If VRLCDACPD = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If VRLCDACPD = 0, VVRLC is the output from the internal RLC DAC.
VVRLC
=
(VRLCSTEP RLC DAC[3:0]) + VRLCBOT
Eqn. 3
V
RLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output.
V2
=
V1 + {255mV (DAC[7:0]-127.5) } / 127.5
Eqn. 4
Eqn. 5
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain.
V3
=
V2 (0.66 + PGA[8:0]x7.34/511)
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 10-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[9:0] = INT{ (V3 /VFS) 1023}
PGAFS[1:0] = 11
PGAFS[1:0] = 10
Eqn. 7
Eqn. 8
D1[9:0] = INT{ (V3 /VFS) 1023} + 1023
where the ADC full-scale range, VFS = 2V when LOWREFS=0 and VFS = 1.2V when LOWREFS=1.
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D2[9:0] = D1[9:0]
(INVOP = 0)
(INVOP = 1)
Eqn. 9
D2[9:0] = 1023 – D1[9:0]
Eqn. 10
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REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS.
The ADC references can be switched from the default values (VRT=2.05V, VRB=1.05V, ADC input
range=2V) to give a smaller ADC reference range (VRT=1.85V, VRB=1.25V, ADC input range=1.2V)
under control of the LOWREFS register bit. Setting LOWREFS=1 allows smaller input signals to be
accommodated.
Note:
When LOWREFS = 1 the output of the RLCDAC will scale if RLCDACRNG = 1. The max output from
RLCDAC will change from 2.05 to 1.85V and the step size will proportionally reduce.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. By default the device is fully
enabled. The EN bit allows the device to be fully powered down when set low. Individual blocks can
be powered down using the bits in Setup Register 5. When in one or two channel mode the unused
input channels are automatically disabled to reduce power consumption.
LINE-BY-LINE OPERATION
Certain linear sensors give colour output on a line-by-line basis (i.e. a full line of red pixels followed by
a line of green pixels followed by a line of blue pixels). Often the sensor will have only a single output
onto which these outputs are time multiplexed.
The WM8215 can accommodate this type of input by setting the LINEBYLINE register bit high. When
in this mode the green and blue input PGAs are disabled to save power. The analogue input signal
should be connected to the RINP pin. The offset and gain values that are applied to the Red input
channel can be selected, by internal multiplexers, to come from the Red, Green or Blue offset and
gain registers. This allows the gain and offset values for each of the input colours to be setup
individually at the start of a scan.
When register bit ACYC=0, the gain and offset multiplexers are controlled via the INTM[1:0] register
bits. When INTM=00, the red offset and gain control registers are used to control the Red input
channel. Likewise, INTM=01 selects the green offset and gain registers and INTM=10 selects the
blue offset and gain registers to control the Red input channel.
When register bit ACYC=1, ‘auto-cycling’ is enabled, and the input channel switches to the next offset
and gain registers in the sequence when a pulse is applied to the RSMP input pin. The sequence is
Red Green Blue Red… offset and gain registers applied to the single input channel. A write
to the Auto-cycle reset register (address 05h) will reset the sequence to a known state (Red registers
selected).
When auto-cycling is enabled, the RSMP pin alone cannot be used to control reset level clamping.
Reset level clamping may be enabled in this situation by setting the CLAMPCTRL and RLCEN bits so
that the logical AND of RSMP and VSMP closes the clamp switch.
Additionally, when auto-cycling is enabled, the RSMP pin cannot be used for reset sampling (i.e. CDS
must be set to 0).
CONTROL INTERFACE
The internal control registers are programmable via the serial digital control interface. The register
contents can be read back via the serial interface on pin OP[9]/SDO.
It is recommended that a software reset is carried out after the power-up sequence, before writing to
any other register. This ensures that all registers are set to their default values (as shown in Table 5).
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SERIAL INTERFACE: REGISTER WRITE
Figure 16 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit
address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word
(b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Setting address bit a4 to 0 indicates that the operation
is a register write. Each bit is latched on the rising edge of SCK. When the data has been shifted into
the device, a pulse is applied to SEN to transfer the data to the appropriate internal register.
SCK
a5
0
a3
a2
a1
a0
b7
b6
b5
b4
b3
b2
b1
b0
SDI
Address
Data Word
SEN
Figure 16 Serial Interface Register Write
A software reset is carried out by writing to Address “000100” with any value of data, (i.e. Data Word
= XXXXXXXX).
SERIAL INTERFACE: REGISTER READ-BACK
Figure 17 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus
as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing
address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of
corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of
SCK). Note that pin SDO is shared with an output pin, OP[9], therefore OEB should always be held
low and the OPD register bit should be set low when register read-back data is expected on this pin.
The next word may be read in to SDI while the previous word is still being output on SDO.
Figure 17 Serial Interface Register Read-back
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NORMAL OPERATING MODES
Table 3 below shows the normal operating modes of the device. The MCLK speed can be specified
along with the MCLK:VSMP ratio to achieve the desired sample rate.
NUMBER
OF
DESCRIPTION
CDS
AVAILABLE
MAXIMUM
SAMPLE RATE
TIMING
REQUIREMENTS
CHANNEL
MODE
CHANNELS
SETTINGS
3
2
1
Three channel
Pixel-by-Pixel
YES
YES
YES
20 MSPS
30 MSPS
45 MSPS
MCLK max = 60MHz
MONO = 0
Minimum MCLK:VSMP
ratio = 3:1
TWOCHAN = 0
Two channel
Pixel-by-Pixel
MCLK max = 60MHz
MONO = 0
Minimum MCLK:VSMP
ratio = 2:1
TWOCHAN = 1
One channel
Pixel-by-Pixel
MCLK max = 45MHz
MONO = 1
Minimum MCLK:VSMP
ratio = 1:1
TWOCHAN = 0
Table 3 WM8215 Normal Operating Modes
Note: In one channel mode the WM8215 can operate at 60MHz but DNL/INL values cannot be
guaranteed.
Table 4 below shows the different channel mode register settings required to operate the 8215 in 1, 2
and 3 channel modes.
MONO
TWOCHAN
CHAN[1:0]
XX
MODE DESCRIPTION
3-channel (colour mode)
0
0
0
1
1
0
XX
00
2-channel (Blue PGA disabled)
1-channel (monochrome) mode.
Red channel selected, Green and Blue PGAs disabled.
1-channel (monochrome) mode.
1
1
0
0
01
10
Green channel selected, Red and Blue PGAs disabled.
1-channel (monochrome) mode.
Blue channel selected, Red and Green PGAs disabled.
Invalid mode
1
1
0
1
11
XX
Invalid mode
Table 4 Sampling Mode Summary
Note: Unused input pins should be connected to AGND, unless reset level clamping is used.
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DEVICE CONFIGURATION
REGISTER MAP
The following table describes the location of each control bit used to determine the operation of the
WM8215.
ADDRES
S
DESCRIPTION
DEF
RW
BIT
(hex)
b7
b6
b5
b4
b3
b2
b1
b0
<a5:a0>
000001 (01h) Setup Reg 1
03
20
1F
00
00
00
00
20
00
00
00
00
80
80
80
-
RW
RW
RW
W
0
0
PGAFS[1]
PGAFS[0]
TWOCHAN
OPD
MONO
INVOP
CDS
0
EN
0
000010 (02h) Setup Reg 2
DEL[1]
CHAN[1]
DEL[0]
CHAN[0]
RLCDACRNG LOWREFS
000011 (03h) Setup Reg 3
0
1
RLCDAC[3] RLCDAC[2]
RLCDAC[1]
RLCDAC[0]
000100 (04h) Software Reset
000101 (05h) Auto-cycle Reset
000110 (06h) Setup Reg 4
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
0
0
0
0
INTM[1]
INTM[0]
ACYC
LINEBYLINE
REDPD
0
000111 (07h) Setup Reg 5
0
VRXPD
ADCREFPD VRLCDACPD
ADCPD
BLUPD
GRNPD
001000 (08h) Setup Reg 6
0
CLAMPCTRL
RLCEN
0
0
0
0
001001 (09h) Reserved
0
0
0
0
0
0
0
0
001010 (0Ah) Reserved
0
0
0
0
0
0
0
0
001011 (0Bh) Reserved
0
0
0
0
0
0
0
0
001100 (0Ch) Reserved
0
0
0
0
0
0
0
0
100000 (20h) DAC Value (Red)
100001 (21h) DAC Value (Green)
100010 (22h) DAC Value (Blue)
100011 (23h) DAC Value (RGB)
100100 (24h) PGA Gain LSB (Red)
100101 (25h) PGA Gain LSB (Green)
100110 (26h) PGA Gain LSB (Blue)
100111 (27h) PGA Gain LSB (RGB)
101000 (28h) PGA Gain MSBs (Red)
101001 (29h) PGA Gain (Green)
101010 (2Ah) PGA Gain (Blue)
101011 (2Bh) PGA Gain (RGB)
DACR[7]
DACG[7]
DACB[7]
DACR[6]
DACG[6]
DACB[6]
DACR[5]
DACG[5]
DACB[5]
DACR[4]
DACG[4]
DACB[4]
DACR[3]
DACG[3]
DACB[3]
DACR[2]
DACG[2]
DACB[2]
DACR[1]
DACG[1]
DACB[1]
DACR[0]
DACG[0]
DACB[0]
DACRGB[0]
PGAR[0]
PGAG[0]
PGAB[0]
PGARGB[0]
PGAR[1]
PGAG[1]
PGAB[1]
PGARGB[1]
DACRGB[7] DACRGB[6] DACRGB[5] DACRGB[4] DACRGB[3] DACRGB[2] DACRGB[1]
00
00
00
-
RW
RW
RW
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0C
0C
0C
-
RW
RW
RW
W
PGAR[8]
PGAG[8]
PGAB[8]
PGAR[7]
PGAG[7]
PGAB[7]
PGAR[6]
PGAG[6]
PGAB[6]
PGAR[5]
PGAG[5]
PGAB[5]
PGAR[4]
PGAG[4]
PGAB[4]
PGAR[3]
PGAG[3]
PGAB[3]
PGAR[2]
PGAG[2]
PGAB[2]
PGARGB[8] PGARGB[7] PGARGB[6] PGARGB[5] PGARGB[4] PGARGB[3] PGARGB[2]
Table 5 Register Map
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REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 5
ADDRESS
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
<A5:A0>
000001
(01h)
Setup Register
1
Global Enable
0 = complete power down,
0
EN
1
1 = fully active (individual blocks can be disabled using
individual powerdown bits – see setup register 5).
Select correlated double sampling mode:
1
2
CDS
1
0
0 = single ended mode,
1 = CDS mode.
Sampling mode select
MONO
0 = other mode (2 or 3-channel)
1 = Monochrome (1-channel) mode. Input channel
selected by CHAN[1:0] register bits, unused channel is
powered down.
TWOCHAN and MONO should not be set concurrently
Sampling mode select
3
TWOCHAN
PGAFS[1:0]
0
0 = other mode (1 or 3-channel)
1 = 2-channel mode. Inputs channels are Red and Green,
Blue channel is powered down.
TWOCHAN and MONO should not be set concurrently
Offsets PGA output to optimise the ADC range for different
polarity sensor output signals. Zero differential PGA input
signal gives:
5:4
00
0x = Invalid option. Either ‘10’ or ‘11’ must be set.
10 = Full-scale positive output (OP=1023) – use for
negative going video.
NB, Set INVOP=1 if zero differential input should
give a zero output code with negative going
video.
11 = Full-scale negative output (OP=0) - use for positive
going video
Must be set to 0
7:6
Not Used
00
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ADDRESS
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
<A5:A0>
000010
(02h)
Setup Register
2
Must be set to 0
Digitally inverts the polarity of output data.
1:0
Not Used
00
0
2
INVOP
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
Output Disable. This works with the OEB pin to control the
output pins.
3
OPD
0
0=Digital outputs enabled, 1=Digital outputs high
impedance
OEB
(pin)
OPD
OP pins
0
0
1
1
0
1
0
1
Enabled
High Impedance
High Impedance
High Impedance
4
LOWREFS
0
Reduces the ADC reference range (2*[VRT-VRB]), thus
changing the max/min input video voltages (ADC ref
range/PGA gain).
0 = ADC reference range = 2.0V
1 = ADC reference range = 1.2V
Sets the output range of the RLCDAC.
5
RLCDACRNG
DEL[1:0]
1
0 = RLCDAC ranges from 0 to AVDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
Controls the latency from sample to data appearing on
output pins
7:6
00
DEL
00
Latency
7 MCLK periods
8 MCLK periods
9 MCLK periods
10 MCLK periods
01
10
11
000011
(03h)
Setup Register
3
Controls RLCDAC driving VRLC/VBIAS pin to define single
ended signal reference voltage or Reset Level Clamp
voltage. See Electrical Characteristics section for ranges.
3:0
RLCDAC[3:0]
1111
Must be set to one
4
5
Reserved
Reserved
CHAN[1:0]
1
0
Must be set to zero
When MONO=0 this register bit has no effect
Monochrome mode channel select.
7:6
00
00 = Red
10 = Blue channel select
11 = Reserved
channel select
01 = Green
channel select
000100
(04h)
Software Reset
Any write to Software Reset causes all cells to be reset. It
is recommended that a software reset be performed after a
power-up before any other register writes.
000101
(05h)
Auto-cycle
Reset
Any write to Auto-cycle Reset causes the auto-cycle
counter to reset to RINP. This function is only required
when LINEBYLINE = 1.
000110
(06h)
Setup Register
4
Selects line by line operation. Line by line operation is
intended for use with systems which operate one line at a
time but with up to three colours shared on that one output.
0
LINEBYLINE
0
0 = normal operation,
1 = line by line operation.
When line by line operation is selected MONO is forced to
1 and CHAN[1:0] to 00 internally, ensuring that the correct
internal timing signals are produced. Green and Blue PGAs
are also disabled to save power.
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ADDRESS
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
<A5:A0>
When LINEBYLINE = 0 this bit has no effect.
1
ACYC
0
When LINEBYLINE = 1 this bit determines the function of
the RSMP input pin and the offset/gain register controls.
0 = RSMP pin enabled for either reset sampling (CDS) or
Reset Level Clamp control. Internal selection of gain/offset
multiplexers using INTM[1:0] register bits.
1 = Auto-cycling enabled by pulsing the RSMP input pin.
This means that each time a pulse is applied to this pin the
single input channel will switch to the next offset register
and gain register in the sequence. The sequence is
Red->Green->Blue->Red… offset and gain registers
applied to the red input channel.
When auto-cycling is enabled, the RSMP pin alone cannot
be used to control reset level clamping. Reset level
clamping may be enabled in this situation by setting the
CLAMPCTRL and RLCEN bits so that he logical AND of
RSMP and VSMP closes the clamp switch.
When auto-cycling is enabled, the RSMP pin cannot be
used for reset sampling (i.e. CDS must be set to 0).
3:2
INTM[1:0]
00
When LINEBYLINE=0 or ACYC=1 this bit has no effect.
When LINEBYLINE=1 and ACYC=0:
Controls the PGA/offset mux selector:
00 = Red PGA/Offset registers applied to input channel
01 = Green PGA/Offset registers applied to input channel
10 = Blue PGA/Offset registers applied to input channel
11 = Reserved.
Must be set to 0
7:4
0
Reserved
REDPD
GRNPD
BLUPD
ADCPD
0000
000111
(07h)
Setup Register
5
0
0
0
0
When set powers down red S/H, PGA
When set powers down green S/H, PGA
When set powers down blue S/H, PGA
When set powers down ADC. Allows reduced power
consumption without powering down the references which
have a long time constant when switching on/off due to the
external decoupling capacitors.
1
2
3
4
VRLCDACPD
0
When set powers down 4-bit RLCDAC, setting the output to
a high impedance state and allowing an external reference
to be driven in on the VRLC/VBIAS pin.
When set disables VRT, VRB buffers to allow external
references to be used.
5
6
ADCREFPD
VRXPD
0
0
When set disables VRX buffer to allow an external
reference to be used.
7
4:0
5
Not Used
Not Used
RLCEN
0
00000
1
Must be set to 0
001000
(08h)
Setup Register
6
Must be set to 0
Reset Level Clamp Enable. When set Reset Level
Clamping is enabled. The method of clamping is
determined by CLAMPCTRL.
6
CLAMPCTRL
0
0 = RLC switch is controlled directly from RSMP input pin:
RSMP = 0: switch is open
RMSP = 1: switch is closed
1 = RLC switch is controlled by logical combination of
RSMP and VSMP.
RSMP && VSMP = 0: switch is open
RSMP && VSMP = 1: switch is closed
Must be set to 0
7
Reserved
0
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WM8215
Production Data
ADDRESS
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
<A5:A0>
100000
(20h)
Offset DAC
(Red)
Red channel 8-bit offset DAC value (mV) =
255*(DACR[7:0]-127.5)/127.5
7:0
7:0
7:0
DACR[7:0]
DACG[7:0]
DACB[7:0]
10000000
10000000
10000000
-
100001
(21h)
Offset DAC
(Green)
Green channel 8-bit offset DAC value (mV) =
255*(DACG[7:0]-127.5)/127.5
100010
(22h)
Offset DAC
(Blue)
Blue channel 8-bit offset DAC value (mV) =
255*(DACB[7:0]-127.5)/127.5
Offset DAC
(RGB)
A write to this register location causes the red, green and
blue offset DAC registers to be overwritten by the new
value
7:0 DACRGB[7:0]
100011
(23h)
0
PGAR[0]
0
This register bit forms the LSB of the red channel PGA gain
code. PGA gain is determined by combining this register
bit and the 8 MSBs contained in register address 28 hex.
100100
(24h)
PGA Gain LSB
(Red)
7:1
0
Reserved
PGAG[0]
0000000
0
Must be set to 0
This register bit forms the LSB of the green channel PGA
gain code. PGA gain is determined by combining this
register bit and the 8 MSBs contained in register address
29 hex.
100101
(25h)
PGA Gain LSB
(Green)
7:1
0
Reserved
PGAB[0]
0000000
0
Must be set to 0
100110
(26h)
PGA Gain LSB
(Blue)
This register bit forms the LSB of the blue channel PGA
gain code. PGA gain is determined by combining this
register bit and the 8 MSBs contained in register address
2A hex.
7:1
0
Reserved
0000000
-
Must be set to 0
PGARGB[0]
100111
(27h)
PGA Gain LSB
(RGB)
Writing a value to this location causes red, green and blue
PGA LSB gain values to be overwritten by the new value.
Must be set to 0
7:1
7:0
Reserved
0000000
101000
(28h)
PGA gain
MSBs
Bits 8 to 1 of red PGA gain. Combined with red LSB
register bit to form complete PGA gain code. This
determines the gain of the red channel PGA according to
the equation:
PGAR[8:1]
00001100
(Red)
Red channel PGA gain (V/V) = 0.66 + PGAR[8:0]x7.34/511
PGA gain
MSBs (Green)
Bits 8 to 1 of green PGA gain. Combined with green LSB
register bit to form complete PGA gain code. This
determines the gain of the green channel PGA according to
the equation:
7:0
7:0
PGAG[8:1]
PGAB[8:1]
00001100
101001
(29h)
Green channel PGA gain (V/V) = 0.66 +
PGAG[8:0]x7.34/511
101010
(2Ah)
PGA gain
MSBs
Bits 8 to 1 of blue PGA gain. Combined with blue LSB
register bit to form complete PGA gain code. This
determines the gain of the blue channel PGA according to
the equation:
00001100
(Blue)
Blue channel PGA gain (V/V) = 0.66 + PGAB[8:0]x7.34/511
101011
(2Bh)
PGA gain MSBs
(RGB)
A write to this register location causes the red, green and
blue PGA MSB gain registers to be overwritten by the new
value.
7:0 PGARGB[8:1]
-
Table 6 Register Control Bits
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WM8215
Production Data
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 18 External Components Diagram
RECOMMENDED EXTERNAL COMPONENT VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
De-coupling for DVDD1.
C1
C2
100nF
100nF
100nF
1F
De-coupling for DVDD2.
De-coupling for AVDD.
C3
Ceramic de-coupling between VRT and VRB (non-polarised).
De-coupling for VRB.
C5
C6
100nF
100nF
100nF
100nF
10F
De-coupling for VRX.
C7
De-coupling for VRT.
C8
De-coupling for VRLC.
C9
Reservoir capacitor for DVDD1.
Reservoir capacitor for DVDD2.
Reservoir capacitor for AVDD.
C10
C11
C12
10F
10F
Table 7 External Components Descriptions
PD, Rev 4.3, September 2012
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WM8215
Production Data
PACKAGE DIMENSIONS
FL: 32 PIN QFN PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm LEAD PITCH
DM101.A
D
D2
DETAIL 1
32
25
L
1
24
4
INDEX AREA
(D/2 X E/2)
EXPOSED
GROUND
PADDLE
6
E2
E
17
8
aaa
C
2 X
16 15
9
1
b
aaa
C
2 X
B
M
C
A
B
bbb
e
TOP VIEW
BOTTOM VIEW
ccc
C
A3
A
5
0.08
C
A1
C
SIDE VIEW
SEATING PLANE
M
45°
DETAIL 2
M
0.30
EXPOSED
GROUND
PADDLE
DETAIL 1
W
Exposed lead
T
A3
G
H
b
Half etch tie bar
DETAIL 2
Dimensions (mm)
Symbols
MIN
0.80
0
NOM
0.90
0.02
MAX
1.00
0.05
NOTE
A
A1
A3
0.203 REF
0.25
1
b
0.18
3.30
3.30
0.30
3.60
D
5.00 BSC
2
2
D2
E
E2
e
3.45
5.00 BSC
3.45
3.60
0.50 BSC
0.20
G
H
L
0.1
0.40
0.103
0.30
0.50
T
W
0.15
Tolerances of Form and Position
aaa
bbb
ccc
0.15
0.10
0.10
REF:
JEDEC, MO-220, VARIATION VHHD-5.
NOTES:
1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC, MO-220, VARIATION VHHD-5.
3. ALL DIMENSIONS ARE IN MILLIMETRES.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002.
5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.
7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
PD, Rev 4.3, September 2012
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WM8215
Production Data
IMPORTANT NOTICE
Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale,
delivery and payment supplied at the time of order acknowledgement.
Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the
right to make changes to its products and specifications or to discontinue any product or service without notice. Customers
should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.
Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.
Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.
In order to minimise risks associated with customer applications, the customer must use adequate design and operating
safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer
product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for
such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.
Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where
malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.
Any use of products by the customer for such purposes is at the customer’s own risk.
Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other
intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or
services might be or are used. Any provision or publication of any third party’s products or services does not constitute
Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document
belong to the respective third party owner.
Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is
accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is
not liable for any unauthorised alteration of such information or for any reliance placed thereon.
Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in
this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or
accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any
reliance placed thereon by any person.
ADDRESS:
Wolfson Microelectronics plc
Westfield House
26 Westfield Road
Edinburgh
EH11 2QB
Tel :: +44 (0)131 272 7000
Fax :: +44 (0)131 272 7001
Email :: sales@wolfsonmicro.com
PD, Rev 4.3, September 2012
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WM8215
Production Data
REVISION HISTORY
DATE
REV
ORIGINATOR
CHANGES
04/09/12
4.3
JMacD
Order codes changed from WM8215SEFL and WM8215SEFL/R to
WM8215CSEFL and WM8215CSEFL/R to reflect change to copper wire
bonding.
04/09/12
4.3
JMacD
Package Diagram changed to DM101.A
PD, Rev 4.3, September 2012
31
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