SCG4503 [CONNOR-WINFIELD]
Synchronous Clock Generator;
| 型号： | SCG4503 |
| 厂家： | 
CONNOR-WINFIELD CORPORATION |
| 描述： | Synchronous Clock Generator |
| 文件： | 总16页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SCG4503
Synchronous Clock
Generator
PLL
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630-851-4722
Fax: 630-851-5040
www.conwin.com
Features
• 27 - 64 Hz Jitter Bandwidth
• Phase Locked Output Frequency Control
• Intrinsically Low Jitter Crystal Oscillator
• LVPECL Outputs with Disable Function
• Dual Input References
• LOR & LOL combined alarm output
• Force Free Run Function
• Automatic Free Run operation on loss of
both References A & B
• Input Duty Cycle Tolerant
• 3.3V dc Power Supply
• Small Size: 1 Square Inch
Bulletin
SG082
Page
1 of 16
Revision
00
Date
17 JUNE 05
Issued By
MBatts
Maximum Dimension Package Outline
General Description
Figure 1
The SCG4503 is a mixed-signal phase locked loop
generating LVPECL outputs from an intrinsically low
jitter, voltage controlled, crystal oscillator. The LVPECL
outputs may be disabled.
The SCG4503 can lock to one of two external
references, which is selectable using the SELAB input
select pin. The unit has a fast acquisition time of about
1.5 seconds and it is tolerant of different reference duty
cycles.
The SCG4503 includes an alarm output that
indicates deviations from normal operation. If a Loss-
of-Reference (LOR) or Loss-of-Lock (LOL) is detected
the alarm with indicate the need for a reference
rearrangement. If both references A and B are absent
the module will enter Free Run operation. The FRstatus
pin will indicate that the module is in Free Run
operation. Frequency stability during Free Run
operation is guaranteed to 20 ppm. Additionally the
Free Run mode may be entered manually.
The package dimensions are 1” x 1.025” x .45” on a
6 layer FR4 board with castellated pins. Parts are
assembled using high temperature solder to withstand
63/37 alloys, 180°C surface mount reflow processes.
Block Diagram
Figure 2
10 kΩ
FREE RUN STATUS
FORCE
10 kΩ
FREE RUN
ALARM
33 Ω
Q
REFA
LOW JITTER
VCXO
8 KHz PHASE
33 Ω
DPFD
ANALOG
FILTER
ALIGNER
REFB
QN
1 / N
SEL AB
10 kΩ
ENABLE/
TRI-STATE
10 kΩ
Absolute Maximum Rating
Table 1
Symbol
Parameter
Minimum
-0.5
Nominal
Maximum
Units
Volts
Volts
°C
Notes
1.0
Vcc
Vi
Power Supply Voltage
Input Voltage
-
-
-
+4.0
+5.5
+100
-0.5
1.0
Ts
Storage Temperature
-65.0
1.0
Data Sheet #: SG082
Page 2 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Operating Specifications
Table 2
Symbol
Parameter
Minimum
Nominal
Maximum
Units
kHz
Notes
RIN
Input Reference Frequency (CMOS)
Output Frequency (LVPECL)
Power Supply Voltage
Power Supply Current
Temperature Range
-
8
-
fOUT
Vcc
-
155.52
-
MHz
Volts
mA
3.135
-
3.3
3.465
300
70
20
0.2
25
64
-
2.0
5.0
Icc
250
To
0
-
-
-
-
-
-
°C
Ffr
Free Run Frequency Range
Phase Gain
-20
-
ppm
Φgain
Fcap
Fbw
tjtol
dB@~0.1Hz
ppm
Capture/pull-in range
Jitter Filter Bandwidth
-25
27
Hz
3.0
Input Jitter Tolerance
31.25
µs
8 kHz Ref. units
(Input Jitter Frequencies ≥ 10 Hz)
taq
Typical Acquisition Time Data
Acquisition from a cold power-up:
Phase lock within 12ns:
Phase lock settled:
Alarm time:
<3
<3
<1
sec.
sec.
sec.
Acquisition from Free Run:
Phase lock within 12ns:
Phase lock settled:
Alarm time:
<3
<3
1
sec.
sec.
sec.
Frequency lock with a 20PPM reference frequency step: Typically 30ms.
Phase lock during a switch between equal frequency references: Typically 0.1s, no alarm should be issued
trf
Output Rise and Fall Time (20% 80%)
Output Duty Cycle
100
40
225
50
350
60
ps
%
4.0
DC
MTIEsr
MTIE at Synchronization Rearrangement
Dynamic Offset Range (0°- 70°)
Dynamic Offset Range (25°- 70°)
Unit to Unit Phase Differential
GR-253-CORE.1999 R5-135
5.0,6.0
-
-
-
-
-
-
20
ns
ns
ns
13
100
7.0
Output Jitter Specifications
Table 3
Jitter BW 10 Hz - 1 MHz
SONET Jitter BW 12 kHz - 20 MHz
Frequency (MHz)
155.52
pS (RMS)
m UI
pS (RMS)
m UI
20Typ.
3.110 Typ.
1 Max.
0.156 Max.
NOTES:
1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF)
3.0 3db loop response.
4.0 50-ohm load biased to 1.3 volts.
5.0 Entry into Free Run doesn’t meet requirement for initial 2.33 seconds of self-timing.
6.0 The wider bandwidth of this model may result in a break in the GR-253-CORE, R5-135 Switching Mask for observation times of <50ms
7.0 Under rapidly changing input conditions. (-11ppm to +11ppm)
Data Sheet #: SG082
Page 3 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Input And Output Characteristics
Table 4
Symbol
Parameter
Minimum
Nominal
Maximum
Units
Notes
CMOS Input and Output Characteristics
Vih
High Level Input Voltage
Low Level Input Voltage
I/O to Output Valid
2.0
0.0
-
-
-
-
-
-
-
-
5.5
0.8
10
10
-
V
Vil
V
Tio
Cl
ns
pF
V
Output Capacitance
-
Voh
Vol
Tir
High Level Output Voltage
Low Level Output Voltage
Input Reference Pulse Width
2.4
-
0.4
-
V
12.5
ns
PECL Output Characteristics
Voh
High Level PECL Voltage
2.27
2.34
1.51
-
2.52
1.68
10
V
Vol
Low Level PECL Voltage
Output Capacitance
1.49
V
Cl
-
-
pF
ps
Tskew
Differential Output Skew
50
-
Input Selection / Output Response
Table 5
INPUTS
REFA
OUTPUTS
ALARM
NOTE
RESET
ENABLE SELAB
REFB
X
FR
X
X
1
FRstatus
Q
X
0
QN
1
X
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
X
X
X
0
1
0
1
1
0
X
X
1
X
1
0
0
0
0
0
0
1
X
X
X
0
0
1
0
1
0
1
X
1
FR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FR
RA
RB
U
A
A
0
A
A
0
NA
NA
A
A
0
A
0
RB
U
NA
NA
NA
0
A
0
RA
FR
NA
0
NOTES:
A
Active
FR Free Run Mode
NA Not Active
RA Locked to Reference A
RB Locked to Reference B
U
X
Unstable (due to conditions shown, switch to active reference or Free Run)
Don’t care
Data Sheet #: SG082
Page 4 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE Measurement
Figure 3
1.0E-9
100.0E-12
0.01
0.1
1
Observation Window (Tau)
(sec)
10
100
Typical TDEV Measurement
Figure 4
100.0E-12
10.0E-12
1.0E-12
0.001
0.01
0.1
1
10
100
Tau (sec)
Data Sheet #: SG082
Page 5 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of
Reference A, No Modulation.
10.0E-6
Figure 5
Requirement Mask
1.0E-6
Objective Mask
100.0E-9
10.0E-9
1.0E-9
0.001
0.01
0.1
1
10
100
1000
Observation Window (Tau)
(sec)
*NOTE: The wider bandwidth of this model may result in a break in the GR-253-CORE, R5-135
Switching Mask for observation times of <50ms.
Circuit Board Footprint & Keepout Recommendations
Figure 6
0.8650
[21.97 mm]
0.0650
[1.65 mm]
Keep Out
0.8400
[21.34 mm]
1.0400
[26.42 mm]
Area
0.1000
[2.54 mm]
0.1000
[2.54 mm]
0.0350
[0.89 mm]
1.0700
[27.18 mm]
Data Sheet #: SG082
Page 6 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Pin Description
Table 6
Pin #
Pin Name
Pin Information
Note
9.0
1
ENABLE/TRI-STATE
VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated)
No Connection, Internal Factory Programming Input.
No Connection, Internal Factory Programming Input.
CMOS Reference Frequency Input.
Input Reference Select Pin. (REFA = 0, REFB = 1)
RESET. (RESET = 1)
2
TCK
TDO
REFA
SELAB
RESET
REFB
Vee
8.0
3
8.0
4
5
9.0
9.0
6
7
CMOS Reference Frequency Input.
Ground.
8
9
FRstatus
Vcc
Free Run Status. (FR = 1)
10
11
12
13
14
15
16
17
18
Supply Voltage relative to ground.
No Connection.
N/C
8.0
ALARM
FR
Loss of Reference / Lock alarm. (Alarm = 1)
Force Free Run. (Phase Lock = 0, Free Run = 1)
No Connection, Internal Factory Programming Input.
No Connection, Internal Factory Programming Input.
LVPECL Complementary Output.
Ground.
9.0
8.0
8.0
TDI
TMS
QN
Vee
Q
LVPECL Output.
NOTES
8.0 Do not connect pin
9.0 Input pulled to ground
Ordering Information
SCG{XXXX}-{FFF.FFF}{M}
XXXX equals a specific model (4503)
FFF.FFF equals the Oscillator Output frequency (155.52)
M equals MHZ and is added to all part numbers
Example: To order an SCG4503 with an Oscillator Output of 155.52 MHz,
Order part number SCG4503-155.52M
Data Sheet #: SG082
Page 7 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Reference Condition Alarm Timing
Figure 7
Start-up
Region
Alarm Output
(LOR + LOL)
LOR
(Internal Signal)
4
LOL
(Internal Signal)
2
1
1
Phase Detector
(Internal Signal)
3
External Reference
(Selected Input A or B)
Internal Reference
(Internal Signal)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
AlarmTiming Legend
Use for all alarm timing diagrams
Table 7
8 kHz Reference Input
< 31.25 µsec
1
2
3
4
5
31.25 µsec
> 31.25 µsec
125 µsec wide range
Minimum pulse width = 62.5 µsec
During Start-up, The LOL Alarm will pulse
during the first few seconds of operation
Start-up Region
Data Sheet #: SG082
Page 8 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Lock Condition Alarm Timing
Figure 8
Alarm Output
(LOR + LOL)
LOR
(Internal Signal)
LOL
(Internal Signal)
5
1
1
1
1
1
Phase Detector
(Internal Signal)
3
3
External Reference
(Selected Input A or B)
Internal Reference
(Internal Signal)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Data Sheet #: SG082
Page 9 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when both are good signals
Figure 9
Ref A
Ref B
Alarm
LOL portion of
Alarm is
Blanked
0.5 sec
Sel A/B
New Reference
Qualification time
Switch from A to B when Reference B is lost
Figure 10
Ref A
Ref B
Alarm
~8ns
Sel A/B
Data Sheet #: SG082
Page 10 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B after Reference A is lost
Figure 11
Ref A
Ref B
Alarm
Blanked
Alarm
156.25µs (8 kHz Ref units)
126µs (19.44 MHz Ref units)
Sel A/B
New Reference
Qualification time
Switch from A to B when A is out of range
Figure 12
Out of
Range
Ref A
Ref B
Alarm
In
Range
Alarm
Blanked
Sel A/B
New Reference
Qualification time
Data Sheet #: SG082
Page 11 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B when B is out of range
Figure 13
In
Range
Ref A
Ref B
Alarm
Out of
Range
Alarm
Blanked
SEL A/B
New Reference
Qualification Time
0.5 sec.
Switch from A to B when both references have been lost and Ref B returns
(Automatic Free Run)
Figure 14
Ref A
Ref B
Alarm
Blanked
Alarm
Sel A/B
New Reference
Qualification time
Free Run
Status
Data Sheet #: SG082
Page 12 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended PECLTermination
Figure 15
3.3 VDC
3.3 VDC
3.3 VDC
130
82
Vcc
Q
Vcc
D
50 OHM Transmission Line
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
GND
GND
130
82
3.3 VDC
3.3 VDC
Vcc - 2 VDC
3.3 VDC
50
Vcc
Q
Vcc
D
50 OHM Transmission Line
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
QN
DN
GND
GND
50
Vcc - 2 VDC
3.3 VDC
3.3 VDC
150
Vcc
Q
Vcc
D
50 OHM Transmission Line
50 OHM Transmission Line
SCGxxx
LVPECL
OUTPUT
LVPECL
INPUT
100
QN
DN
GND
GND
150
If PECL outputs do not drive a long line (< 0.5”),
a single 150Ω termination resistor to ground may be used for each pin.
Data Sheet #: SG082
Page 13 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Tape and Reel Packaging
Figure 16
Data Sheet #: SG082
Page 14 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 17
250
200
150
Temp
(Deg C)
100
50
0
1
2
3
4
5
6
7
8
Time (minutes)
Recommended Reflow Profile
Peak Temp:
217 Deg C
1.5 Deg
Max Rise Slope:
C/Sec
Time Above 150 C: 100 Sec
Model Comparison Table
Table 8
Max
Model
Input
Ref Freq
Duty
Cycle
Oscillator Output
(Synchronized Output)
Notes
SCG4500
SCG4503
SCG4510
SCG4520
SCG4540
2@8 kHz
40/60
40/60
40/60
40/60
40/60
77.76 MHz,155.52 MHz,125 MHz
155.52 MHz
Basic Model
2@8 kHz
27-64 Hz Jitter Bandwidth
2@1.544 MHz
2@19.44 MHz
2@10 kHz
155.52 MHz
77.76 MHz,155.52 MHz
163.84 MHz
Other low jitter line card solutions from Connor-Winfield
SCG51 Series
Single input, jitter filtered with Free Run, 1 CMOS and 3 LVPECL outputs up to 622.08 MHz.
Single input, frequency selectable, LVPECL clock smoothers from 77.76 to 777.76 MHz.
Single input, jitter filtered with 20ppm Free Run, CMOS outputs from 8 kHz to 125.0 MHz.
Dual input, jitter filtered with Free Run, CMOS outputs up to 125.0 MHz.
SCG102A/104A
SCG2000 Series
SCG2500 Series
SCG3000 Series
SCG4000 Series
SCG4600 Series
Single input, jitter filtered with Dual LVPECL outputs.
Single input, jitter filtered with 20ppm Free Run, LVPECL outputs from 77.76 MHz to 180 MHz.
Dual input, jitter filtered with Free Run, 1 CML differential pair output up to 622.08 MHz.
Data Sheet #: SG082
Page 15 of 16
Rev: 00 Date: 06/17/05
© Copyright 2005 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Revision
Revision Date
Note
00
06/17/05
Final Release
相关型号：
SCG4525
PLL Based Clock Driver, 4000/14000/40000 Series, 1 True Output(s), 1 Inverted Output(s), 1 X 1.025 INCH, 0.45 INCH HEIGHT, SMT-18
CONNOR-WINFIE
©2020 ICPDF网 联系我们和版权申明