SFX-424G_技术文档

SFX-424G

Synchronous Clock

Generators

PLL

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630-851-5040

www.conwin.com

Applications

SONET / SDH / ATM

DWDM / FDM

FEC (Forward Error Correction)

Features

• 3.3V High Precision PLL

• Jitter Generation OC-192 Compliant

• Surface Mount

• Accepts up to 4 Inputs from an External MUX

• Inputs Compatible with CMOS/LVDS/LVPECL

• Frequency Translation up to 800 MHz

• Alarm detection for Loss of Lock/ Loss of Reference condition

• ROHS Compliant

Bulletin

SG124

Revision

05

Date

11 Sept 2014

General Description

The SFX-424G is a high precision frequency translator that

translates up to four inputs from 8 kHz to 100MHz, to output

frequencies between 8 MHz and 800 MHz. The SFX-424G

supports all major FEC rates such as 15/14, 255/237 etc.

SFX-424G is well suited for use in line cards, service

termination cards and similar functions to provide reliable

reference, phase locked, synchronization for TDM, PDH, SONET

and SDH network equipment. The SFX-424G provides a jitter

ﬁltered, wander following output signal synchronized to a

superior Stratum or peer input reference signal.

The SFX-424G includes a lock detect alarm output. The

PLL control voltage is brought out through a 470 kΩ resistor

and can be used to determine when the pull range limits are

reached. The LVPECL outputs may be put into the tri-state high

impedance condition for external testing purposes by asserting

a high signal to the Enable/Disable pin.

Parts are assembled using high temperature solder to

withstand surface mount reﬂow process. This product is

compliant with all required ROHS speciﬁcations.

Absolute Maximum Rating

Table 1

Symbol

Parameter

PowerꢀSupplyꢀVoltageꢀ(OptionD)ꢀ

InputꢀVoltageꢀ ꢀ

StorageꢀTemperatureꢀ(OptionF)ꢀ

StorageꢀTemperatureꢀ(OptionA)ꢀ

Minimum

-0.3ꢀ

Nominal

Maximum

4.0ꢀ

Vccꢀ+0.3Vꢀ

125ꢀ

Units Notes

Vccꢀ

VIꢀ

Tsꢀ

ꢀ

-ꢀ

Volts

°C

ꢀ

-0.2ꢀ

-55ꢀ

-40ꢀ

85ꢀ

°C

Speciﬁcations

Table 2

Symbol

f_INꢀ

f_OUTꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ

ꢀ

Parameter

InputꢀFrequenciesꢀ

OutputꢀFrequenciesꢀ(LVPECL)ꢀ19.44ꢀMꢀ

OutputꢀFrequenciesꢀ(LVCMOS)ꢀ

SupplyꢀVoltageꢀ(3.3ꢀVDC)ꢀ

SupplyꢀCurrentꢀ

Minimum

8ꢀkꢀ

Nominal

Maximum

100ꢀMꢀ

Hz

130ꢀMꢀꢀ

3.46ꢀ

Units Notes

Hz

ꢀ

-ꢀ

800ꢀMꢀ

-ꢀ

3.3ꢀ

-ꢀ

8ꢀMꢀ

3.13ꢀ

60ꢀ

Hz

Volts

Vccꢀ

ꢀ

-ꢀ

I_CC

ꢀ

mA

LVCMOSꢀINPUT

ꢀꢀꢀV_IHꢀ

ꢀꢀꢀV_ILꢀ

2ꢀ

-0.3ꢀ

-ꢀ

VCCꢀ

0.8ꢀ

Volts

ꢀ

LVPECLꢀINPUT

ꢀꢀꢀV_IHꢀ

ꢀꢀꢀV_ILꢀ

ꢀ

1.49ꢀ

0.86ꢀ

ꢀ

-ꢀ

2.72ꢀ

2.125ꢀ

Volts

LVCMOSꢀOUTPUTꢀ(OptionꢀA)ꢀ

LVPECLꢀOUTPUTꢀ(OptionꢀF)

TYP.ꢀLVCMOS

ꢀꢀꢀV_OHꢀ

ꢀꢀꢀV_OLꢀ

ꢀꢀꢀT_R/T_Fꢀ

SYMꢀ

ꢀ

2.275ꢀ

-ꢀ

45ꢀ

-ꢀ

0.6ꢀ

ꢀ

V

ns

%

1.68ꢀ

1.5ꢀ

55ꢀ

-ꢀ

Rise/FallꢀTimeꢀ @20%ꢀtoꢀ80%ꢀ ꢀ

OutputꢀSymmetryꢀ

JitterꢀGenerationꢀRMSꢀ

(12ꢀkHzꢀ-ꢀ20ꢀMHz)

ꢀ

J_GEN1

ꢀ

0.35ꢀ

psꢀ

1.0

2.0

3.0

ꢀ

J_GEN2

ꢀ

J_TRANꢀ

APRꢀ

ꢀ

JitterꢀGenerationꢀRMSꢀ

(12ꢀkHzꢀ-ꢀ20ꢀMHz)

JitterꢀTransferꢀ ꢀ

InputꢀFrequencyꢀTrackingꢀ

OperatingꢀTemperatureꢀ

ꢀ

-ꢀ

0.50ꢀ

-ꢀ

psꢀ

ꢀ

-ꢀ

40ꢀ

-40ꢀ

0ꢀ

-ꢀ

0.1ꢀ

ꢀ

85ꢀ

70ꢀ

dBꢀ

ppm

°C

T_OP

ꢀ

Fꢀ=ꢀ

Cꢀ=

ꢀ

°C

SSBꢀPhaseꢀNoiseꢀ(forꢀSFX-424G-DFF-A10Zꢀonly)ꢀ

ꢀ

4.0ꢀꢀ

ꢀ

atꢀ10Hzꢀoffsetꢀ ꢀ

atꢀ100Hzꢀoffsetꢀ

atꢀ1kHzꢀoffsetꢀ ꢀ

atꢀ10kHzꢀoffsetꢀ

atꢀ100kHzꢀoffsetꢀ

atꢀ1MHzꢀoffsetꢀꢀ

atꢀ10MHzꢀoffsetꢀ

ꢀ

-ꢀ

-57ꢀ

-45ꢀ

dBc/Hzꢀ

dBc/Hz

-92ꢀ

-80ꢀ

-120ꢀ

-138ꢀ

-150ꢀ

-157ꢀ

-160ꢀ

-110ꢀ

-135ꢀ

-145ꢀ

-147ꢀ

-150ꢀ

0ꢀ

/

PhaseꢀOffsetꢀ ꢀ

ꢀ

-ꢀ

5ꢀ

15ꢀ

ns

OFFꢀ

NOTES:ꢀ

ꢀ

1.0ꢀꢀ155.52ꢀMHzꢀ

2.0ꢀꢀ156.25ꢀMHz

ꢀ

3.0ꢀꢀGR-253-CORE,ꢀSec.ꢀ5.6.2.1.2

4.0ꢀꢀForꢀotherꢀmodelsꢀandꢀfrequencies,ꢀconsultꢀfactory.

Data Sheet #: SG124_SFX-424G Page 2

Rev: 05

Date: 09/11/14

Functional Block Diagram

Figure 1

LD

(Pin 10)

470 kΩ

V_MON

(Pin 5)

F

OUT

(Pin 8)

Frequency

Divider

Loop

Filter

F_IN

(Pin 13)

OSC

0.01 µF

CFOut

(Pin 9)

Frequency

Divider

10 kΩ

SEL0

(Pin 1)

Microprocessor

SEL1

(Pin 2)

10 kΩ

OD

(Pin 6)

Pin Description

Table 3

PIN # SYMBOL

I/O

Level

Function

1

SEL0

SEL1ꢀ

GNDꢀ

ꢀ

I

Iꢀ

LVTTL

LVTTLꢀ

Supplyꢀ

Input Frequency Select .* 10kΩ Pull down resistor

InputꢀFrequencyꢀSelectꢀ.*ꢀ10kΩꢀPullꢀdownꢀresistor

Ground

2ꢀ

3ꢀ

4ꢀ

5ꢀ

ꢀ

6ꢀ

ꢀ

GNDꢀ

ꢀ

Oꢀ

ꢀ

Iꢀ

ꢀ

Missingꢀ

VMONꢀ

Analogꢀ

ꢀVCXOꢀControlꢀVoltageUnderꢀlockedꢀconditionsꢀVMONꢀshouldꢀ

beꢀ>ꢀ0.3Vꢀandꢀ<3.0V.ꢀꢀTheꢀInputꢀFrequencyꢀmayꢀbeꢀoutꢀofꢀ

rangeꢀifꢀtheꢀvoltageꢀisꢀoutsideꢀofꢀthisꢀvoltageꢀrange.

OutputꢀDisable

ꢀ

ODꢀ

ꢀ

LVCMOSꢀ

ꢀ

Disableꢀ=ꢀLogicꢀ1

ꢀ

Enableꢀ=ꢀLogicꢀ0ꢀorꢀNoꢀConnect

Ground

7ꢀ

8ꢀ

9ꢀ

ꢀ

GNDꢀ

FOUTꢀ

CFOUTꢀ

GNDꢀ

Oꢀ

ꢀ

Oꢀ

ꢀ

Supplyꢀ

LVPECLꢀorꢀLVCMOSꢀ

LVPECLꢀorꢀGNDꢀ

FrequencyꢀOutput

ComplementaryꢀFrequencyꢀOutput

Note:ꢀForꢀtheꢀLVCMOSꢀOption,ꢀthisꢀ

connectionꢀisꢀtiedꢀtoꢀGND

ꢀ

LDꢀ

ꢀ

10ꢀ

ꢀ

LVCMOSꢀ

LockꢀDetect

Lockedꢀ=ꢀLogicꢀ1

ꢀ

LossꢀofꢀSignalꢀ=ꢀLogicꢀ0

11ꢀ

12ꢀ

13ꢀ

ꢀ

GNDꢀ

FINꢀ

ꢀ

GNDꢀ

Iꢀ

Supplyꢀ

LVPECLꢀorꢀLVCMOSꢀ

Ground

InputꢀFrequencyNote:ꢀInputꢀisꢀACꢀcoupled

forꢀhandlingꢀeitherꢀLVCMOSꢀorꢀLVPECLꢀinputꢀsignals

PowerꢀSupplyꢀVoltageꢀ(3.3Vꢀ 5%)

ꢀ

14ꢀ

VCCꢀ

Supplyꢀ

Data Sheet #: SG124_SFX-424G Page 3

Rev: 05

Date: 09/11/14

Output Load and Power Supply Filtering Recommendations

Figure 2

*

It is highly recommended

*

that either a linear regulator

or bypass capacitors be

used. Typical values would

be 10 uF, 0.1 uF, 100 pF.

Only Required for Option F

V_CC-2 V_DC

LD

(Pin 10)

470 kΩ

V_MON

(Pin 5)

50Ω

F_IN

(Pin 13)

REF 1

REF 2

F_OUT

Frequency

Divider

Loop

Filter

OSC

(Pin 8)

REF 3

REF 4

0.01 µF

CF_OUT

(Pin 9)

Frequency

Divider

10 kΩ

SEL0

(Pin 1)

Microprocessor

SEL1

(Pin 2)

10 kΩ

OD

(Pin 6)

Package Dimensions

Recommended Footprint Dimensions

Figure 3

Figure 4

Data Sheet #: SG124_SFX-424G Page 4

Rev: 05

Date: 09/11/14

Solder Proﬁle

Figure 5

Temperature

260°C

220°C

180°C

150°C

120°C

0

Time

120 S

Max.

10 S

60 S

Max.

360 Sec. Max.

Meets IPC/JEDEC J-STD-020C

Data Sheet #: SG124_SFX-424G Page 5

Rev: 05

Date: 09/11/14

Standard Frequencies

Table 4

ꢀ

8ꢀkHzꢀ

16ꢀkHzꢀ

64ꢀkHzꢀ

Cꢀ

Dꢀ

Eꢀ

Fꢀ

Hꢀ

Jꢀ

38.880ꢀMHzꢀ

49.152ꢀMHzꢀ

204.80ꢀMHzꢀ

51.84ꢀMHzꢀ

61.44ꢀMHzꢀ

77.76ꢀMHzꢀ

82.944ꢀMHzꢀ

100.00ꢀMHzꢀ

X

Y

Z

0

1

2

3

4

5

6

7

8

9

A

S

1.024ꢀMHzꢀ

1.544ꢀMHzꢀ

2.048ꢀMHzꢀ

4.096ꢀMHzꢀ

8.192ꢀMHzꢀ

10.00ꢀMHzꢀ

16.3840ꢀMHzꢀ

10.24ꢀMHzꢀ

19.440ꢀMHzꢀ

20.480ꢀMHzꢀ

26.00ꢀMHzꢀ

32.768ꢀMHzꢀ

ꢀ

Kꢀ

Lꢀ

Mꢀ

Nꢀ

Oꢀꢀ

Pꢀ

Rꢀ

Tꢀ

139.2640ꢀMHzꢀ

155.520ꢀMHzꢀ

166.6286ꢀMHzꢀ

622.080ꢀMHzꢀ

666.5143ꢀMHzꢀ

156.250ꢀMHzꢀ

InputꢀFreqꢀnotꢀlistedꢀ

OutputꢀFreqꢀnotꢀlistedꢀ

Wꢀ

ꢀ

Ordering Information

SFX-424G- X X X - X X X X

Output Frequency (Options L - A)

See standard frequencies chart above.

* If the desired frequency is not listed,

Please Consult a sales representative

for availabilty of additional frequencies.

Supply Voltage

D = 3.3 V_DC

5%

Output Logic

A = LVCMOS

F = Comp. LVPECL

Input Frequency (Options C - 3)

See standard frequencies chart above.

* If the desired frequency is not listed, Please Consult

a sales representative for availabilty of additional

frequencies.

Temperature Range

C = 0˚C to 70˚C

F = -40˚C to 85˚C

D = 0˚C to 85˚C

Input Logic

A = LVCMOS

F = LVPECL

Number of Input Frequencies

1: 1 Input Frequency

2: 2 Input Frequencies

3: 3 Input Frequencies

4: 4 Input Frequencies

Data Sheet #: SG124_SFX-424G Page 6

Rev: 05

Date: 09/11/14

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630-851-4722

Fax: 630-851-5040

www.conwin.com

Revision

P00ꢀ

P01ꢀ

P02ꢀ

P03ꢀ

P04ꢀ

P05ꢀ

00ꢀ

01ꢀ

02ꢀ

03ꢀ

04ꢀ

Revision Date Note

6/30/06ꢀ

2/6/07ꢀ

PreliminaryꢀRelease

AddedꢀSolderꢀProﬁle

3/1/07ꢀ

AddedꢀMechanicalꢀDrawing

6/7/07ꢀ

UpdatedꢀSolderꢀProﬁle

1/22/08ꢀ

9/19/08ꢀ

12/09/08ꢀ

06/17/09ꢀ

04/06/11ꢀ

05/10/11ꢀ

09/02/14ꢀ

09/11/14ꢀ

UpdatedꢀOutputꢀFrequencyꢀRange

AddedꢀInputꢀFrequencyꢀRangeꢀtoꢀTbl.ꢀ2

ChangeꢀfromꢀPreliminaryꢀtoꢀRelease

JitterꢀChange

StandardꢀFrequencyꢀUpdatesꢀ&ꢀTempꢀRangeꢀ&ꢀSolderꢀProﬁleꢀupdate

Addedꢀphaseꢀnoiseꢀexampleꢀspecꢀ&ꢀeditedꢀPackageꢀDimensions

StandardꢀFrequencyꢀUpdates

05ꢀ

UpdatedꢀPackageꢀandꢀFootprintꢀDrawings


型号：	SFX-424G
厂家：	CONNOR-WINFIELD CORPORATION
描述：	Synchronous Clock Generators
文件：	总7页 (文件大小：354K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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