656L3003C3T [CTS]

LVDS Output Clock Oscillator;


型号：	656L3003C3T
厂家：	CTS
描述：	LVDS Output Clock Oscillator 机械输出元件振荡器
文件：	总7页 (文件大小：1226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Features

. Ceramic Surface Mount Package

. Low Phase Jitter Performance, 600fs Typical

. Advanced PLL Design w/ Low Fundamental Crystal

. Frequency Range 10MHz – 1.0GHz *

. +2.5V or +3.3V Operation

Part Dimensions:

7.0 × 5.0 × 2.0mm • 178.462mg

. Output Enable Standard

. Tape and Reel Packaging, EIA‐418

Standard Frequencies

‐ 20.00MHz

‐ 161.1328MHz

‐ 200.00MHz

‐ 204.80MHz

‐ 250.00MHz

‐ 312.50MHz

‐ 622.08MHz

‐ 693.4830MHz

‐ 983.04MHz

‐ 25.00MHz

‐ 27.00MHz

‐ 122.88MHz

‐ 125.00MHz

‐ 148.351648MHz

‐ 155.52MHz

‐ 156.253906MHz

Applications

. Broadcast Video

. Storage Area Networking

. Broadband Access

. PCI Express

. Networking Equipment

. Ethernet/GbE/SyncE

. Fiber Channel

. Test and Measurement

* Check with factory for availability.

Description

CTS Model 656P/L is a low cost, high performance PLL clock oscillator supporting differential LVPECL or LVDS

outputs. Employing the latest IC technology, M656P/L has excellent stability and low phase jitter performance.

Ordering Information

Output

Type

Frequency

Stability

Temperature

Supply

Voltage

Frequency Code

[MHz]

Packaging

Model

Range

656

XXX or XXXX

Frequency

Temp. Range

‐20°C to +70°C

‐40°C to +85°C

Packing

1k pcs./reel

Code

Product Frequency Code ¹

Output

LVPECL

LVDS

Stability

Voltage

+2.5Vdc

+3.3Vdc

Code

±20ppm ²

±25ppm

±50ppm

Notes:

1] Refer to document 016‐1454‐0, Frequency Code Tables.

3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater.

Consult factory for availability of 6I Stability/Temperature combination.

Not all performance combinations and frequencies may be available.

Contact your local CTS Representative or CTS Customer Service for availability.

DOC# 008‐0342‐0 Rev. B

Page 1 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Electrical Specifications

Operating Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

‐0.5

TYP

‐

MAX

5.0

UNIT

Maximum Supply Voltage

V_CC

‐

2.375

3.135

2.5

3.3

2.625

3.465

Supply Voltage

V_CC

±5%

Supply Current

LVPECL

I_CC

Maximum Load

‐

LVDS

‐

‐20

‐40

‐55

+70

+85

+125

Operating Temperature

Storage Temperature

T_A

‐

+25

°C

T_STG

‐

Frequency Stability

PARAMETER

SYMBOL

f_O

CONDITIONS

MIN

TYP

MAX

UNIT

MHz

10 ‐ 1000

Frequency Range

‐

Frequency Stability

Δf/f_O

‐

20, 25 or 50

±ppm

ppm

[Note 1]

Aging

Δf/f₂₅

First Year @ +25°C, nominal V_CC

‐3

‐

1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st yearaging.

Output Parameters

PARAMETER

Output Type

Output Load

SYMBOL

‐

CONDITIONS

MIN

TYP

MAX

UNIT

‐

LVPECL

‐

R_L

Terminated to V_CC‐ 2.0V

‐

Ohms

V_OH

V_CC‐ 1.03

‐

V_CC‐ 0.60

V_CC‐ 1.60

Output Voltage Levels

PECL Load

V_OL

V_CC‐ 1.85

‐

Output Duty Cycle

Rise and Fall Time

SYM

T_R, T_F

@ V_CC‐ 1.3V

@ 20%/80% Levels, R_L= 50 Ohms

‐

0.25

0.60

LVDS

100

1.43

1.10

‐

Output Type

Output Load

‐

R_L

Between Outputs

‐

Ohms

V_OH

V_OL

‐

1.60

‐

Output Voltage Levels

LVDS Load

0.90

175

1.20

‐

Output Duty Cycle

Differential Output Voltage

Offset Voltage

SYM

V_OD

V_OS

T_R, T_F

@ 1.25V

R_L= 100 Ohms

350

1.25

‐

454

1.30

0.4

LVDS Load

Rise and Fall Time

@ 20%/80% Levels, R_L= 100 Ohms

DOC# 008‐0342‐0 Rev. B

Page 2 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Electrical Specifications

Output Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Start Up Time

T_S

Application of V_CC

‐

Enable Function [Standby]

Enable Input Voltage

Disable Input Voltage

Disable Current

V_IH

V_IL

Pin 1 Logic '1', Output Enabled

Pin 1 Logic '0', Output Disabled

Pin 1 Logic '1', Output Enabled

Bandwidth 12 kHz ‐ 20 MHz

‐

0.7V_CC

‐

0.3V_CC

I_IL

‐

Enable Time

T_PLZ

‐

Phase Jitter, RMS

Period Jitter, pk‐pk

Period Jitter, RMS

tjrms

pjpk‐pk

pjrms

600

2.5

<1000

‐

Enable Truth Table

Pin 1

Logic ‘1’

Open

Pin 4 & Pin 5

Output

Logic ‘0’

High Imp.

Test Circuit

LVPECL

LVDS

Output Waveform

LVPECL or LVDS

DOC# 008‐0342‐0 Rev. B

Page 3 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Electrical Specifications

Performance Data

Phase Noise [typical]

100.00MHz, LVPECL, V_CC= 3.3V, T_A= +25°C

156.25MHz, LVPECL, V_CC= 3.3V, T_A= +25°C

312.50MHz, LVPECL, V_CC= 3.3V, T_A= +25°C

800.00MHz, LVPECL, V_CC= 3.3V, T_A= +25°C

DOC# 008‐0342‐0 Rev. B

Page 4 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Electrical Specifications

Performance Data

Phase Noise Tabulated

Typical, HCMOS, V_CC= 3.3V, T_A= +25°C

PARAMETER

SYMBOL

CONDITIONS

TYP

UNIT

PARAMETER

SYMBOL

CONDITIONS

TYP

UNIT

LVPECL @ 100.00MHz

Phase Noise

LVPECL @ 156.25MHz

Phase Noise

Single Side Band

@ 10Hz

‐69.70

‐92.90

@ 10Hz

‐88.60

‐97.80

@ 100Hz

@ 1kHz

@ 100Hz

@ 1kHz

‐115.90

‐126.80

‐129.50

‐143.50

‐154.90

‐155.30

‐111.40

‐121.00

‐127.00

‐141.80

‐151.50

‐153.30

‐

dBc/Hz

‐

dBc/Hz

@ 10kHz

@ 100kHz

@ 1MHz

@ 10MHz

@ 40MHz

@ 10kHz

@ 100kHz

@ 1MHz

@ 10MHz

@ 40MHz

Phase Jitter, RMS

tjrms

Integration Bandwidth 12kHz ‐ 20MHz 714.35

Phase Jitter, RMS

tjrms

Integration Bandwidth 12kHz ‐ 20MHz 869.93

PARAMETER

SYMBOL

CONDITIONS

TYP

UNIT

PARAMETER

SYMBOL

CONDITIONS

TYP

UNIT

LVPECL @ 312.50MHz

Phase Noise

LVPECL @ 800.00MHz

Phase Noise

Single Side Band

@ 10Hz

‐81.30

‐91.80

@ 10Hz

‐85.00

‐90.90

@ 100Hz

@ 1kHz

@ 100Hz

@ 1kHz

‐105.30

‐115.50

‐120.80

‐136.40

‐153.20

‐96.90

‐

dBc/Hz

‐

dBc/Hz

@ 10kHz

@ 100kHz

@ 1MHz

@ 10MHz

@ 40MHz

@ 10kHz

@ 100kHz

@ 1MHz

@ 10MHz

@ 40MHz

‐106.70

‐107.50

‐125.90

‐145.40

‐150.40

Phase Jitter, RMS

tjrms

Integration Bandwidth 12kHz ‐ 20MHz 496.03

Phase Jitter, RMS

tjrms

Integration Bandwidth 12kHz ‐ 20MHz 781.63

DOC# 008‐0342‐0 Rev. B

Page 5 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Mechanical Specifications

Package Drawing

Marking Information

1. ** ‐ Manufacturing Site Code.

2. YYWW – Date Code; YY – year, WW – week.

3. O – Output Type; P = LVPECL, L = LVDS.

4. ST – Frequency Stability/Temperature Code.

[Refer to Ordering Information]

5. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.

6. xxxx – Frequency Code.

CTS**YYWW

656OSTV

● xxxx

3‐digits, frequencies below 100MHz

4‐digits, frequencies 100MHz or greater

[See document 016‐1454‐0, Frequency Code Tables.]

Recommended Pad Layout

Notes

1. JEDEC termination code (e4). Barrier‐plating is

nickel [Ni] with gold [Au] flash plate.

2. Reflow conditions per JEDEC J‐STD‐020; +260°C

maximum, 20 seconds.

3. MSL = 1.

Pin Assignments

Symbol

Function

Enable

EOH

N.C.

No Connect

GND

Circuit & Package Ground

RF Output

Output

V_CC

Complimentary RF Output

Supply Voltage

DOC# 008‐0342‐0 Rev. B

Page 6 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

Model 656P/L

Advanced PLL LVPECL or LVDS Clock

Packaging ‐ Tape and Reel

Tape Drawing

Reel Drawing

Notes

1. Device quantity is 1k pieces maximum per 180mm reel.

2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.

DOC# 008‐0342‐0 Rev. B

Page 7 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

相关型号：