BCM20732A0KML2G_技术文档

CYW20732A0

Single-Chip

Bluetooth Low-Energy Only SoC

The Cypress CYW20732A0 is a Bluetooth Low-Energy (BLE)-only SoC. The CYW20732A0 radio has been designed to provide low

power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed Industrial, Scien-

tific, and Medical (ISM) band.

The single-chip BLE SoC is a monolithic component implemented in a standard digital CMOS process and requires minimal external

components to make a fully compliant Bluetooth device. The CYW20732A0 is available in a 32-pin, 5 mm × 5 mm 32-QFN package.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM20732

CYW20732

BCM20732A0KML2G

CYW20732A0KML2G

Features

Applications

■ Bluetooth Low-Energy (BLE)-compliant

■ Infrared modulator

The following profiles are supported in ROM:

■ Battery status

■ Blood pressure monitor

■ Find me

■ IR learning

■ Supports Adaptive Frequency Hopping

■ Excellent receiver sensitivity

■ 10-bit auxiliary ADC with nine analog channels

■ Heart rate monitor

■ Proximity

■ On-chip support for serial peripheral interface (master and

slave modes)

■ Thermometer

■ Weight scale

■ Time

■ Cypress CypressSerial Control (BSC) interface (compatible

with NXP I²C slaves)

Additional profiles that can be supported from RAM

include:

■ Programmable output power control

■ Integrated ARM Cortex-M3 based microprocessor core

■ On-chip power-on reset (POR)

■ Blood glucose monitor

■ Temperature alarm

■ Location

■ Support for EEPROM and serial flash interfaces

■ Integrated Low DropOut (LDO) regulator

■ On-chip, software controlled power management unit

■ 32-pin 32-QFN (5 mm × 5 mm) package

■ RoHS compliant

Full qualification and use of these profiles may require firmware

updates from Cypress. Some profiles are under development/

approval at Bluetooth SIG and conformity with the final approved

version is pending. Contact your supplier for updates and the

latest list of profiles.

Cypress Semiconductor Corporation

Document Number: 002-14837 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 2, 2016

CYW20732A0

Figure 1. Functional Block Diagram

Muxed on GPIO

Tx RTS_N

1.2V

UART_TXD

UART_RXD

SDA/

SCL/

Rx

CTS_N

VDD_CORE

1.2V

SCK

MOSI

MISO

1.2V VDD_CORE

Domain

WDT

28 ADC

Inputs

VSS,

VDDO,

VDDC

BSC/SPI

Master

Interface

(BSC is I²C -

compaƟble)

1.2V

POR

Test

UART

Periph 320K

UART ROM

Processing

Unit

(ARM -CM3)

60K

RAM

CT ɇ ѐ

ADC

1.2V

LDO

1.425V to 3.6V

1.62V to 3.6V

3.6V

System Bus

MIA POR

32 kHz

LPCLK

Peripheral

Interface

Block

I/O Ring

Control

Registers

Volt. Trans

hclk

VDD_IO

Domain

(24 MHz to 1 MHz)

RF Control

and Data

I/O Ring Bus

Bluetooth

2.4 GHz

Radio

Baseband

Core

GPIO

Control/

Status

IR

Mod.

and

SPI

PMU

24

MHz

M/S

Learning

Registers

Power

RF I/O

T/R

Switch

Frequency

Synthesizer

32 kHz

LPCLK

WAKE

128 kHz

LPO

High Current

Driver Controls

IR

I/O

14 GPIOs

AutoCal

128 kHz

LPCLK

1.2V VDD_RF

Domain

9 ADC

Inputs

÷ 4

PWM

24 MHz

Ref Xtal

32 kHzꢀyƚĂůꢀ;ŽƉƟŽŶĂůͿꢀ

1.62V to 3.6V

VDD_IO

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website

(http://community.cypress.com/).

Document Number: 002-14837 Rev. *L

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CYW20732A0

Contents

1. Functional Description .................................................4

1.1 Bluetooth Baseband Core .....................................4

1.2 Infrared Modulator .................................................5

1.3 Infrared Learning ...................................................5

1.4 ADC Port ...............................................................6

1.5 Serial Peripheral Interface .....................................6

1.6 Microprocessor Unit ..............................................7

1.7 Integrated Radio Transceiver ................................8

1.8 Peripheral Transport Unit ......................................9

1.9 Clock Frequencies ...............................................10

1.10 GPIO Port ..........................................................12

1.11 PWM ..................................................................12

1.12 Power Management Unit ...................................13

2. Pin Assignments ........................................................15

2.1 Pin Descriptions ..................................................15

2.2 Ball Maps .............................................................19

3. Specifications .............................................................20

3.1 Electrical Characteristics .....................................20

3.2 RF Specifications ................................................23

3.3 Timing and AC Characteristics ............................24

3.4 ESD Test Models ................................................27

4. Mechanical Information .............................................29

5. Ordering Information ..................................................31

A. Appendix: Acronyms and Abbreviations ................32

Document History ..........................................................33

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CYW20732A0

1. Functional Description

1.1 Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high performance Bluetooth operation.

The BBC manages the buffering, segmentation, and data routing for all connections. It also buffers data that passes through it, handles

data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into

baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it

independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase TX/RX data reliability and security

before sending over the air:

■ Receive Functions: symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data dewhitening.

■ Transmit Functions: data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and

data whitening.

1.1.1 Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,

Bluetooth clock, and device address.

1.1.2 E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide

minimal processor intervention.

1.1.3 Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU).

This layer consists of the Command Controller, which takes software commands, and other controllers that are activated or configured

by the Command Controller to perform the link control tasks. Each task performs a different Bluetooth link controller state. STANDBY

and CONNECTION are the two major states. In addition, there are five substates: page, page scan, inquiry, and inquiry scan.

1.1.4 Adaptive Frequency Hopping

The CYW20732 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map

selection. The link quality is determined by using both RF and baseband signal processing to provide a more accurate frequency hop

map.

1.1.5 Bluetooth Low Energy Profiles

The CYW20732 supports Bluetooth low-energy, including the following profiles that are supported¹in ROM:

■ Battery status

■ Blood pressure monitor

■ Find me

■ Heart rate monitor

■ Proximity

■ Thermometer

■ Weight scale

■ Time

The following additional profiles can be supported¹from RAM:

■ Blood glucose monitor

■ Temperature alarm

■ Location

■ Custom profile

1. Full qualification and use of these profiles may require firmware updates from Cypress. Some of these profiles are under development/approval at the Bluetooth SIG

and conformity with the final approved version is pending. Contact your supplier for updates and the latest list of profiles.

Document Number: 002-14837 Rev. *L

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CYW20732A0

1.1.6 Test Mode Support

The CYW20732 fully supports Bluetooth Test mode, as described in the Bluetooth low energy specification.

1.2 Infrared Modulator

The CYW20732 includes hardware support for infrared TX. The hardware can transmit both modulated and un-modulated waveforms.

For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from

firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.

If descriptors are used, they include IR on/off state and the duration between 1 and 32,767 µsec. The CYW20732 IR TX firmware

driver inserts this information in a hardware FIFO and makes sure that all descriptors are played out without a glitch due to under run

(see Figure 2 on page 5).

Figure 2. Infrared TX

1.3 Infrared Learning

The CYW20732 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.

For modulated signals, the CYW20732 can detect carrier frequencies between 10 kHz– 500 kHz and the duration that the signal is

present or absent. The CYW20732 firmware driver supports further analysis and compression of learned signal. The learned signal

can then be played back through the CYW20732 IR TX subsystem (see Figure 3).

Figure 3. Infrared RX

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CYW20732A0

1.4 ADC Port

The CYW20732 contains a 16-bit ADC (effective number of bits is 10).

Additionally:

■ There are nine analog input channels in the 32-pin package

■ The following GPIOs can be used as ADC inputs:

❐ P0

❐ P1

❐ P8/P33 (select only one)

❐ P11

❐ P12

❐ P13/P28 (select only one)

❐ P14/P38 (select only one)

❐ P15

❐ P32

■ The conversion time is 10 μs.

■ There is a built-in reference with supply- or bandgap-based reference modes.

■ The maximum conversion rate is 187 kHz.

■ There is a rail-to-rail input swing.

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes

the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input

multiplexers that select the ADC input signal V_inpand the ADC reference signals V_ref

.

The ADC input range is selectable by firmware control:

■ When an input range of 0–3.6V is used, the input impedance is 3 MΩ.

■ When an input range of 0–2.4V is used, the input impedance is 1.84 MΩ.

■ When an input range of 0–1.2V is used, the input impedance is 680 kΩ.

ADC modes are defined in Table 2.

Table 2. ADC Modes

Mode

ENOB (Typical)

Maximum Sampling Rate (kHz)

Latency^a(μs)

0

1

2

3

4

13

5.859

11.7

171

85

21

11

5

12.6

12

46.875

93.75

187

11.5

10

a.Settling time after switching channels.

1.5 Serial Peripheral Interface

The CYW20732 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.

Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the

CYW20732 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,

Table 4, and Table 5. The CYW20732 acts as a SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20732 can also

act as an SPI slave device that supports a 1.8V or 3.3V SPI master.

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CYW20732A0

Table 3. CYW20732 First SPI Set (Master Mode)

Pin Name

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS^a

Configured Pin Name

SCL

–

SDA

P24

P26

P32

–

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 4. CYW20732 Second SPI Set (Master Mode)

Pin Name

SPI_CLK

SPI_CS^a

Configured Pin Name

P3

–

P0

P1

P25

–

P4

P24

P27

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

Table 5. CYW20732 Second SPI Set (Slave Mode)

Pin Name

SPI_CLK

SPI_CS

Configured Pin Name

P3

–

P0

P27

P33

–

P1

–

P2

–

P24

–

P25

–

P26

P32

1.6 Microprocessor Unit

The CYW20732 microprocessor unit (µPU) executes software from the link control (LC) layer up to the application layer components.

The microprocessor is based on an ARM Cortex-M3, 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units.

The µPU has 320 KB of ROM for program storage and boot-up, 60 KB of RAM for scratch-pad data, and patch RAM code. The SoC

has a total storage of 380 KB, including RAM and ROM.

The internal boot ROM provides power-on reset flexibility, which enables the same device to be used in different HID applications with

an external serial EEPROM or with an external serial flash memory. At power-up, the lowest layer of the protocol stack is executed

from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can

also support the integration of user applications.

1.6.1 EEPROM Interface

The CYW20732 provides a Cypress Serial Control (CSC) master interface. BSC is programmed by the CPU to generate four types

of bus transfers: read-only, write-only, combined read/write, and combined write/read. BSC supports both low-speed and fast mode

devices. BSC is compatible with an NXP I²C slave device, except that master arbitration (multiple I²C masters contending for the bus)

is not supported.

The EEPROM can contain customer application configuration information including application code, configuration data, patches,

pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.

Native support for the Microchip 24LC128, Microchip 24AA128, and the STMicroelectronics M24128-BR is included.

1.6.2 Serial Flash Interface

The CYW20732 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic.

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CYW20732A0

Devices natively supported include the following:

■ Atmel AT25BCM512B

■ MXIC MX25V512ZUI-20G

1.6.3 Internal Reset

Figure 4. Internal Reset Timing

VDDO POR delay

~ 2 ms

VDDO

VDDO POR threshold

VDDO POR

VDDC POR threshold

VDDC

VDDC POR delay

~ 2 ms

VDDC POR

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal Enable

1.6.4 External Reset

The CYW20732 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external

active low reset signal, RESET_N, can be used to put the CYW20732 in the reset state. The RESET_N pin has an internal pull-up

resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after the

VDDO supply voltage level has been stabilized.

Figure 5. External Reset Timing

Pulse width

>20 µs

RESET_N

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and

firmware boot

Crystal Enable

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CYW20732A0

1.7 Integrated Radio Transceiver

The CYW20732 has an integrated radio transceiver that is optimized for 2.4 GHz Bluetooth wireless systems. It has been designed

to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed

ISM band. It is fully compliant with Bluetooth Radio Specification 4.0 and meets or exceeds the requirements to provide the highest

communication link quality of service.

1.7.1 Transmitter Path

The CYW20732 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

1.7.2 Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes

any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

1.7.3 Power Amplifier

The CYW20732 has an integrated power amplifier (PA) that can transmit up to +4 dBm for class 2 operation.

1.7.4 Receiver Path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order, on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation,

enables the CYW20732 to be used in most applications without off-chip filtering.

1.7.5 Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

1.7.6 Receiver Signal Strength Indicator

The radio portion of the CYW20732 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller

to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

1.7.7 Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The

CYW20732 uses an internal loop filter.

1.7.8 Calibration

The CYW20732 radio transceiver features a self-contained automated calibration scheme. No user interaction is required during

normal operation or during manufacturing to provide optimal performance. Calibration compensates for filter, matching network, and

amplifier gain and phase characteristics to yield radio performance within 2% of what is optimal. Calibration takes process and

temperature variations into account, and it takes place transparently during normal operation and hop setting times.

1.7.9 Internal LDO Regulator

The CYW20732 has an integrated 1.2V LDO regulator that provides power to the digital and RF circuits. The 1.2V LDO regulator

operates from a 1.425V to 3.63V input supply with a 30 mA maximum load current.

Note: Always place the decoupling capacitors near the pins as closely together as possible.

1.8 Peripheral Transport Unit

1.8.1 Cypress Serial Communications Interface

The CYW20732 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external

EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse

devices. The BSC interface is compatible with I²C slave devices. The BSC does not support multimaster capability or flexible wait-

state insertion by either master or slave devices.

The following transfer clock rates are supported by the BSC:

■ 100 kHz

■ 400 kHz

■ 800 kHz (not a standard I²C-compatible speed.)

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CYW20732A0

■ 1 MHz (Compatibility with high-speed I²C-compatible devices is not guaranteed.)

The following transfer types are supported by the BSC:

■ Read (Up to 16 bytes can be read.)

■ Write (Up to 16 bytes can be written.)

■ Read-then-Write (Up to 16 bytes can be read and up to 16 bytes can be written.)

■ Write-then-Read (Up to 16 bytes can be written and up to 16 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20732 are required on

both the SCL and SDA pins for proper operation.

1.8.2 UART Interface

The UART is a standard 2-wire interface (RX and TX) and has adjustable baud rates from 9600 bps to 115.2 Kbaud. The baud rate

can be selected via a vendor-specific UART HCI command. The interface supports the Bluetooth 3.0 UART HCI (H4) specification.

The default baud rate for H4 is 115.2 Kbaud.

Both high and low baud rates can be supported by running the UART clock at 24 MHz.

The CYW20732 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5

percent

1.9 Clock Frequencies

The CYW20732 is set with a crystal frequency of 24 MHz.

1.9.1 Crystal Oscillator

The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load

capacitors in the range of 5 pF to 30 pF (see Figure 6) are required to work with the crystal oscillator. The selection of the load

capacitors is crystal-dependent.

Figure 6. Recommended Oscillator Configuration—12 pF Load Crystal

22 pF

XIN

Crystal

XOUT

20 pF

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CYW20732A0

Table 6 shows the recommended crystal specifications.

Table 6. Reference Crystal Electrical Specifications

Parameter

Nominal frequency

Conditions

Minimum

Typical

Maximum

Unit

MHz

–

24.000

–

Oscillation mode

–

Fundamental

Frequency tolerance

Tolerance stability over temp

Equivalent series resistance

Load capacitance

@25°C

–

±10

–

ppm

Ω

@0°C to +70°C

–

60

–

12

–

pF

Operating temperature range

Storage temperature range

Drive level

0

+70

+125

200

±10

2

°C

–40

–

°C

–

μW

Aging

–

ppm/year

pF

Shunt capacitance

–

1.9.2 Peripheral Block

The CYW20732 peripheral blocks all run from a single 128 kHz low-power RC oscillator. The oscillator can be turned on at the request

of any of the peripherals. If the peripheral is not enabled, it shall not assert its clock request line.

The keyboard scanner is a special case, in that it may drop its clock request line even when enabled, and then reassert the clock

request line if a keypress is detected.

1.9.3 32 kHz Crystal Oscillator

Figure 7 shows the 32 kHz crystal (XTAL) oscillator with external components and Table 7 on page 11 lists the oscillator’s character-

istics. It is a standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The

hysteresis was added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit

can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The default

component values are: R1 = 10 MΩ, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Figure 7. 32 kHz Oscillator Block Diagram

C2

32.768 kHz

R1

XTAL

C1

Table 7. XTAL Oscillator Characteristics

Parameter

Symbol

Conditions

Minimum

Typical

32.768

Maximum

Unit

Output frequency F_oscout

–

kHz

Frequency

tolerance

–

Crystal dependent

100

ppm

Start-up time

T_startup

P_drv

–

500

–

ms

XTAL drive level

For crystal selection 0.5

μW

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CYW20732A0

Table 7. XTAL Oscillator Characteristics (Cont.)

Parameter

Symbol

Conditions

Minimum

Typical

Maximum

Unit

XTAL series resis- R_series

tance

For crystal selection

–

70

kΩ

XTAL shunt capaci- C_shunt

tance

For crystal selection

1.3

pF

1.10 GPIO Port

The CYW20732 has 14 general-purpose I/Os (GPIOs) in the 32-pin package. All GPIOs support programmable pull-up and pull-down

resistors, and all support a 2 mA drive strength except P26, P27, and P28, which provide a 16 mA drive strength at 3.3V supply.

The following GPIOs are available:

■ P0–P4

■ P8/P33 (Dual bonded, only one of two is available.)

■ P11/P27 (Dual bonded, only one of two is available.)

■ P12/P26 (Dual bonded, only one of two is available.)

■ P13/P28 (Dual bonded, only one of two is available.)

■ P14/P38 (Dual bonded, only one of two is available.)

■ P15

■ P24

■ P25

■ P32

For a description of all GPIOs, see Table 9 on page 16.

1.11 PWM

The CYW20732 has four internal PWM channels. The PWM module is described as follows:

■ PWM0–3

■ The following GPIOs can be mapped as PWMs:

❐ P26

❐ P27

❐ P14/P28 (Dual bonded, only one of two is available.)

❐ P13

■ Each of the PWM channels, PWM0–3, contains the following registers:

❐ 10-bit initial value register (read/write)

❐ 10-bit toggle register (read/write)

❐ 10-bit PWM counter value register (read)

■ The PWM configuration register is shared among PWM0–3 (read/write). The 12-bit register is used:

❐ To configure each PWM channel.

❐ To select the clock of each PWM channel.

❐ To change the phase of each PWM channel.

Figure 8 shows the structure of one PWM channel.

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CYW20732A0

Figure 8. PWM Channel Block Diagram

pwm_cfg_adr register

pwm#_init_val_adr register

10

pwm#_togg_val_adr register

10

pwm#_cntr_adr

10

cntr value is CM3 readable

pwm_out

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)

PWM cntr w/ pwm#_init_val = x (solid line)

10'H3FF

pwm_togg_val_adr

10'Hx

10'H000

pwm_out

1.12 Power Management Unit

The power management unit (PMU) provides power management features that can be invoked by software through power

management registers or packet-handling in the baseband core.

1.12.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-

ceiver, which then processes the power-down functions accordingly.

1.12.2 Host Controller Power Management

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the

disabling of the on-chip regulator when in deep sleep mode.

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CYW20732A0

1.12.3 BBC Power Management

There are several low-power operations for the BBC:

■ Physical layer packet handling turns RF on and off dynamically within packet TX and RX.

■ Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYW20732 runs on the low

power oscillator (LPO) and wakes up after a predefined time period.

The CYW20732 automatically adjusts its power dissipation based on user activity. The following power modes are supported:

■ Active mode

■ Idle mode

■ Sleep mode

■ HIDOFF (Deep Sleep) mode

The CYW20732 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered

when user activity resumes.

In HIDOFF (Deep Sleep) mode, the CYW20732 baseband and core are powered off by disabling power to LDOOUT. The VDDO

domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power

consumption and is intended for long periods of inactivity.

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CYW20732A0

2. Pin Assignments

2.1 Pin Descriptions

Table 8. Pin Descriptions

Pin Number

Radio I/O

Pin Name

I/O

Power Domain

Description

6

RF

VDD_RF

RF antenna port

RF Power Supplies

4

VDDIF

I

VDD_RF

IFPLL power supply

RF front-end supply

VCO, LOGEN supply

5

VDDFE

7

VDDVCO

VDDPLL

8

RFPLL and crystal oscillator supply

Power Supplies

11

28

14

VDDC

VDDO

VDDM

I

VDDC

VDDO

VDDM

Baseband core supply

I/O pad and core supply

I/O pad supply

Clock Generator and Crystal Interface

9

XTALI

I

VDD_RF

VDDO

Crystal oscillator input. See page 10 for options.

Crystal oscillator output.

10

1

XTALO

XTALI32K

O

I

LPO input is used. Alternative Function:

■ P11

■ P27

32

XTALO32K

O

VDDO

LPO output. Alternative Function:

■ P12

■ P26

Core

18

RESET_N

TMC

I/O PU

I

VDDO

Active-low system reset with open-drain output & internal

pull-up resistor

17

Test mode control

High: test mode

Connect to GND if not used.

UART

12

UART_RXD

UART_TXD

I

VDDM

UART serial input – Serial data input for the HCI UART

interface. Leave unconnected if not used.

Alternative function:

■ GPIO3

13

O, PU

UART serial output – Serial data output for the HCI UART

interface. Leave unconnected if not used.

Alternative Function:

■ GPIO2

BSC

Document Number: 002-14837 Rev. *L

Page 15 of 35

CYW20732A0

Table 8. Pin Descriptions (Cont.)

Pin Number Pin Name

15

I/O

Power Domain

Description

Data signal for an external I²C device.

Alternative function:

SDA

I/O, PU VDDM

■ SPI_1: MOSI (master only)

■ GPIO0

■ CTS

16

SCL

I/O, PU VDDM

Clock signal for an external I²C device.

Alternative function:

■ SPI_1: SPI_CLK (master only)

■ GPIO1

■ RTS

LDO Regulator Power Supplies

2

3

LDOIN

I

N/A

Battery input supply for the LDO

LDO output

LDOOUT

O

Table 9. GPIO Pin Descriptions^a

Default Di- After POR Power Do-

rection State main

Pin Number

19

Pin Name

P0

Alternate Function Description

Input Input VDDO

■ GPIO: P0

floating

■ A/D converter input

■ Peripheral UART: puart_tx

■ SPI_2: MOSI (master and slave)

■ IR_RX

■ 60Hz_main

■ Not available during TMC=1

■ GPIO: P1

20

P1

Input

floating

VDDO

■ A/D converter input

■ Peripheral UART: puart_rts

■ SPI_2: MISO (master and slave)

■ IR_TX

21

22

P3

P2

Input

floating

VDDO

■ GPIO: P3

■ Peripheral UART: puart_cts

■ SPI_2: SPI_CLK (master and slave)

■ GPIO: P2

Input

floating

■ Peripheral UART: puart_rx

■ SPI_2: SPI_CS (slave only)

■ SPI_2: SPI_MOSI (master only)

Document Number: 002-14837 Rev. *L

Page 16 of 35

CYW20732A0

Table 9. GPIO Pin Descriptions^a(Cont.)

Default Di- After POR Power Do-

Pin Number

23

Pin Name

P4

Alternate Function Description

■ GPIO: P4

rection State main

Input Input VDDO

floating

■ Peripheral UART: puart_rx

■ SPI_2: MOSI (master and slave)

■ IR_TX

24

P8

Input

floating

VDDO

■ GPIO: P8

■ A/D converter input

■ External T/R switch control: ~tx_pd

■ GPIO: P33

P33

Input

floating

■ A/D converter input

■ SPI_2: MOSI (slave only)

■ Auxiliary clock output: ACLK1

■ Peripheral UART: puart_rx

■ GPIO: P11

1

P11

Input

floating

VDDO

■ A/D converter input

■ XTALI32K

P27

PWM1

Input

floating

■ GPIO: P27

■ SPI_2: MOSI (master and slave)

■ Current: 16 mA

32

P12

Input

floating

VDDO

■ GPIO: P12

■ A/D converter input

■ XTALO32K

P26

PWM0

Input

floating

■ GPIO: P26

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Current: 16 mA

29

P13

PWM3

Input

floating

VDDO

■ GPIO: P13

■ A/D converter input

P28

PWM2

Input

floating

■ GPIO: P28

■ A/D converter input

■ LED1

■ IR_TX

■ Current: 16 mA

Document Number: 002-14837 Rev. *L

Page 17 of 35

CYW20732A0

Table 9. GPIO Pin Descriptions^a(Cont.)

Default Di- After POR Power Do-

Pin Number

30

Pin Name

P14

Alternate Function Description

rection State main

Input Input VDDO

■ GPIO: P14

PWM2

floating

■ A/D converter input

P38

Input

floating

VDDO

■ GPIO: P38

■ A/D converter input

■ SPI_2: MOSI (master and slave)

■ IR_TX

31

27

P15

P24

Input

floating

■ GPIO: P15

■ A/D converter input

■ IR_RX

■ 60 Hz_main

■ GPIO: P24

Input

floating

■ SPI_2: SPI_CLK (master and slave)

■ SPI_1: MISO (master only)

■ Peripheral UART: puart_tx

■ GPIO: P25

26

25

P25

P32

Input

floating

VDDO

■ SPI_2: MISO (master and slave)

■ Peripheral UART: puart_rx

■ GPIO: P32

Input

floating

■ A/D converter input

■ SPI_2: SPI_CS (slave only)

■ SPI_1: MISO (master only)

■ Auxiliary clock output: ACLK0

■ Peripheral UART: puart_tx

a. During power-on reset, all inputs are disabled.

Document Number: 002-14837 Rev. *L

Page 18 of 35

CYW20732A0

2.2 Ball Maps

Figure 9. 32-pin QFN Ball Map

32

31

30

29

28

27

26

25

P11/P27/XIN32

LDO_IN

LDO_OUT

VDDIF

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

P8/P33

P4

P2

P3

VDDFE

P1

RF

P0

VDDVCO

VDDPLL

RST_N

TMC

9

10

11

12

13

14

15

16

Document Number: 002-14837 Rev. *L

Page 19 of 35

CYW20732A0

3. Specifications

3.1 Electrical Characteristics

Table 10 shows the maximum electrical rating for voltages referenced to VDD pin.

Table 10. Maximum Electrical Rating

Rating

Symbol

Value

Unit

DC supply voltage for RF domain

DC supply voltage for core domain

DC supply voltage for VDDM domain (UART/I²C)

DC supply voltage for VDDO domain

DC supply voltage for VR3V

–

1.4

V

–

1.4

V

3.8

V

3.8

V

3.8

V

DC supply voltage for VDDFE

1.4

V

Voltage on input or output pin

VSS – 0.3 to VDD + 0.3

–30 to +85

V

Operating ambient temperature range

Storage temperature range

Topr

Tstg

°C

–40 to +125

Table 11 shows the power supply characteristics for the range T_J= 0 to 125°C.

Table 11. Power Supply

Parameter

Minimum^a

1.14

Typical

Maximum^a

1.26

Unit

DC supply voltage for RF

DC supply voltage for Core

1.2

–

V

1.14

1.62

1.425

1.14

1.26

3.63

1.26

DC supply voltage for VDDM (UART/I²C)

DC supply voltage for VDDO

–

DC supply voltage for LDOIN

–

DC supply voltage for VDDFE

1.2^b

a. Overall performance degrades beyond minimum and maximum supply voltages.

b. 1.2V for Class 2 output with internal VREG.

Document Number: 002-14837 Rev. *L

Page 20 of 35

CYW20732A0

Table 12 shows the digital level characteristics for (VSS = 0V).

Table 12. LDO Regulator Electrical Specifications

Parameter

Input voltage range

Default output voltage

Output voltage

Conditions

Min.

1.425

Typ.

Max.

3.63

Unit

–

V

–

1.2

–

V

Range

Step size

0.8

–

1.4

–

V

40 or 80

mV

%

Accuracy at any step

–5

–

+5

30

0.2

Load current

–

mA

Line regulation

Load regulation

Vin from 1.425 to 3.63V, I_load= 30 mA

–0.2

–

%V_O/V

I

_loadfrom 1 µA to 30 mA, Vin = 3.3V, Bonding R –

0.1

%V_O/mA

= 0.3Ω

Quiescent current

No load @Vin = 3.3V

*Current limit enabled

–

6

5

–

µA

nA

Power-down current

Vin = 3.3V, worst@70°C

200

Table 13 shows the specifications for the ADC characteristics.

Table 13. ADC Specifications

Parameter

Number of Input channels

Channel switching rate

Input signal range

Reference settling time

Input resistance

Symbol

Conditions

Min.

Typ.

Max.

Unit

–

9

–

f_ch

V_inp

–

133.33

kch/s

V

0

–

3.63

Changing refsel

7.5

–

s

R_inp

C_inp

f_C

Effective, single ended

–

500

–

k

pF

kHz

s

Input capacitance

Conversion rate

–

5

–

5.859

5.35

–

187

170.7

–

Conversion time

T_C

R

–

Resolution

–

16

bits

–

Effective number of bits

–

In specified performance range

–

See Table 2

on page 6

–

Absolutevoltagemeasurement –

error

Using on-chip ADC firmware driver

–

±2

–

%

Current

I

I_avdd1p2+ I_avdd3p3

–

1

mA

Power

P

–

1.5

–

mW

nA

Leakage current

Power-up time

Integral nonlinearity³

Differential nonlinearity^a

I_leakage

T_powerup

INL

T = 25°C

–

100

200

1

–

µs

In guaranteed performance range

–1

–

LSB^a

DNL

–

1

a. LSBs are expressed at the 10-bit level.

Table 14 shows the specifications for the digital voltage levels.

Document Number: 002-14837 Rev. *L

Page 21 of 35

CYW20732A0

Table 14. Digital Levels^a

Characteristics

Symbol

Min

Typ

Max

0.4

Unit

Input low voltage

V_IL

V_IH

V_IL

V_IH

–

V

Input high voltage

0.75 × VDDO

–

V

Input low voltage (VDDO = 1.62V)

Input high voltage (VDDO = 1.62V)

Output low voltage^b

–

0.4

–

V

1.2

V

V_OL

V_OH

C_IN

–

0.4

–

V

Output high voltage^b

VDDO – 0.4

–

V

Input capacitance (VDDMEM domain)

0.12

–

pF

a. This table is also applicable to VDDMEM domain.

b. At the specified drive current for the pad.

Table 15 shows the specifications for current consumption.

Table 15. Current Consumption ^a

Operational Mode

Receive

Conditions

Min

Typ

Max

Unit

mA

Receiver and baseband are both operating, 100% ON.

–

9.8

–

Transmit

Sleep

Transmitter and baseband are both operating, 100% ON.

9.1

–

mA

Internal LPO is in use.

–

12.0

0.65

μA

a. Currents measured between power terminals (Vdd) using 90% efficient DC-DC converter at 3V.

Document Number: 002-14837 Rev. *L

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CYW20732A0

3.2 RF Specifications

Table 16. Receiver RF Specifications

Parameter

Receiver Section^a

Mode and Conditions

Min

2402

Typ

Max

2480

Unit

MHz

Frequency range

–

RX sensitivity (standard)

RX sensitivity (low current)

Input IP3

0.1%BER, 1Mbps, dirty transmitter OFF

–

–93

–90

–

dBm

–

–16

–10

Maximum input

–

Interference Performance^a,b

C/I cochannel

0.1%BER

–

21

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I 3 MHz adjacent channel

C/I image channel

15

–17

–27

–9.0

–15

C/I 1 MHz adjacent to image channel

Out-of-Band Blocking Performance (CW)^a,b

30 MHz to 2000 MHz

2003 MHz to 2399 MHz

2484 MHz to 2997 MHz

3000 MHz to 12.75 GHz

Spurious Emissions

30 MHz to 1 GHz

0.1%BER^c

–

–30.0

–35

–

dBm

0.1%BER^d

0.1%BER^e

–35

–30.0

–

–57.0

–55.0

dBm

1 GHz to 12.75 GHz

a.30.8% PER.

b.Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm).

c. Measurement resolution is 10 MHz.

d. Measurement resolution is 3 MHz.

e. Measurement resolution is 25 MHz.

Document Number: 002-14837 Rev. *L

Page 23 of 35

CYW20732A0

Table 17. Transmitter RF Specifications

Parameter

Transmitter Section

Frequency range

Minimum

2402

Typical

Maximum

Unit

MHz

–

2480

Output power adjustment range

Default output power

Output power variation

Adjacent Channel Power

|M – N| = 2

–20

–

4

–

dBm

dB

4.0

2.0

–

–20

–30

dBm

|M – N| 3

Out-of-Band Spurious Emission

30 MHz to 1 GHz

–

–36.0

–30.0

–47.0

dBm

1 GHz to 12.75 GHz

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

LO Performance

Initial carrier frequency tolerance

Frequency Drift

–

±150

kHz

Frequency drift

–

±50

20

kHz

Drift rate

kHz/50 µs

Frequency Deviation

Average deviation in payload

(sequence used is 00001111)

225

185

–

2

275

–

kHz

MHz

Maximum deviation in payload

(sequence used is 10101010)

Channel spacing

–

3.3 Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

3.3.1 UART Timing

Table 18. UART Timing Specifications

Reference

Characteristics

Min

Max

24

Unit

Baud out cycles

ns

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

Setup time, UART_CTS_N high before midpoint of stop bit

Delay time, midpoint of stop bit to UART_RTS_N high

–

10

2

Baud out cycles

Document Number: 002-14837 Rev. *L

Page 24 of 35

CYW20732A0

Figure 10. UART Timing

3.3.2 SPI Timing

The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz when 2.2V > VDDIO

≥ 1.62V.

Table 19. SPI Interface Timing Specifications

Reference

Characteristics

Time from CSN asserted to first clock edge

Master setup time

Min

1 SCK

Typ

Max

1

2

3

4

5

6

100

∞

–

½ SCK

–

Master hold time

½ SCK

–

Slave setup time

½ SCK

–

Slave hold time

½ SCK

1 SCK

–

Time from last clock edge to CSN deasserted

10 SCK

100

Figure 11 and Figure 12 on page 26 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3,

respectively.

Document Number: 002-14837 Rev. *L

Page 25 of 35

CYW20732A0

Figure 11. SPI Timing – Mode 0 and 2

6

SPI_CSN

SPI_CLK

1

(Mode 0)

SPI_CLK

(Mode 2)

2

3

‐

First Bit

Second Bit

Last bit

‐

SPI_MOSI

SPI_MISO

4

5

First Bit

Not Driven

Second Bit

Not Driven

Figure 12. SPI Timing – Mode 1 and 3

6

SPI_CSN

SPI_CLK

1

(Mode 1)

SPI_CLK

(Mode 3)

2

3

‐

Invalid bit

‐

First bit

Last bit

SPI_MOSI

SPI_MISO

4

5

Not Driven

First bit

3.3.3 BSC Interface Timing

Table 20. BSC Interface Timing Specifications

Reference

Characteristics

Min

Max

100

Unit

kHz

1

Clock frequency

–

400

800

1000

–

2

3

4

5

6

START condition setup time

START condition hold time

Clock low time

650

280

650

280

0

ns

–

Clock high time

Data input hold time^a

–

Document Number: 002-14837 Rev. *L

Page 26 of 35

CYW20732A0

Table 20. BSC Interface Timing Specifications

Reference

Characteristics

Min

100

Max

Unit

7

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time^b

–

ns

8

280

–

9

400

–

10

650

a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START

or STOP conditions.

b. Time that the cbus must be free before a new transaction can start.

Figure 13. BSC Interface Timing Diagram

Document Number: 002-14837 Rev. *L

Page 27 of 35

CYW20732A0

3.4 ESD Test Models

ESD can have serious detrimental effects on all semiconductor ICs and the system that contains them. Standards are developed to

enhance the quality and reliability of ICs by ensuring all devices employed have undergone proper ESD design and testing, thereby

minimizing the detrimental effects of ESD. Three major test methods are widely used in the industry today to describe uniform methods

for assessing ESD immunity at Component level, Human Body Model (HBM), Machine Model (MM), and Charged Device Model

(CDM). The following standards were used to test this device:

3.4.1 Human-Body Model (HBM) – ANSI/ESDA/JEDEC JS-001-2012

The HBM has been developed to simulate the action of a human body discharging an accumulated static charge through a device to

ground, and employs a series RC network consisting of a 100 pF capacitor and a 1500ꢀ (Ohm) resistor. Both positive and negative

polarities are used for this test. Although, a 100 ms delay is allowable per specification, the minimum delay used for testing was set

to 300 ms between each pulse.

3.4.2 Machine Model (MM) – JEDEC JESD22-A115C

The MM has been developed to simulate the rapid discharge from a charged conductive object, such as a metallic tool or fixture. The

most common application would be rapid discharge from charged board assembly or the charged cables of automated testers. This

model consists of a 200 pF capacitor discharged directly into a component with no series resistor (0ꢀ). One positive and one negative

polarity pulses are applied. The minimum delay between pulses is 500 ms.

3.4.3 Charged-Device Model (CDM) - JEDEC JESD22-C101E

CDM simulates charging/discharging events that occur in production equipment and processes. The potential for a CDM ESD events

occurs when there is metal-to-metal contact in manufacturing. CDM addresses the possibility that a charge may reside on the lead

frame or package (e.g., from shipping) and discharge through a pin that subsequently is grounded, causing damage to sensitive

devices in the path. Discharge current is limited only by the parasitic impedance and capacitance of the device. CDM testing consists

of charging package to a specified voltage, then discharging the voltage through relevant package leads. One positive and one

negative polarity pulse is applied. The minimum delay between pulses is 200 ms.

3.4.4 Results Summary

ESD Test Voltage Level Results:

■ HBM +/– 2KV PASS

■ CDM +/– 500V PASS

■ MM +/– 150V PASS

Document Number: 002-14837 Rev. *L

Page 28 of 35

CYW20732A0

4. Mechanical Information

Figure 14. 32-Pin 5x5 mm QFN Package

Document Number: 002-14837 Rev. *L

Page 29 of 35

CYW20732A0

Table 21 provides dimensions and additional details on the 32-pin 5x5 mm QFN package.

Table 21. 32-pin 5x5 mm QFN Package Dimensions (Footprint: 0.80)

S/N

SYM

Dimension

Comments/Specifications

1

2

A

0.900 ±0.100

Overall Height

General tolerance:

Distance:

Angle:

±0.100

A1

0.020 ±TBD

Standoff

Matte finish on package body surface, except ejection and pin 1

marking.

Ra 0.3 ~ 1.2 μm

3

4

5

6

D

E

L

5.000 ±0.100

0.400 ±0.075

0.203 Ref.

Package Length

Frame base metal thickness

0.203 base

Package Width

All molded body sharp corner radii; unless otherwise specified.

R0.200 (maximum)

Foot Length

Drawing does not include plastic or metal protrusion of cutting burr.

T

Frame Thickness

Compliant to JEDEC standard: MO-220.

Lead Width

7

8

b

e

0.250 ±0.050

0.500 Base

Lead Pitch

4.0.1 Tape Reel and Packaging Specifications

Table 22. CYW20732 5 × 5 × 1 mm QFN, 32-Pin Tape Reel Specifications

Parameter

Value

Quantity per reel

Reel diameter

Hub diameter

Tape width

2500 pieces

13 inches

7 inches

12 mm

Tape pitch

8 mm

The top left corner of the CYW20732 package is situated near the sprocket holes, as shown in Figure 15.

Figure 15. Pin 1 Orientation

Pin 1: Top left corner of package toward sprocket holes

Document Number: 002-14837 Rev. *L

Page 30 of 35

CYW20732A0

5. Ordering Information

Table 23. Ordering Information

Part Number

Package

Ambient Operating Temperature

–30°C to +85°C

CYW20732A0KML2G

32-pin QFN

Document Number: 002-14837 Rev. *L

Page 31 of 35

CYW20732A0

A. Appendix: Acronyms and Abbreviations

The following list of acronyms and abbreviations may appear in this document.

Term

Description

ADC

AFH

AHB

APB

APU

analog-to-digital converter

adaptive frequency hopping

advanced high-performance bus

advanced peripheral bus

audio processing unit

Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable

Cypress Serial Control

Bluetooth controller

ARM7TDMI-S

CSC

BTC

COEX

DFU

DMA

EBI

coexistence

device firmware update

direct memory access

external bus interface

Host Control Interface

high voltage

HCI

HV

IDC

initial digital calibration

intermediate frequency

interrupt request

IF

IRQ

JTAG

LCU

LDO

LHL

Joint Test Action Group

link control unit

low drop-out

lean high land

LPO

LV

low power oscillator

LogicVision

MIA

multiple interface agent

pulse code modulation

phase locked loop

PCM

PLL

PMU

POR

PWM

QD

power management unit

power-on reset

pulse width modulation

quadrature decoder

RAM

RF

random access memory

radio frequency

ROM

RX/TX

SPI

read-only memory

receive, transmit

serial peripheral interface

software

SW

UART

UPI

universal asynchronous receiver/transmitter

µ-processor interface

watchdog

WD

Document Number: 002-14837 Rev. *L

Page 32 of 35

CYW20732A0

Document History

Document Title: CYW20732A0 Single-Chip Bluetooth Low-Energy Only SoC

Document Number: 002-14837

Revision

ECN

Orig. of Change Submission Date

Description of Change

20732-DS100-R:

Initial release

**

-

6/27/2011

20732-DS101-R:

Updated:

• Document title changed.

• “Bluetooth Low Energy Features” on page 1.

• Table 8: “GPIO Pin Descriptions,” on page 16.

• Table 15: “Receiver RF Specifications,” on page 23.

• Table 16: “Transmitter RF Specifications,” on page 24.

• “SPI Timing” on page 25.

*A

-

2/24/2012

20732-DS102-R:

Updated:

*B

*C

*D

-

9/17/2012

7/10/2013

• ‘Preliminary Data Sheet’ to ‘Data Sheet’.

• ‘HIDOFF mode’ to ‘HIDOFF (Deep Sleep) mode’.

20732-DS103-R:

Updated:

• “Bluetooth Low Energy Features” on page 1.

• “Microprocessor Unit” on page 07.

• Table 9: “Maximum Electrical Rating,” on page 20

• Table 21: “Ordering Information,” on page 31.

20732-DS104-R:

Updated:

-

9/17/2013

• Table 14: “Current Consumption,” on page 22: RX/Tx maximum

current values.

20732-DS105-R:

*E

*F

-

10/03/2013

12/12/2013

Updated:

• Table 14: “Current Consumption,” on page 22.

20732-DS106-R:

Updated:

• Table 16: “Transmitter RF Specifications,” on page 24

20732-DS107-R:

Updated:

• Figure 14: “32-Pin 5x5 mm QFN Package,” on page 30

Added:

*G

-

3/26/2014

• Table 20: “32-pin 5x5 mm QFN Package Dimensions (Footprint:

0.80),” on page 30

20732-DS108-R:

Updated:

• “UART Interface” on page 10.

*H

*I

-

06/05/2014

11/24/2014

20732-DS109-R:

Updated:

• Table 5: “Reference Crystal Electrical Specifications,” on page10

20732-DS110-R:

*J

-

04/21/2015

Updated:

• Table15:“Receiver RF Specifications,” on page23

Document Number: 002-14837 Rev. *L

Page 33 of 35

CYW20732A0

Document Title: CYW20732A0 Single-Chip Bluetooth Low-Energy Only SoC

Document Number: 002-14837

20732-DS111-R:

*K

*L

-

02/16/2016

11/02/2016

Added:

• “ESD Test Models” on page 27

Migrated to Cypress template.

5448744

UTSV

Document Number: 002-14837 Rev. *L

Page 34 of 35

CYW20732A0

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Lighting & Power Control

Memory

Technical Support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

35

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14837 Rev. *L

Revised November 2, 2016

Page 35 of 35


型号：	BCM20732A0KML2G
厂家：	CYPRESS
描述：	Bluetooth Low-Energy (BLE)-compliant
文件：	总35页 (文件大小：3015K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BCM20732A0KML2G [CYPRESS]

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