BCM43364KUBGT_技术文档

PRELIMINARY

CYW43364

Single-Chip IEEE 802.11 b/g/n MAC/

Baseband/Radio

The Cypress CYW43364 is a highly integrated single-chip solution and offers the lowest RBOM in the industry for Internet of Things

(IoT) and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio. In

addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier

(LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost

and printed circuit board area.

The WLAN host interface supports gSPI and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when operating in

4-bit mode at a 50 MHz bus frequency.

Using advanced design techniques and process technology to reduce active and idle power, the CYW43364 is designed to address

the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit

that simplifies the system power topology while maximizing battery life.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

BCM43364

CYW43364

BCM43364KUBG

BCM43364KUBGT

CYW43364KUBG

CYW43364KUBGT

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use.

For a comprehensive list of acronyms and other terms used in Cypress documents, go to http://www.cypress.com/glossary.

Figure 1. CYW43364 System Block Diagram

VDDIO

VBAT

WL_REG_ON

WLAN

Host I/F

WL_HOST_WAKE

SDIO*/SPI

2.4 GHz WLAN TX/RX

BPF

CYW43364

CLK_REQ

REF_CLK

(19.2, 26, or 37.4 MHz)

Cypress Semiconductor Corporation

Document Number: 002-14781 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised Friday, November 18, 2016

PRELIMINARY

CYW43364

Features

IEEE 802.11x Key Features

■ Single-band 2.4 GHz IEEE 802.11b/g/n.

■ Integrated ARM Cortex-M3 processor and on-chip memory for

complete WLAN subsystem functionality, minimizing the need

to wake up the applications processor for standard WLAN

functions. This allows for further minimization of power

consumption, while maintaining the ability to field-upgrade with

future features. On-chip memory includes 512 KB SRAM and

640 KB ROM.

■ Support for 2.4 GHz Cypress TurboQAM^®data rates (256-

QAM) and 20 MHz channel bandwidth.

■ Integrated iTR switch supports a single 2.4 GHz antenna.

■ Supports explicit IEEE 802.11n transmit beamforming.

■ OneDriver^™software architecture for easy migration from

existing embedded WLAN.

■ Tx and Rx low-density parity check (LDPC) support for

improved range and power efficiency.

■ Supports standard SDIO v2.0 and gSPI host interfaces.

■ Supports space-time block coding (STBC) in the receiver.

General Features

■ Support diversity antenna.

■ 4 Kbitone-time programmable (OTP) memory for storing board

parameters.

■ Supports a battery voltage range from 3.0V to 4.8V with an

internal switching regulator.

■ Can be routed on low-cost 1-x-1 PCB stack-ups.

■ Programmable dynamic power management.

■ 74-ball WLBGA package (4.87 mm × 2.87 mm, 0.4 mm pitch).

■ Security:

❐ WPA and WPA2 (Personal) support for powerful encryption

and authentication.

❐ Reference WLAN subsystem provides Wi-Fi protected setup

(WPS).

❐ AES in WLAN hardware for faster data encryption and IEEE

■ Worldwide regulatory support: Global products supported with

worldwide homologated design.

802.11i compatibility.

❐ Reference WLAN subsystem provides Cisco Compatible Ex-

tensions (CCX, CCX 2.0, CCX 3.0, CCX 4.0, CCX 5.0).

IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website

(http://community.cypress.com/).

Document Number: 002-14781 Rev. *C

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PRELIMINARY

CYW43364

Contents

1. Overview ........................................................................4

1.1 Overview ...............................................................4

1.2 Features ................................................................5

1.3 Standards Compliance ..........................................5

2. Power Supplies and Power Management ...................6

2.1 Power Supply Topology ........................................6

2.2 CYW43364 PMU Features ....................................6

2.3 WLAN Power Management ...................................9

2.4 PMU Sequencing ..................................................9

2.5 Power-Off Shutdown ...........................................10

2.6 Power-Up/Power-Down/Reset Circuits ...............10

3. Frequency References ...............................................11

3.1 Crystal Interface and Clock Generation ..............11

3.2 TCXO ..................................................................12

3.3 External 32.768 kHz Low-Power Oscillator .........13

4. WLAN System Interfaces ...........................................14

4.1 SDIO v2.0 ............................................................14

4.2 Generic SPI Mode ...............................................15

5. Wireless LAN MAC and PHY .....................................24

5.1 MAC Features .....................................................24

5.2 PHY Description ..................................................26

6. WLAN Radio Subsystem ............................................28

6.1 Receive Path .......................................................28

6.2 Transmit Path ......................................................28

6.3 Calibration ...........................................................28

7. CPU and Global Functions ........................................29

7.1 WLAN CPU and Memory Subsystem ..................29

7.2 One-Time Programmable Memory ......................29

7.3 GPIO Interface ....................................................29

7.4 External Coexistence Interface ...........................30

7.5 JTAG Interface ...................................................32

7.6 UART Interface ...................................................32

8. Pinout and Signal Descriptions ................................33

8.1 Ball Map ..............................................................33

8.2 WLBGA Ball List in Ball Number Order with

8.5 WLAN GPIO Signals and Strapping Options ......41

8.6 Chip Debug Options ............................................41

8.7 I/O States ............................................................42

9. DC Characteristics .....................................................44

9.1 Absolute Maximum Ratings .................................44

9.2 Environmental Ratings ........................................44

9.3 Electrostatic Discharge Specifications ................45

9.4 Recommended Operating Conditions and

DC Characteristics .............................................45

10. WLAN RF Specifications ..........................................47

10.1 2.4 GHz Band General RF Specifications .........47

10.2 WLAN 2.4 GHz Receiver Performance

Specifications ...................................................48

10.3 WLAN 2.4 GHz Transmitter Performance

Specifications ...................................................51

10.4 General Spurious Emissions Specifications ......52

11. Internal Regulator Electrical Specifications ..........53

11.1 Core Buck Switching Regulator .........................53

11.2 3.3V LDO (LDO3P3) .........................................54

11.3 CLDO ................................................................55

11.4 LNLDO ..............................................................56

12. System Power Consumption ...................................57

12.1 WLAN Current Consumption .............................57

13. Interface Timing and AC Characteristics ...............58

13.1 SDIO Default Mode Timing ...............................58

13.2 SDIO High-Speed Mode Timing ........................59

13.3 gSPI Signal Timing ............................................60

13.4 JTAG Timing .....................................................61

14. Power-Up Sequence and Timing .............................62

14.1 Sequencing of Reset and Regulator Control

Signals ..............................................................62

15. Package Information ................................................63

15.1 Package Thermal Characteristics .....................63

16. Mechanical Information ...........................................64

17. Ordering Information ................................................66

Document History ..........................................................67

X-Y Coordinates .................................................34

8.3 WLBGA Ball List Ordered By Ball Name .............37

8.4 Signal Descriptions ..............................................38

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PRELIMINARY

CYW43364

1. Overview

1.1 Overview

The Cypress CYW43364 provides the highest level of integration for IoT and wireless automation system, with integrated

IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes

and allows for handheld device flexibility in size, form, and function. The CYW43364 is designed to address the needs of highly mobile

devices that require minimal power consumption and reliable operation.

Figure 2 on page 4 shows the interconnection of all the major physical blocks in the CYW43364 and their associated external

interfaces, which are described in greater detail in subsequent sections.

Figure 2. CYW43364 Block Diagram

Cortex

Debug

M3

AHB

AHB to

APB Bridge

RAM

ROM

APB

Patch

InterCtrl

DMA

WD Timer

SW Timer

Bus Arb

ARM IP

GPIO

Ctrl

JTAG supported

over SDIO

SDIO or gSPI

SWREG

LDOx2

Power

Supply

Sleep CLK

XTAL

PMU

Control

SDIO

gSPI

LPO

XTAL OSC.

POR

WL_REG_ON

ARM

CM3

WDT

OTP

GPIO

UART

JTAG*

GPIO

UART

RAM

ROM

Supported over SDIO

BT-

WLAN

ECI

2.4 GHz

PA

LNA

BPF

WLAN

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PRELIMINARY

CYW43364

1.2 Features

The CYW43364 supports the following WLAN features:

■ IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch

■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality

■ WLAN host interface options:

❐ SDIO v2.0, including default and high-speed timing.

❐ gSPI—up to a 50 MHz clock rate

1.3 Standards Compliance

The CYW43364 supports the following standards:

■ IEEE 802.11n—Handheld Device Class (Section 11)

■ IEEE 802.11b

■ IEEE 802.11g

■ IEEE 802.11d

■ IEEE 802.11h

■ IEEE 802.11i

The CYW43364 will support the following future drafts/standards:

■ IEEE 802.11r — Fast Roaming (between APs)

■ IEEE 802.11k — Resource Management

■ IEEE 802.11w — Secure Management Frames

■ IEEE 802.11 Extensions:

■ IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported)

■ IEEE 802.11i MAC Enhancements

■ IEEE 802.11r Fast Roaming Support

■ IEEE 802.11k Radio Resource Measurement

The CYW43364 supports the following security features and proprietary protocols:

■ Security:

❐ WEP

❐ WPA Personal

❐ WPA2 Personal

❐ WMM

❐ WMM-PS (U-APSD)

❐ WMM-SA

❐ WAPI

❐ AES (Hardware Accelerator)

❐ TKIP (host-computed)

❐ CKIP (SW Support)

■ Proprietary Protocols:

❐ CCXv2

❐ CCXv3

❐ CCXv4

❐ CCXv5

■ IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements.

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PRELIMINARY

CYW43364

2. Power Supplies and Power Management

2.1 Power Supply Topology

One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43364. All regulators

are programmable via the PMU to simplify the power supply.

A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided

by the regulators in the CYW43364.

The WL_REG_ON control signal is used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK

CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when WL_REG_ON

is deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband.

The CYW43364 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO

regulators. When in this state, LPLDO1 provides the CYW43364 with all required voltage, further reducing leakage currents.

Notes:

VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device.

VDDIO should be connected to the SYS_VDDIO and WCC_VDDIO pins of the device.

2.2 CYW43364 PMU Features

The PMU supports the following:

■ VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator

■ VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3

■ 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO

■ 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep

■ Additional internal LDOs (not externally accessible)

■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode.

Figure 3 on page 7 and Figure 4 on page 8 show the typical power topology of the CYW43364.

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PRELIMINARY

CYW43364

2.3 WLAN Power Management

The CYW43364 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the

chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current

and supply voltages. Additionally, the CYW43364 integrated RAM is a high volatile memory with dynamic clock control. The dominant

supply current consumed by the RAM is leakage current only. Additionally, the CYW43364 includes an advanced WLAN power

management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43364 into various

power management states appropriate to the operating environment and the activities that are being performed. The power

management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required

resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up

sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer

are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for

the current mode. Slower clock speeds are used wherever possible.

The CYW43364 WLAN power states are described as follows:

■ Active mode: All WLAN blocks in the CYW43364 are powered up and fully functional with active carrier sensing and frame

transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock

speeds are dynamically adjusted by the PMU sequencer.

■ Doze mode: The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43364 remains

powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The

32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake

up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current.

■ Deep-sleep mode: Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states

in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To

avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-

up event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers.

■ Power-down mode: The CYW43364 is effectively powered off by shutting down all internal regulators. The chip is brought out of

this mode by external logic re-enabling the internal regulators.

2.4 PMU Sequencing

The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a

computation of required resources and a table that describes the relationship between resources and the time required to enable and

disable them.

Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin

register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of

resources required to produce the requested clocks.

Each resource is in one of the following four states:

■ enabled

■ disabled

■ transition_on

■ transition_off

The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on

or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements

on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If

the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that

the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either

the immediate transition or the timer load-decrement sequence.

During each clock cycle, the PMU sequencer performs the following actions:

■ Computes the required resource set based on requests and the resource dependency table.

■ Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource

and inverts the ResourceState bit.

■ Compares the request with the current resource status and determines which resources must be enabled or disabled.

■ Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.

■ Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.

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PRELIMINARY

CYW43364

2.5 Power-Off Shutdown

The CYW43364 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices

in the system, remain operational. When the CYW43364 is not needed in the system, VDDIO_RF and VDDC are shut down while

VDDIO remains powered. This allows the CYW43364 to be effectively off while keeping the I/O pins powered so that they do not draw

extra current from any other devices connected to the I/O.

During a low-power shutdown state, provided VDDIO remains applied to the CYW43364, all outputs are tristated, and most input

signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths

or create loading on any digital signals in the system, and enables the CYW43364 to be fully integrated in an embedded device and

to take full advantage of the lowest power-savings modes.

When the CYW43364 is powered on from this state, it is the same as a normal power-up, and the device does not retain any

information about its state from before it was powered down.

2.6 Power-Up/Power-Down/Reset Circuits

The CYW43364 has two signals (see Table 2) that enable or disable the WLAN circuits and the internal regulator blocks, allowing the

host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 14.:

“Power-Up Sequence and Timing,” on page 62.

Table 2. Power-Up/Power-Down/Reset Control Signals

Signal

Description

This signal is used by the PMU to power-up the WLAN section. When this pin is high, the regulators are enabled

and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. This pin has an

internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming.

WL_REG_ON

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PRELIMINARY

CYW43364

3. Frequency References

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency

reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to

differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.

3.1 Crystal Interface and Clock Generation

The CYW43364 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator,

including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration.

Figure 5. Recommended Oscillator Configuration

C

WLRF_XTAL_XOP

12 – 27 pF

C

WLRF_XTAL_XON

R

12 – 27 pF

Note: Resistor value determined by crystal

drive level. See reference schematics for

details.

The CYW43364 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate

using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced

directly to the CYW43364.

The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal

interface are shown in Table 3 on page 12.

Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require

support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.

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PRELIMINARY

CYW43364

3.2 TCXO

As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase

noise requirements listed in Table 3 on page 12.

If the TCXO is dedicated to driving the CYW43364, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor

with value ranges from 200 pF to 1000 pF as shown in Figure 6.

Figure 6. Recommended Circuit to Use with an External Dedicated TCXO

200 pF – 1000 pF

TCXO

WLRF_XTAL_XOP

WLRF_XTAL_XON

NC

Table 3. Crystal Oscillator and External Clock Requirements and Performance

Crystal

ExternalFrequencyRefer-

ence

Parameter

Conditions/Notes

Units

Min. Typ.

Max.

Min.

–

Typ.

Max.

Frequency

–

37.4^a

–

7

MHz

pF

Ω

Crystal load capacitance

ESR

–

12

–

60

–

Resistive

–

10k

–

100k

–

Ω

Input Impedance

(WLRF_XTAL_XOP)

Capacitive

–

pF

WLRF_XTAL_XOP input

voltage

AC-coupled analog signal

–

400^b

–

1260

0.2

mV_p-p

V

WLRF_XTAL_XOP input

low level

DC-coupled digital signal

0

WLRF_XTAL_XOP input

high level

DC-coupled digital signal

–

1.0

–20

1.26

20

V

Frequency tolerance

Initial + over temperature

–20

20

ppm

Duty cycle

37.4 MHz clock

–

40

–

50

–

60

%

Phase Noise^{c, d, e}

(IEEE 802.11 b/g)

37.4 MHz clock at 10 kHz offset

37.4 MHz clock at 100 kHz offset

37.4 MHz clock at 10 kHz offset

37.4 MHz clock at 100 kHz offset

37.4 MHz clock at 10 kHz offset

37.4 MHz clock at 100 kHz offset

–129

–136

–134

–141

–140

–147

dBc/Hz

–

Phase Noise^{c, d, e}

(IEEE 802.11n, 2.4 GHz)

–

Phase Noise^{c, d, e}

(256-QAM)

–

a. The frequency step size is approximately 80 Hz. The CYW43364 does not auto-detect the reference clock frequency; the frequency is specified in the software

and/or NVRAM file.

b. To use 256-QAM, a 800 mV minimum voltage is required.

c. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.

d. Phase noise is assumed flat above 100 kHz.

e. The CYW43364 supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table.

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PRELIMINARY

CYW43364

3.3 External 32.768 kHz Low-Power Oscillator

The CYW43364 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an

external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,

voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a

small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.

Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table

4 on page 13.

Note: The CYW43364 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it

doesn't sense a clock, it will use its own internal LPO.

■ To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating.

■ To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK.

Table 4. External 32.768 kHz Sleep-Clock Specifications

Parameter

Nominal input frequency

LPO Clock

Units

kHz

ppm

%

32.768

±200

Frequency accuracy

Duty cycle

30–70

Input signal amplitude

Signal type

200–3300

mV, p-p

–

Square wave or sine wave

>100

<5

kΩ

Input impedance^a

Clock jitter

pF

<10,000

ppm

a. When power is applied or switched off.

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CYW43364

4. WLAN System Interfaces

4.1 SDIO v2.0

The CYW43364 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high speed

4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal

notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within

the WLAN chip is also provided.

SDIO mode is enabled using the strapping option pins. See Table 11 on page 41 for details.

Three functions are supported:

■ Function 0 standard SDIO function. The maximum block size is 32 bytes.

■ Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes.

■ Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes.

4.1.1 SDIO Pin Descriptions

Table 5. SDIO Pin Descriptions

SD 4-Bit Mode

SD 1-Bit Mode

gSPI Mode

DATA0

DATA1

DATA2

DATA3

CLK

Data line 0

DATA

IRQ

NC

Data line

Interrupt

DO

IRQ

NC

Data output

Interrupt

Data line 1 or Interrupt

Data line 2

Not used

Clock

Not used

Card select

Clock

Data line 3

NC

CS

Clock

CLK

CMD

SCLK

DI

CMD

Command line

Data input

Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)

CLK

CMD

CYW43364

SD Host

DAT[3:0]

Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)

CLK

CMD

CYW43364

SD Host

DATA

IRQ

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PRELIMINARY

CYW43364

4.2 Generic SPI Mode

In addition to the full SDIO mode, the CYW43364 includes the option of using the simplified generic SPI (gSPI) interface/protocol.

Characteristics of the gSPI mode include:

■ Up to 50 MHz operation

■ Fixed delays for responses and data from the device

■ Alignment to host gSPI frames (16 or 32 bits)

■ Up to 2 KB frame size per transfer

■ Little-endian and big-endian configurations

■ A configurable active edge for shifting

■ Packet transfer through DMA for WLAN

The gSPI mode is enabled using the strapping option pins. See Table 11 on page 41 for details.

Figure 9. Signal Connections to SDIO Host (gSPI Mode)

SCLK

DI

DO

CYW43364

SD Host

IRQ

CS

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PRELIMINARY

CYW43364

4.2.1 SPI Protocol

The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes. Figure 10 and Figure

11 on page 17 show the basic write and write/read commands.

Figure 10. gSPI Write Protocol

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Figure 11. gSPI Read Protocol

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Command Structure

The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 12.

Figure 12. gSPI Command Structure

BCM_SPID Command Structure

27

31 30 29 28

11 10

0

C

A

F1 F0

Address – 17 bits

Packet length - 11bits *

* 11’h0 = 2048 bytes

Function No: 00 – Func 0: All SPI-specific registers

01 – Func 1: Registers and memories belonging to other blocks in the chip (64 bytes max)

10 – Func 2: DMA channel 1. WLAN packets up to 2048 bytes.

11 – Func 3: DMA channel 2 (optional). Packets up to 2048 bytes.

Access : 0 – Fixed address

1 – Incremental address

Command : 0 – Read

1 – Write

Write

The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following

bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge.

Write/Read

The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge

of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows

data to be ready for the first clock edge without relying on asynchronous delays.

Read

The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read

command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval

between the command/address is not fixed.

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Status

The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information

about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of

interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus

timing for read/write transactions with and without status notification are as shown in Figure 13 below and Figure 14 on page 20. See

Table 6 on page 20 for information on status-field details.

Figure 13. gSPI Signal Timing Without Status

Write

CS

SCLK

MOSI

CC3311 CC3300

CC11 CC00 DD3311 DD3300

DD11 DD00

Command 32 bits Write Data 16*n bits

CS

Write-Read

SCLK

MOSI

MISO

CC3311 CC3300

CC00

DD3311 DD3300

DD00

DD11

Response

Delay

Command

32 bits

Read Data 16*n bits

Read

CS

SCLK

MOSI

MISO

CC3311 CC3300

DD3311 DD3300

DD00

Command

32 bits

Response

Delay

Read Data

16*n bits

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Figure 14. gSPI Signal Timing with Status (Response Delay = 0)

CS

Write

SCLK

MOSI

CC3311

CC11 CC00 DD3311

DD11 DD00

SS3311

SS11 SS00

Status 32 bits

MISO

Command 32 bits

Write Data 16*n bits

Write-Read

CS

SCLK

MOSI

MISO

CC3311

CC00

SS3311

SS00

DD3311

DD11 DD00

Read Data 16*n bits

Status 32 bits

Command 32 bits

CS

Read

SCLK

MOSI

MISO

CC3311

CC00

SS3311

Status 32 bits

SS00

DD3311

DD11 DD00

Command 32 bits

Read Data 16*n bits

Table 6. gSPI Status Field Details

Bit

0

Name

Description

Data not available

Underflow

The requested read data is not available.

1

FIFO underflow occurred due to current (F2, F3) read command.

FIFO overflow occurred due to current (F1, F2, F3) write command.

F2 channel interrupt

2

Overflow

3

F2 interrupt

5

F2 RX ready

Reserved

F2 FIFO is ready to receive data (FIFO empty).

–

7

8

F2 packet available

F2 packet length

Packet is available/ready in F2 TX FIFO.

Length of packet available in F2 FIFO

9:19

4.2.2 gSPI Host-Device Handshake

To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN

register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43364 is ready for data transfer. The

device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for

waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to

pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the

interrupt and then take necessary actions.

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4.2.3 Boot-Up Sequence

After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read command

to F0 address 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register

content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wake-up WLAN bit (F0 reg

0x00 bit 7). Wake-up WLAN turns the PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal

frequency.

For the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. Once it is available,

the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive

interrupt is issued to the host. This indicates device awake/ready status. See Table 7 for information on gSPI registers.

In Table 7, the following notation is used for register access:

■ R: Readable from host and CPU

■ W: Writable from host

■ U: Writable from CPU

Table 7. gSPI Registers

Address

Register

Word length

Bit

Access

Default

Description

0: 16-bit word length

1: 32-bit word length

0

R/W/U

0

0: Little endian

1: Big endian

Endianess

1

4

R/W/U

0

1

0: Normal mode. Sample on SPICLK rising edge, output

on falling edge.

1: High-speed mode. Sample and output on rising edge of

SPICLK (default).

High-speed mode

x0000

0: Interrupt active polarity is low.

1: Interrupt active polarity is high (default).

Interrupt polarity

Wake-up

5

7

0

R/W/U

R/W

1

0

1

A write of 1 denotes a wake-up command from host to

device. This will be followed by an F2 interrupt from the

gSPI device to host, indicating device awake status.

0: No status sent to host after a read/write.

1: Status sent to host after a read/write.

Status enable

R/W

x0002

x0003

0: Do not interrupt if status is sent.

1: Interrupt host even if status is sent.

Interrupt with status

Reserved

1

–

0

R/W

–

0

–

0

–

Requested data not available. Cleared by writing a 1 to this

location.

R/W

1

2

5

6

7

5

6

7

R

0

F2/F3 FIFO underflow from the last read.

F2/F3 FIFO overflow from the last write.

F2 packet available

x0004

x0005

Interrupt register

F3 packet available

F1 overflow from the last write.

F1 Interrupt

F2 Interrupt

F3 Interrupt

x0006,

x0007

Interrupt enable

register

15:0

31:0

R/W/U

R

16'hE0E7

32'h0000

Particular interrupt is enabled if a corresponding bit is set.

Same as status bit definitions

x0008 to

x000B

Status register

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Table 7. gSPI Registers (Cont.)

Address

Register

Bit

0

Access

Default

Description

R

1

F1 enabled

x000C,

x000D

F1 info. register

1

0

12'h40

1

F1 ready for data transfer

F1 maximum packet size

F2 enabled

13:2

0

R/U

R

x000E,

x000F

F2 info. register

1

0

F2 ready for data transfer

F2 maximum packet size

15:2

R/U

14'h800

This register contains a predefined pattern, which the host

can read to determine if the gSPI interface is working

properly.

x0014 to Test Read-only

32'hFEEDBE

AD

31:0

R

x0017

register

This is a dummy register where the host can write some

pattern and read it back to determine if the gSPI interface

is working properly.

x0018 to

x001B

32'h0000000

0

Test R/W register

R/W/U

Individual response delays for F0, F1, F2, and F3. The

value of the registers is the number of byte delays that are

introduced before data is shifted out of the gSPI interface

during host reads.

0x1D = 4,

other

registers = 0

x001C to Response delay

x001F registers

7:0

R/W

Figure 15 on page 23 shows the WLAN boot-up sequence from power-up to firmware download, including the initial device power-on

reset (POR) evoked by the WL_REG_ON signal. After initial power-up, the WL_REG_ON signal can be held low to disable the

CYW43364 or pulsed low to induce a subsequent reset.

Note: The CYW43364 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after

VDDC and VDDIO have both passed the 0.6V threshold.

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Figure 15. WLAN Boot-Up Sequence

Ramp time from 0V to 4.3V > 40 µs

0.6V

VBAT

VDDIO

> 2 Sleep Clock cycles

WL_REG_ON

< 1.5 ms

< 3 ms

VDDC

(from internal PMU)

Internal POR

After a fixed delay following internal POR going high, the

device responds to host F0 (address 0x14) reads.

< 50 ms

Device requests a reference clock.

15 1 ms

After 15 ms¹the reference clock

is assumed to be up. Access to

PLL registers is possible.

SPI Host Interaction:

Host polls F0 (address 0x14) until it reads

a predefined pattern.

Host sets wake-up-wlan bit

and waits 15 ms¹, the

maximum time for reference

After 15 ¹ms, the host

programs the PLL registers to

set the crystal frequency.

clock availability.

Chip-active interrupt is asserted after the PLL locks.

WL_IRQ

Host downloads

code.

¹This wait time is programmable in sleep-clock increments from 1 to 255 (30 µs to 15 ms).

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5. Wireless LAN MAC and PHY

5.1 MAC Features

The CYW43364 WLAN MAC supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The

salient features are listed below:

■ Transmission and reception of aggregated MPDUs (A-MPDU).

■ Support for power management schemes, including WMM power-save, power-save multipoll (PSMP) and multiphase PSMP

operation.

■ Support for immediate ACK and Block-ACK policies.

■ Interframe space timing support, including RIFS.

■ Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges.

■ Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification.

■ Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT)

generation in hardware.

■ Hardware off-load for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management.

■ Programmable independent basic service set (IBSS) or infrastructure basic service set functionality

■ Statistics counters for MIB support.

5.1.1 MAC Description

The CYW43364 WLAN MAC is designed to support high throughput operation with low-power consumption. In addition, several

power-saving modes that have been implemented allow the MAC to consume very little power while maintaining network-wide timing

synchronization. The architecture diagram of the MAC is shown in Figure 16 on page 24.

Figure 16. WLAN MAC Architecture

Embedded CPU Interface

Host Registers, DMA Engines

TX‐FIFO

32 KB

RX‐FIFO

10 KB

PSM

PMQ

PSM

UCODE

Memory

IFS

WEP

WEP, TKIP, AES

TSF

SHM

BUS

IHR

NAV

BUS

Shared Memory

6 KB

RXE

RX A‐MPDU

TXE

TX A‐MPDU

EXT‐ IHR

MAC

‐

PHY Interface

The following sections provide an overview of the important modules in the MAC.

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PSM

The programmable state machine (PSM) is a microcoded engine that provides most of the low-level control to the hardware to

implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow-control operations, which are predom-

inant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which

allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving

IEEE 802.11 specifications.

The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data

store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratch-pad

memory (similar to a register bank) to store frequently accessed and temporary variables.

The PSM exercises fine-grained control over the hardware engines by programming internal hardware registers (IHR). These IHRs

are collocated with the hardware functions they control and are accessed by the PSM via the IHR bus.

The PSM fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal,

or a program stack. For ALU operations, the operands are obtained from shared memory, scratch-pad memory, IHRs, or instruction

literals, and the results are written into the shared memory, scratch-pad memory, or IHRs.

There are two basic branch instructions: conditional branches and ALU-based branches. To better support the many decision points

in the IEEE 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition

signals are available to the PSM without polling the IHRs) or on the results of ALU operations.

WEP

The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as

well as the MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP,

and WPA2 AES-CCMP.

Based on the frame type and association information, the PSM determines the appropriate cipher algorithm to be used. It supplies

the keys to the hardware engines from an on-chip key table. The WEP interfaces with the transmit engine (TXE) to encrypt and

compute the MIC on transmit frames and the receive engine (RXE) to decrypt and verify the MIC on receive frames. WAPI is also

supported.

TXE

The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames

in the TXFIFO. It interfaces with WEP module to encrypt frames and transfers the frames across the MAC-PHY interface at the

appropriate time determined by the channel access mechanisms.

The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic

streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule

a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a

precise timing trigger received from the IFS module.

The TXE module also contains the hardware that allows the rapid assembly of MPDUs into anA-MPDU for transmission. The hardware

module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed.

RXE

The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMAengine to drain the received frames

from the RX FIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The

decrypted data is stored in the RX FIFO.

The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria

such as receiver address, BSSID, and certain frame types.

The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate

them into component MPDUS.

IFS

The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple

back-off engines required to support prioritized access to the medium as specified by WMM.

The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers

provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform

transmit frame-bursting (RIFS or SIFS separated, as within a TXOP).

The back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or

pause the back-off counters. When the back-off counters reach 0, the TXE gets notified so that it may commence frame transmission.

In the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies

provided by the PSM.

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The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power-

saving mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized

by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer

expires, the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration, ensuring that the

TSF is synchronized to the network.

TSF

The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon trans-

mission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon

and probe response frames in order to maintain synchronization with the network.

The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink

transmission times used in PSMP.

NAV

The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration

field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard.

The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames.

This timing information is provided to the IFS module, which uses it as a virtual carrier-sense indication.

MAC-PHY Interface

The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is a programming

interface, which can be controlled either by the host or the PSM to configure and control the PHY.

5.2 PHY Description

The CYW43364 WLAN digital PHY is designed to comply with IEEE 802.11b/g/n single stream to provide wireless LAN connectivity

supporting data rates from 1 Mbps to 96 Mbps for low-power, high-performance handheld applications.

The PHY has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments.

It incorporates efficient implementations of the filters, FFT, and Viterbi decoder algorithms. Efficient algorithms have been designed

to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition

and tracking, and channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY

carrier sense has been tuned to provide high throughput for IEEE 802.11g/IEEE 802.11b hybrid networks.

5.2.1 PHY Features

■ Supports the IEEE 802.11b/g/n single-stream standards.

■ Supports explicit IEEE 802.11n transmit beamforming.

■ Supports optional Greenfield mode in TX and RX.

■ Tx and Rx LDPC for improved range and power efficiency.

■ Supports IEEE 802.11h/d for worldwide operation.

■ Algorithms achieving low power, enhanced sensitivity, range, and reliability.

■ Automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications.

■ Closed-loop transmit power control.

■ Designed to meet FCC and other regulatory requirements.

■ Support for 2.4 GHz Cypress TurboQAM data rates and 20 MHz channel bandwidth.

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Figure 17. WLAN PHY Block Diagram

CCK/DSSS

Demodulate

Filters

and

Radio

Comp

Frequency

and Timing

Synch

Descramble

and

Deframe

OFDM

Demodulate

Viterbi

Decoder

Carrier Sense,

AGC, and Rx

FSM

Buffers

Radio

Control

Block

MAC

Interface

FFT/IFFT

AFE

and

Radio

Modulation

and Coding

Tx FSM

Frame and

Scramble

Filters and

Radio Comp

Modulate/

Spread

PA Comp

COEX

The PHY is capable of fully calibrating the RF front-end to extract the highest performance. On power-up, the PHY performs a full

calibration suite to correct for IQ mismatch and local oscillator leakage. The PHY also performs periodic calibration to compensate

for any temperature related drift, thus maintaining high-performance over time. A closed-loop transmit control algorithm maintains the

output power at its required level and can control TX power on a per-packet basis.

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6. WLAN Radio Subsystem

The CYW43364 includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It

is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz

unlicensed ISM band. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Improvements

to the radio design include shared TX/RX baseband filters and high immunity to supply noise.

Figure 18 shows the radio functional block diagram.

Figure 18. Radio Functional Block Diagram

WL DAC

WL TXLPF

WL DAC

WL PA

WL PGA

WL TX G‐Mixer WL TXLPF

Voltage

Regulators

WLAN BB

WLRF_2G_RF

4 ~ 6 nH

Recommend

Q= 40

WL ADC

10 pF

WL RXLPF

WLRF_2G_eLG

SLNA

WL G‐LNA12

WL RXLPF

WL RX G‐Mixer

CLB

WL ATX

WL ARX

WL GTX

WL GRX

WL LOGEN

WL PLL

6.1 Receive Path

The CYW43364 has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure

reliable operation in the noisy 2.4 GHz ISM band.

6.2 Transmit Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable

of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA. This PAis supplied

by an internal LDO that is directly supplied by VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power

control is integrated.

6.3 Calibration

The CYW43364 features dynamic on-chip calibration, eliminating process variation across components. This enables the CYW43364

to be used in high-volume applications because calibration routines are not required during manufacturing testing. These calibration

routines are performed periodically during normal radio operation. Automatic calibration examples include baseband filter calibration

for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q calibration, R calibration,

and VCO calibration are performed on-chip.

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7. CPU and Global Functions

7.1 WLAN CPU and Memory Subsystem

The CYW43364 includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is a

low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded

applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the

Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI.

At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit

devices on MIPS/µW. It supports integrated sleep modes.

ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced

silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM Cortex-

M3 supports extensive debug features including real-time tracing of program execution.

On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM.

7.2 One-Time Programmable Memory

Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable (OTP) memory, which is

read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC

address, can be stored, depending on the specific board design.

The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0.

The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test

tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state

can be altered during each programming cycle.

Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with

the reference board design package. Documentation on the OTP development process is available on the Cypress customer support

portal (http://community.cypress.com/).

7.3 GPIO Interface

Five general-purpose I/O (GPIO) pins are available on the CYW43364 that can be used to connect to various external devices.

GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register.

They can also be programmed to have internal pull-up or pull-down resistors.

GPIO_0 is normally used as a WL_HOST_WAKE signal.

The CYW43364 supports 2-wire, 3-wire, and 4-wire coexistence configurations using GPIO_1 through GPIO_4. The signal functions

of GPIO_1 through GPIO_4 are programmable to support the three coexistence configurations.

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7.4 External Coexistence Interface

The CYW43364 supports 2-wire, 3-wire, and 4-wire coexistence interfaces to enable signaling between the device and an external

colocated wireless device in order to manage wireless medium sharing for optimal performance. The external colocated device can

be any of the following ICs: GPS, WiMAX, LTE, or UWB. An LTE IC is used in this section for illustration.

7.4.1 2-Wire Coexistence

Figure 19 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure:

■ GPIO_1: WLAN_SECI_TX output to an LTE IC.

■ GPIO_2: WLAN_SECI_RX input from an LTE IC.

Figure 19. 2-Wire Coexistence Interface to an LTE IC

WLAN_SECI_TX

GPIO_1

GPIO_2

UART_IN

WLAN_SECI_RX

UART_OUT

CYW43364

LTE/IC

Note: WLAN_SECI_OUT and WLAN_SECI_IN are multiplexed on the GPIOs.

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7.4.2 3-Wire and 4-Wire Coexistence Interfaces

Figure 20 and Figure 21 show 3-wire and 4-wire LTE coexistence examples, respectively. The following definitions apply to the GPIOs

in the figures:

■ For the 3-wire coexistence interface:

■ GPIO_2: WLAN priority output to an LTE IC.

■ GPIO_3: LTE_RX input from an LTE IC.

■ GPIO_4: LTE_TX input from an LTE IC.

For the 4-wire coexistence interface:

■ GPIO_1: WLAN priority output to an LTE IC.

■ GPIO_2: LTE frame sync input from an LTE IC. This GPIO applies only to the 4-wire coexistence interface.

■ GPIO_3: LTE_RX input from an LTE IC.

■ GPIO_4: LTE_TX input from an LTE IC.

Figure 20. 3-Wire Coexistence Interface to an LTE IC

WLAN Priority

LTE_RX

GPIO_2

GPIO_3

LTE_TX

GPIO_4

CYW43364

LTE/IC

Figure 21. 4-Wire Coexistence Interface to an LTE IC

GPIO_1

GPIO_2

GPIO_3

GPIO_4

WLAN Priority

LTE_Frame_Sync

LTE_RX

LTE_TX

CYW43364

LTE/IC

Document Number: 002-14781 Rev. *C

Page 31 of 68

PRELIMINARY

CYW43364

7.5 JTAG Interface

The CYW43364 supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB

assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug

and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by

means of test points or a header on all PCB designs.

7.6 UART Interface

One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI

pin, and UART_TX is available on the JTAG_TDO pin.

The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the

CYW43364 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It

is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction.

Document Number: 002-14781 Rev. *C

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CYW43364

8.2 WLBGA Ball List in Ball Number Order with X-Y Coordinates

Table 8 provides ball numbers and names in ball number order. The table includes the X and Y coordinates for a top view with a (0,0)

center.

Table 8. CYW43364 WLBGA Ball List — Ordered By Ball Number

Ball Number

A1

Ball Name

X Coordinate

–1200.006

–799.992

–399.996

0

Y Coordinate

2199.996

2199.978

1800

NC

A2

NC

A3

NC

A4

NC

A5

NC

399.996

799.992

1199.988

–1200.006

–799.992

–399.996

0

A6

SR_VLX

SR_PVSS

NC

A7

B1

B2

NC

1800

B3

NC

1800

B4

NC

1800

B5

NC

399.996

799.992

1199.988

–1200.006

–799.992

–399.996

0

1800

B6

PMU_AVSS

SR_VBAT5V

NC

1799.982

1399.995

1399.986

1399.995

1399.986

999.99

B7

C1

C2

C3

C4

C5

C6

C7

D2

D3

D4

D5

D6

E1

NC

SYS_VDDIO

VOUT_CLDO

LDO_VDD15V

NC

399.996

799.992

1199.988

–799.992

–399.996

0

VDDC

999.999

999.99

VSSC

NC

399.996

799.992

–1199.988

–799.992

–399.996

399.996

799.992

1199.988

–1199.988

–799.992

VOUT_LNLDO

NC

999.99

599.994

199.998

E2

VDD_1P2

VSS

E3

E5

NC

E6

GND

E7

VOUT_3P3

VDD_1P2

F1

F2

Document Number: 002-14781 Rev. *C

Page 34 of 68

PRELIMINARY

CYW43364

Table 8. CYW43364 WLBGA Ball List — Ordered By Ball Number

Ball Number

F4

Ball Name

X Coordinate

0

Y Coordinate

NC

199.998

F5

LPO_IN

399.996

800.001

1199.988

–1199.988

–799.992

0

F6

WCC_VDDIO

LDO_VBAT5V

VDD_1P2

199.998

F7

199.998

G1

G2

G4

G5

G6

H1

H2

H3

H4

H5

H6

H7

J1

–199.998

–599.994

–999.99

VSS

VDDC

NC

399.996

800.001

–1199.988

–799.992

–399.996

0

WL_REG_ON

VDDB_PA

VSS

WLRF_AFE_GND

NC

399.996

800.001

1200.006

–1199.988

–799.992

–399.996

399.996

800.001

1200.006

–1199.988

–799.992

0

GPIO_1

SDIO_DATA_1

WLRF_2G_eLG

WLRF_LNA_GND

WLRF_GPIO

VSSC

J2

–999.99

J3

–999.99

J5

–999.999

–1399.986

–1399.995

–1799.982

–1799.991

–2199.978

J6

GPIO_0

J7

SDIO_DATA_3

WLRF_2G_RF

WLRF_GENERAL_GND

GPIO_3

K1

K2

K4

K5

K6

L2

GPIO_4

399.996

800.001

–799.992

–399.996

0

SDIO_DATA_0

WLRF_PA_GND

WLRF_VCO_GND

WLRF_XTAL_GND

GPIO_2

L3

L4

L5

399.996

800.001

1200.006

–1199.988

–799.992

–399.996

0

L6

SDIO_CMD

SDIO_DATA_2

WLRF_PA_VDD

WLRF_VDD_1P35

WLRF_XTAL_VDD1P2

WLRF_XTAL_XOP

WLRF_XTAL_XON

L7

M1

M2

M3

M4

M5

399.996

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Page 35 of 68

PRELIMINARY

CYW43364

Table 8. CYW43364 WLBGA Ball List — Ordered By Ball Number

Ball Number

Ball Name

CLK_REQ

SDIO_CLK

X Coordinate

800.001

Y Coordinate

M6

M7

–2199.996

1200.006

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CYW43364

8.3 WLBGA Ball List Ordered By Ball Name

Table 9 provides the ball numbers and names in ball name order.

Table 9. CYW43364 WLBGA Ball List — Ordered By Ball Name

Ball Name

SDIO_DATA_3

Ball Number

Ball Name

CLK_REQ

Ball Number

J7

M6

E6

J6

SR_PVSS

A7

B7

A6

C5

E2

F1

F2

G1

H1

D3

G4

E7

C6

D6

E3

G2

H2

H3

D4

J5

GND

SR_VDDBAT5V

SR_VLX

GPIO_0

GPIO_1

H6

L5

SYS_VDDIO

VDD_1P2

GPIO_2

GPIO_3

K4

K5

C7

F7

F5

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

C3

C4

D2

D5

E1

E5

F4

G5

H5

B6

M7

L6

VDD_1P2

GPIO_4

VDD_1P2

LDO_VDD1P5

VDD_1P2

LDO_VDDBAT5V

VDDB_PA

LPO_IN

VDDC

NC

VDDC

NC

VOUT_3P3

NC

VOUT_CLDO

VOUT_LNLDO

VSS

NC

VSS

NC

VSS

NC

VSS

NC

VSSC

NC

VSSC

NC

WCC_VDDIO

WL_REG_ON

WLRF_2G_eLG

WLRF_2G_RF

WLRF_AFE_GND

WLRF_GENERAL_GND

WLRF_GPIO

WLRF_LNA_GND

WLRF_PA_GND

WLRF_PA_VDD

WLRF_VCO_GND

WLRF_VDD_1P35

WLRF_XTAL_GND

WLRF_XTAL_VDD1P2

WLRF_XTAL_XON

WLRF_XTAL_XOP

F6

G6

J1

NC

K1

H4

K2

J3

NC

J2

NC

L2

NC

M1

L3

NC

PMU_AVSS

SDIO_CLK

SDIO_CMD

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

M2

L4

M3

M5

M4

K6

H7

L7

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PRELIMINARY

CYW43364

8.4 Signal Descriptions

Table 10 provides the WLBGA package signal descriptions.

Table 10. WLBGA Signal Descriptions

Signal Name

RF Signal Interface

WLBGA Ball

Type

Description

WLRF_2G_RF

SDIO Bus Interface

SDIO_CLK

K1

O

2.4 GHz WLAN RF output port.

M7

L6

I

SDIO clock input.

SDIO command line.

SDIO data line 0.

SDIO data line 1.

SDIO_CMD

I/O

SDIO_DATA_0

SDIO_DATA_1

K6

H7

SDIO data line 2. Also used as a strapping option (see

Table 13 on page 42).

SDIO_DATA_2

SDIO_DATA_3

L7

J7

I/O

SDIO data line 3.

Note: Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This

requirement must be met during all operating states by using external pull-up resistors or properly programming internal SDIO host

pull-ups.

WLAN GPIO Interface

WLRF_GPIO

Clocks

J3

I/O

Test pin. Not connected in normal operation.

WLRF_XTAL_XON

WLRF_XTAL_XOP

M5

M4

O

I

XTAL oscillator output.

XTAL oscillator input.

External system clock request—Used when the

system clock is not provided by a dedicated crystal (for

example, when a shared TCXO is used). Asserted to

indicate to the host that the clock is required.

CLK_REQ

LPO_IN

M6

F5

O

I

External sleep clock input (32.768 kHz). If an external

32.768 kHz clock cannot be provided, pull this pin low.

However, BLE will be always on and cannot go to deep

sleep.

No Connect

NC_A1

NC_A2

NC_A3

NC_A4

NC_A5

NC_B1

NC_B2

NC_B3

NC_B4

NC_B5

NC_C1

NC_C2

A1

A2

A3

A4

A5

B1

B2

B3

B4

B5

C1

C2

I

No connect.

O

I/O

I

I/O

O

I/O

O

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PRELIMINARY

CYW43364

Table 10. WLBGA Signal Descriptions (Cont.)

Signal Name

WLBGA Ball

Type

O

Description

NC_C3

NC_C4

C3

C4

D2

E1

F4

G5

H5

E5

D5

No connect.

I

NC_D2

O

NC_E1

I

NC_F4

I/O

N/A

NC_G5

NC_H5

NC_E5

Not used. Do not connect to this pin.

NC_D5

Miscellaneous

Used by PMU to power up or power down the internal

regulators used by the WLAN section. Also, when

deasserted, this pin holds the WLAN section in reset.

This pin has an internal 200 kΩ pull-down resistor that

is enabled by default. It can be disabled through

programming.

WL_REG_ON

G6

I

GND_E6

GPIO_0

E6

J6

I

Tie pin E6 to ground.

Programmable GPIO pins. This pin becomes an

output pin when it is used as WLAN_HOST_WAKE/

out-of-band signal.

I/O

GPIO_1

GPIO_2

GPIO_3

GPIO_4

H6

L5

K4

K5

I/O

Programmable GPIO pins.

Connect to an external inductor. See the reference

schematic for details.

WLRF_2G_eLG

J1

I

Integrated Voltage Regulators

SR_VDDBAT5V

B7

A6

I

SR VBAT input power supply.

CBUCK switching regulator output. See Table 22 on

page 53 for details of the inductor and capacitor

required on this output.

SR_VLX

O

LDO_VDDBAT5V

LDO_VDD1P5

VOUT_LNLDO

VOUT_CLDO

VDDB_PA

F7

C7

D6

C6

H1

G1

F2

F1

E2

I

LDO VBAT.

LNLDO input.

O

I

Output of low-noise LNLDO.

Output of core LDO.

Connect to VOUT_3P3.

Connect to VOUT_LNLDO.

Connect pin E2 to VOUT_LNLDO.

VDD_1P2

I

VDD_1P2

I

VDD_1P2

I

VDD_1P2

I

Power Supplies

WLRF_XTAL_VDD1P2

WLRF_PA_VDD

WCC_VDDIO

M3

M1

F6

I

XTAL oscillator supply.

Power amplifier supply.

VDDIO input supply. Connect to VDDIO.

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CYW43364

Table 10. WLBGA Signal Descriptions (Cont.)

Signal Name

SYS_VDDIO

WLBGA Ball

C5

Type

Description

I

VDDIO input supply. Connect to VDDIO.

LNLDO input supply.

WLRF_VDD_1P35

VDDC

M2

D3, G4

Core supply for WLAN.

3.3V output supply. See the reference schematic for

details.

VOUT_3P3

E7

O

Ground

VSS_H2

H2

G2

H3

E3

I

Connect to ground.

Quiet ground.

VSS_G2

VSS_H3

VSS_E3

PMU_AVSS

B6

SR_PVSS

A7

Switcher-power ground.

Core ground for WLAN.

AFE ground.

VSSC

D4, J5

H4

J2

WLRF_AFE_GND

WLRF_LNA_GND

WLRF_GENERAL_GND

WLRF_PA_GND

WLRF_VCO_GND

WLRF_XTAL_GND

2.4 GHz internal LNA ground.

Miscellaneous RF ground.

2.4 GHz PA ground.

VCO/LO generator ground.

XTAL ground.

K2

L2

L3

L4

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PRELIMINARY

CYW43364

8.5 WLAN GPIO Signals and Strapping Options

The pins listed in Table 11 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few

milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative

function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor

that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using

a 10 kΩ resistor or less.

Note: Refer to the reference board schematics for more information.

Table 11. GPIO Functions and Strapping Options

Pin Name

WLBGA Pin #

Default

Function

Description

WLAN host interface

select

This pin selects the WLAN host interface mode. The

default is SDIO. For gSPI, pull this pin low.

SDIO_DATA_2

L7

1

8.6 Chip Debug Options

The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and

SDIO_CLK) I/O depending on the bootstrap state of GPIO_1 and GPIO_2.

Table 12 shows the debug options of the device.

Table 12. Chip Debug Options

JTAG_SEL

GPIO_2

GPIO_1

Function

Normal mode

SDIO I/O Pad Function

0

1

0

1

SDIO

JTAG

SDIO

JTAG over SDIO

SWD over GPIO_1/GPIO_2

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PRELIMINARY

CYW43364

9. DC Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

9.1 Absolute Maximum Ratings

Caution: The absolute maximum ratings in Table 14 indicate levels where permanent damage to the device can occur,

even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions.

Excluding VBAT, operation at the absolute maximum conditions for extended periods can adversely affect long-term

reliability of the device.

Table 14. Absolute Maximum Ratings

Rating

DC supply for VBAT and PA driver supply

DC supply voltage for digital I/O

Symbol

Value

–0.5 to +6.0^a

Unit

V

VBAT

VDDIO

–0.5 to 3.9

–0.5 to 1.575

–0.5 to 1.32

–0.5

V

DC supply voltage for RF switch I/Os

DC input supply voltage for CLDO and LNLDO

DC supply voltage for RF analog

DC supply voltage for core

Maximum undershoot voltage for I/O^b

Maximum overshoot voltage for I/O^b

Maximum junction temperature

VDDIO_RF

–

V

VDDRF

VDDC

V_undershoot

V_overshoot

T_j

V

VDDIO + 0.5

125

V

°C

a. Continuous operation at 6.0V is supported.

b. Duration not to exceed 25% of the duty cycle.

9.2 Environmental Ratings

The environmental ratings are shown in Table 15.

Table 15. Environmental Ratings

Characteristic

Ambient temperature (T_A)

Storage temperature

Value

Units

Conditions/Comments

–30 to +70°C ^a

–40 to +125°C

Less than 60

Less than 85

C

%

Operation

–

Storage

Operation

Relative humidity

%

a. Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details).

Document Number: 002-14781 Rev. *C

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CYW43364

9.3 Electrostatic Discharge Specifications

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps

to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.

Table 16. ESD Specifications

Pin Type

Symbol

Condition

ESD Rating

1250

Unit

V

ESD, Handling Reference:

NQY00083, Section 3.4, Group ESD_HAND_HBM

D9, Table B

Human Body Model Contact Discharge

per JEDEC EID/JESD22-A114

Machine Model (MM)

ESD_HAND_MM

Machine Model Contact

50

V

Charged Device Model Contact

Discharge per JEDEC EIA/JESD22-

C101

CDM

ESD_HAND_CDM

300

V

9.4 Recommended Operating Conditions and DC Characteristics

Functional operation is not guaranteed outside the limits shown in Table 17, and operation outside these limits for extended periods

can adversely affect long-term reliability of the device.

Table 17. Recommended Operating Conditions and DC Characteristics

Value

Element

Symbol

Unit

Minimum

3.0^a

Typical

–

Maximum

4.8^b

DC supply voltage for VBAT

VBAT

VDD

V

DC supply voltage for core

1.14

1.2

1.26

DC supply voltage for RF blocks in chip

VDDRF

1.14

1.2

1.26

VDDIO,

VDDIO_SD

DC supply voltage for digital I/O

1.71

–

3.63

V

DC supply voltage for RF switch I/Os

External TSSI input

VDDIO_RF

TSSI

3.13

0.15

0.4

3.3

–

3.46

0.95

0.7

V

Internal POR threshold

SDIO Interface I/O Pins

For VDDIO_SD = 1.8V:

Input high voltage

Vth_POR

–

VIH

VIL

1.27

–

V

Input low voltage

0.58

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO_SD = 3.3V:

Input high voltage

VOH

VOL

1.40

–

0.45

VIH

VIL

0.625 × VDDIO

–

V

Input low voltage

–

0.25 × VDDIO

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

Other Digital I/O Pins

For VDDIO = 1.8V:

VOH

VOL

0.75 × VDDIO

–

0.125 × VDDIO

Input high voltage

VIH

VIL

0.65 × VDDIO

–

V

Input low voltage

–

0.35 × VDDIO

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO = 3.3V:

VOH

VOL

VDDIO – 0.45

–

0.45

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CYW43364

Table 17. Recommended Operating Conditions and DC Characteristics (Cont.)

Value

Element

Symbol

Unit

Minimum

Typical

Maximum

Input high voltage

Input low voltage

VIH

VIL

2.00

–

V

–

0.80

–

Output high voltage @ 2 mA

Output low Voltage @ 2 mA

RF Switch Control Output Pins^c

For VDDIO_RF = 3.3V:

VOH

VOL

VDDIO – 0.4

–

0.40

Output high voltage @ 2 mA

Output low voltage @ 2 mA

Input capacitance

VOH

VOL

C_IN

VDDIO – 0.4

–

0.40

5

V

–

pF

a. The CYW43364 is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only for 3.2V < VBAT <

4.8V.

b. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are allowed. Voltages as

high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed.

c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

Document Number: 002-14781 Rev. *C

Page 46 of 68

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CYW43364

10. WLAN RF Specifications

The CYW43364 includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF

characteristics of the 2.4 GHz radio.

Note: Values in this data sheet are design goals and may change based on device characterization results.

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table

15 on page 44 and Table 17 on page 45. Functional operation outside these limits is not guaranteed.

Typical values apply for the following conditions:

■ VBAT = 3.6V.

■ Ambient temperature +25°C.

Figure 23. RF Port Location

Chip

Port

C2

TX

RX

Filter

Antenna

Port

10 pF

CYW43364

C1

L1

4.7 nH

10 pF

Note: All specifications apply at the chip port unless otherwise specified.

10.1 2.4 GHz Band General RF Specifications

Table 18. 2.4 GHz Band General RF Specifications

Item

TX/RX switch time

Condition

Including TX ramp down

Including TX ramp up

Minimum

Typical

Maximum

Unit

µs

–

5

2

RX/TX switch time

µs

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CYW43364

10.2 WLAN 2.4 GHz Receiver Performance Specifications

Note: Unless otherwise specified, the specifications in Table 19 are measured at the chip port (for the location of the chip port, see

Figure 23 on page 47).

Table 19. WLAN 2.4 GHz Receiver Performance Specifications

Parameter

Frequency range

Condition/Notes

Minimum

Typical

Maximum Unit

–

2400

–97.5

–93.5

–91.5

–88.5

–91.5

–90.5

–87.5

–85.5

–82.5

–80.5

–76.5

–75.5

–

2500

–

MHz

dBm

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps DSSS

11 Mbps DSSS

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–99.5

–95.5

–93.5

–90.5

–93.5

–92.5

–89.5

–87.5

–84.5

–82.5

–78.5

–77.5

–

RX sensitivity (8% PER for 1024

octet PSDU) ^a

–

RXsensitivity(10%PERfor1000

octet PSDU) at WLAN RF port ^a

–

20 MHz channel spacing for all MCS rates (Mixed mode)

256-QAM, R = 5/6

256-QAM, R = 3/4

MCS7

–67.5

–69.5

–71.5

–73.5

–74.5

–79.5

–82.5

–84.5

–86.5

–90.5

–69.5

–71.5

–73.5

–75.5

–76.5

–81.5

–84.5

–86.5

–88.5

–92.5

–

dBm

RX sensitivity

MCS6

(10% PER for 4096 octet PSDU).

Defined for default parameters:

GF, 800 ns GI.

MCS5

MCS4

MCS3

MCS2

MCS1

MCS0

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CYW43364

Table 19. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum

Typical

Maximum Unit

704–716

777–787

LTE

–

–13

–

dBm

776–794 MHz

815–830

CDMA2000

LTE

–

–13.5

–12.5

–13.5

–11.5

–12.5

–11.5

–8

–

816–824

CDMA2000

LTE

–

816–849

–

824–849

WCDMA

CDMA2000

LTE

–

824–849

–

824–849

–

824–849

GSM850

LTE

–

830–845

–

–11.5

–10

832–862

LTE

–

880–915

WCDMA

LTE

–

Blocking level for 3 dB Rx sensi-

tivity degradation (without

external filtering)

880–915

–

–12

880–915

E-GSM

WCDMA

LTE

–

–9

1710–1755

1710–1785

1850–1910

1850–1915

1920–1980

2300–2400

2500–2570

2570–2620

5G (WLAN)

–

–13

–

–14.5

–13

CDMA2000

WCDMA

LTE

–

–14.5

–12.5

–11.5

–16

GSM1800

GSM1900

CDMA2000

WCDMA

LTE

–

–13.5

–16

–

LTE

–

–17

WCDMA

CDMA2000

LTE

–

–17.5

–19.5

–44

–

Blocking level for 3 dB Rx sensi-

tivity degradation (without

external filtering)

LTE

–

LTE

–

–43

(cont.)

LTE

–

–34

WLAN

–

>–4

@ 1, 2 Mbps (8% PER, 1024 octets)

@ 5.5, 11 Mbps (8% PER, 1024 octets)

@ 6–54 Mbps (10% PER, 1000 octets)

–6

–12

–15.5

–

Maximum receive level

@ 2.4 GHz

–

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CYW43364

Table 19. WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Minimum

Typical

Maximum Unit

Adjacent channel rejection-

DSSS.

(Difference between interfering

and desired signal [25 MHz

apart] at 8% PER for 1024 octet

PSDU with desired signal level

as specified in Condition/Notes.)

11 Mbps DSSS

–70 dBm

35

–

dB

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

–79 dBm

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

–61 dBm

16

15

13

11

8

–

3

5

–

dB

Adjacent channel rejection-

OFDM.

(Difference between interfering 18 Mbps OFDM

and desired signal (25 MHz

24 Mbps OFDM

apart) at 10% PER for 1000^b

octet PSDU with desired signal 36 Mbps OFDM

4

level as specified in Condition/

Notes.)

48 Mbps OFDM

0

54 Mbps OFDM

65 Mbps OFDM

–1

–2

–3

–5

10

Range –98 dBm to –75 dBm

Range above –75 dBm

Zo = 50Ω across the dynamic range.

RCPI accuracy^c

Return loss

a. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.

b. For 65 Mbps, the size is 4096.

c. The minimum and maximum values shown have a 95% confidence level.

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CYW43364

10.3 WLAN 2.4 GHz Transmitter Performance Specifications

Note: Unless otherwise specified, the specifications in Table 19 are measured at the chip port (for the location of the chip port, see

Figure 23 on page 47).

Table 20. WLAN 2.4 GHz Transmitter Performance Specifications

Parameter

Frequency range

Condition/Notes

Minimum Typical Maximum

Unit

–

2400

–

2500

MHz

776–794 MHz

869–960 MHz

1450–1495

CDMA2000

–

–167.5

–163.5

–154.5

–152.5

–149.5

–145.5

–143.5

–140.5

–138.5

–

dBm/Hz

CDMAOne, GSM850

DAB

1570–1580 MHz

1592–1610 MHz

1710–1800

GPS

GLONASS

DSC-1800-Uplink

GSM 1800

GSM 1900

TDSCDMA,LTE

1805–1880 MHz

1850–1910 MHz

1910–1930 MHz

Transmitted power in cellular

and WLAN 5G band (at 21

dBm, 90% duty cycle, 1 Mbps

CCK).

GSM1900, CDMAOne,

WCDMA

1930–1990 MHz

–

–139

–

dBm/Hz

2010–2075 MHz

2110–2170 MHz

2305–2370

TDSCDMA

WCDMA

–

–127.5

–124.5

–104.5

–81.5

–

dBm/Hz

LTE Band 40

LTE Band 41

WLAN 5G

2370–2400

2496–2530

–94.5

2530–2560

–120.5

–121.5

–109.5

2570–2690

5000–5900

dBm/

MHz

4.8-5.0 GHz

7.2-7.5 GHz

9.6-10 GHz

2nd Harmonic

3rd Harmonic

4th Harmonic

–

–26.5

–23.5

–32.5

–

Harmonic level (at 21 dBm with

90% duty cycle, 1 Mbps CCK)

dBm/

MHz

dBm/

MHz

EVM Does Not Exceed

21

IEEE 802.11b

(DSSS/CCK)

–9 dB

–

dBm

OFDM, BPSK

OFDM, QPSK

OFDM, 16-QAM

–8 dB

20.5

–

dBm

–13 dB

–19 dB

TX power at the chip port for the

highest power level setting at

25°C, VBA = 3.6V, and spectral

mask and EVM compliance^{a, b}

OFDM, 64-QAM

(R = 3/4)

–25 dB

–27 dB

–32 dB

18

17.5

15

–

dBm

OFDM, 64-QAM

(R = 5/6)

OFDM, 256-QAM(R

= 5/6)

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CYW43364

Table 20. WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)

Parameter

TX power control

Condition/Notes

Minimum Typical Maximum

Unit

–

9

–

dB

dynamic range

Closed loop TX power variation Across full temperature and voltage range.

±1.5

dB

at highest power level setting

Carrier suppression

Gain control step

Applies across 5 to 21 dBm output power range.

–

15

–

0.25

6

–

dBc

dB

–

Return loss

Zo = 50

4

EVM degradation

–

3.5

±2

Output power variation

–

VSWR = 2:1.

ACPR-compliant power

level

–

15

–

dBm

Load pull variation for output

power, EVM, and Adjacent

Channel Power Ratio (ACPR)

EVM degradation

–

4

–

dB

Output power variation

±3

VSWR = 3:1.

ACPR-compliant power

level

–

15

–

dBm

a. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance.

b. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C.

10.4 General Spurious Emissions Specifications

Table 21. General Spurious Emissions Specifications

Parameter

Condition/Notes

Minimum

Typical

Maximum

Unit

Frequency range

–

2400

–

2500

MHz

General Spurious Emissions

30 MHz < f < 1 GHz

RBW = 100 kHz

RBW = 1 MHz

RBW = 100 kHz

RBW = 1 MHz

–

–99

–44

–68

–88

–99

–54

–88

–96

–41

–65

–85

–96

–51

–85

dBm

1 GHz < f < 12.75 GHz

1.8 GHz < f < 1.9 GHz

5.15 GHz < f < 5.3 GHz

30 MHz < f < 1 GHz

TX emissions

1 GHz < f < 12.75 GHz

1.8 GHz < f < 1.9 GHz

5.15 GHz < f < 5.3 GHz

RX/standby

emissions

Note: The specifications in this table apply at the chip port.

Document Number: 002-14781 Rev. *C

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PRELIMINARY

CYW43364

11. Internal Regulator Electrical Specifications

Note: Values in this data sheet are design goals and are subject to change based on device characterization results.

Functional operation is not guaranteed outside of the specification limits provided in this section.

11.1 Core Buck Switching Regulator

Table 22. Core Buck Switching Regulator (CBUCK) Specifications

Specification

Notes

Min.

Typ.

Max.

Units

Input supply voltage (DC)

DC voltage range inclusive of disturbances.

2.4

3.6

4.8^a

V

PWM mode switching

frequency

CCM, load > 100 mA VBAT = 3.6V.

–

4

–

MHz

PWM output current

Output current limit

–

370

–

mA

1400

Programmable, 30 mV steps.

Default = 1.35V.

Output voltage range

1.2

–4

1.35

–

1.5

4

V

PWM output voltage

DC accuracy

Includes load and line regulation.

Forced PWM mode.

%

Measure with 20 MHz bandwidth limit.

Static load, max. ripple based on VBAT = 3.6V,

Vout = 1.35V,

Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap +

Board total-ESR < 20 mΩ,

PWM ripple voltage, static

–

7

20

mVpp

C_out> 1.9 μF, ESL<200 pH

Peak efficiency at 200 mA load, inductor DCR =

200 mΩ, VBAT = 3.6V, VOUT = 1.35V

PWM mode peak efficiency

PFM mode efficiency

–

85

77

–

%

10 mA load current, inductor DCR = 200 mΩ,

VBAT = 3.6V, VOUT = 1.35V

VDDIO already ON and steady.

Time from REG_ON rising edge to CLDO reaching

1.2V

Start-up time from

power down

–

400

500

µs

0603 size, 2.2 μH ±20%,

DCR = 0.2Ω ± 25%

External inductor

–

2.2

4.7

–

µH

µF

Ceramic, X5R, 0402,

ESR <30 mΩ at 4 MHz, 4.7 μF ±20%, 10V

External output capacitor

2.0^b

10^c

For SR_VDDBATP5V pin,

ceramic, X5R, 0603,

ESR < 30 mΩ at 4 MHz, ±4.7 μF ±20%, 10V

External input capacitor

0.67^b

40

4.7

–

µF

µs

Input supply voltage ramp-up time

0 to 4.3V

a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as

high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

c. Total capacitance includes those connected at the far end of the active load.

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CYW43364

11.2 3.3V LDO (LDO3P3)

Table 23. LDO3P3 Specifications

Specification

Notes

Min.

Typ.

Max.

Units

Min. = V_o+ 0.2V = 3.5V dropout voltage

requirement must be met under maximum load

for performance specifications.

Input supply voltage, V_in

3.1

3.6

4.8^a

V

Output current

–

Default = 3.3V.

0.001

–

3.3

–

450

–

mA

V

Nominal output voltage, V_o

Dropout voltage

–

At max. load.

200

+5

mV

Output voltage DC accuracy

Quiescent current

Line regulation

Includes line/load regulation.

No load

–5

–

%

66

–

85

µA

V_infrom (V_o+ 0.2V) to 4.8V, max. load

–

3.5

0.3

mV/V

mV/mA

Load regulation

load from 1 mA to 450 mA

–

V_in≥ V_o+ 0.2V,

V_o= 3.3V, C_o= 4.7 µF,

Max. load, 100 Hz to 100 kHz

PSRR

20

–

dB

LDO turn-on time

Chip already powered up.

–

160

4.7

250

µs

Ceramic, X5R, 0402,

(ESR: 5 mΩ–240 mΩ), ± 10%, 10V

External output capacitor, C_o

1.0^b

5.64

µF

For SR_VDDBATA5V pin (shared with band

gap) Ceramic, X5R, 0402,

(ESR: 30m-200 mΩ), ± 10%, 10V.

Not needed if sharing VBAT capacitor 4.7 µF

with SR_VDDBATP5V.

External input capacitor

–

4.7

–

µF

a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as

high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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CYW43364

11.3 CLDO

Table 24. CLDO Specifications

Specification

Notes

Min.

1.3

Typ.

1.35

–

Max.

1.5

Units

V

Min. = 1.2 + 0.15V = 1.35V dropout voltage

requirement must be met under maximum load.

Input supply voltage, V_in

Output current

7

0.2

200

1.26

mA

V

Programmable in 10 mV steps.

Default = 1.2.V

Output voltage, V_o

0.95

1.2

Dropout voltage

At max. load

–

–4

–

150

+4

–

mV

%

Output voltage DC accuracy

Includes line/load regulation

No load

13

1.24

µA

mA

Quiescent current

200 mA load

–

V_infrom (V_o+ 0.15V) to 1.5V,

maximum load

Line regulation

Load regulation

–

5

mV/V

Load from 1 mA to 300 mA

Power down

–

0.02

0.05

20

3

mV/mA

µA

5

1

–

Leakage current

PSRR

Bypass mode

–

µA

@1 kHz, Vin ≥ 1.35V, C_o= 4.7 µF

20

–

dB

VDDIO up and steady. Time from the REG_ON rising

edge to the CLDO

Start-up time of PMU

–

700

µs

reaching 1.2V.

LDO turn-on time when rest of the

chip is up.

LDO turn-on time

–

140

2.2

180

–

µs

External output capacitor, C_o

Total ESR: 5 mΩ–240 mΩ

1.1^a

µF

Only use an external input capacitor

at the VDD_LDO pin if it is not supplied

from CBUCK output.

External input capacitor

–

1

2.2

µF

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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CYW43364

11.4 LNLDO

Table 25. LNLDO Specifications

Specification

Notes

Min.

Typ.

Max.

Units

Min. V_IN= V_O+ 0.15V = 1.35V

(where V_O= 1.2V) dropout voltage requirement

must be met under maximum load.

Input supply voltage, Vin

1.3

1.35

1.5

V

Output current

–

0.1

1.1

–

150

mA

V

Programmable in 25 mV steps.

Default = 1.2V

Output voltage, V_o

1.2

1.275

Dropout voltage

At maximum load

Includes line/load regulation

No load

–

–4

–

150

+4

mV

%

Output voltage DC accuracy

10

970

12

µA

Quiescent current

Line regulation

Max. load

–

990

V_infrom (V_o+ 0.15V) to 1.5V,

200 mA load

–

5

mV/V

Load from 1 mA to 200 mA:

Load regulation

Leakage current

Output noise

–

0.025

0.045

20

mV/mA

µA

V_in≥ (V_o+ 0.12V)

Power-down, junction temp. = 85°C

5

–

@30 kHz, 60–150 mA load C_o= 2.2 µF

@100 kHz, 60–150 mA load C_o= 2.2 µF

60

35

nV/ Hz

–

PSRR

@1 kHz, V_in≥ (V_o+ 0.15V), C_o= 4.7 µF

20

–

dB

µs

LDO turn-on time

LDO turn-on time when rest of chip is up

140

180

Total ESR (trace/capacitor):

5 mΩ–240 mΩ

External output capacitor, C_o

0.5^a

2.2

4.7

µF

Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from CBUCK

output.

External input capacitor

–

1

2.2

µF

Total ESR (trace/capacitor): 30 mΩ–200 mΩ

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging.

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PRELIMINARY

CYW43364

12. System Power Consumption

Note:

The values in this data sheet are design goals and are subject to change based on device characterization.Unless otherwise stated, these

values apply for the conditions specified in Table 17 on page 45.

12.1 WLAN Current Consumption

Table 26 shows typical currents consumed by the CYW43364’s WLAN section.

12.1.1 2.4 GHz Mode

Table 26. 2.4 GHz Mode WLAN Power Consumption

VBAT = 3.6V, VDDIO = 1.8V, TA 25°C

Mode

Rate

VBAT (mA)

Vio (µA)

Sleep Modes

Leakage (OFF)

Sleep (idle, unassociated) ^a

N/A

0.0035

0.0058

1.05

0.08

80

N/A

Sleep (idle, associated, inter-beacons) ^b

IEEE Power Save PM1 DTIM1 (Avg.) ^c

IEEE Power Save PM1 DTIM3 (Avg.) ^d

IEEE Power Save PM2 DTIM1 (Avg.) ^c

IEEE Power Save PM2 DTIM3 (Avg.) ^d

Active Modes

Rate 1

80

74

0.35

86

1.05

74

0.35

86

Rx Listen Mode ^e

N/A

37

39

12

15

Rate 1

Rate 11

Rate 54

40

Rx Active (at –50dBm RSSI) ^f

40

Rate MCS7

41

Rate 1 @ 20 dBm

Rate 11 @ 18 dBm

Rate 54 @ 15 dBm

Rate C7 @ 15 dBm

320

290

260

Tx ^f

a. Device is initialized in Sleep mode, but not associated.

b. Device is associated, and then enters Power Save mode (idle between beacons).

c. Beacon interval = 100 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).

d. Beacon interval = 300 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon).

e. Carrier sense (CCA) when no carrier present.

f. Tx output power is measured on the chip-out side; duty cycle =100%. Tx Active mode is measured in Packet Engine mode (pseudo-random data)

Document Number: 002-14781 Rev. *C

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CYW43364

13. Interface Timing and AC Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table

15 on page 44 and Table 17 on page 45. Functional operation outside of these limits is not guaranteed.

13.1 SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 24 and Table 27 on page 59.

Figure 24. SDIO Bus Timing (Default Mode)

f_PP

t_WL

t_WH

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

(max)

(min)

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CYW43364

Table 27. SDIO Bus Timing ^aParameters (Default Mode)

Parameter

SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)

Symbol

Minimum

Typical

Maximum

Unit

Frequency—Data Transfer mode

Frequency—Identification mode

Clock low time

fPP

fOD

0

–

25

400

–

MHz

kHz

ns

tWL

tWH

tTLH

tTHL

10

–

Clock high time

–

ns

Clock rise time

10

ns

Clock fall time

–

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

tISU

tIH

5

–

ns

Input hold time

Outputs: CMD, DAT (referenced to CLK)

Output delay time—Data Transfer mode

Output delay time—Identification mode

tODLY

0

–

14

50

ns

a. Timing is based on CL  40 pF load on command and data.

b. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

13.2 SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 25 and Table 28.

Figure 25. SDIO Bus Timing (High-Speed Mode)

f_PP

t_WL

t_WH

50% VDD

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

t_OH

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CYW43364

Table 28. SDIO Bus Timing ^aParameters (High-Speed Mode)

Parameter Symbol

SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)

Minimum

Typical

Maximum

Unit

Frequency – Data Transfer Mode

Frequency – Identification Mode

Clock low time

fPP

fOD

0

7

–

50

400

–

MHz

kHz

ns

tWL

tWH

tTLH

tTHL

Clock high time

–

ns

Clock rise time

3

ns

Clock fall time

3

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

tISU

tIH

6

2

–

ns

Input hold time

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer Mode

Output hold time

tODLY

tOH

–

2.5

–

14

–

ns

pF

Total system capacitance (each line)

CL

40

a. Timing is based on CL  40 pF load on command and data.

b. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.

13.3 gSPI Signal Timing

The gSPI device always samples data on the rising edge of the clock.

Figure 26. gSPI Timing

T1

T2

T4

T5

T3

SPI_CLK

SPI_DIN

T6

T7

T8

T9

SPI_DOUT

(falling edge)

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CYW43364

Table 29. gSPI Timing Parameters

Parameter Symbol

Clock period

Minimum

Maximum

Units

ns

Note

= 50 MHz

T1

20.8

–

(0.55 × T1) – T4

2.5

F

–

max

Clock high/low

T2/T3

T4/T5

(0.45 × T1) – T4

–

ns

Clock rise/fall time

ns

Setup time, SIMO valid to SPI_CLK

active edge

Input setup time

Input hold time

T6

T7

T8

T9

5.0

–

ns

Hold time, SPI_CLK active edge to

SIMO invalid

Setup time, SOMI valid before

SPI_CLK rising

Output setup time

Output hold time

Hold time, SPI_CLK active edge to

SOMI invalid

a

CSX to clock

–

7.86

–

ns

CSX fall to 1st rising edge

c

Clock to CSX

Last falling edge to CSX high

a. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (that is, overall words for multiple word transaction).

13.4 JTAG Timing

Table 30. JTAG Timing Characteristics

Output

Maximum

Output

Minimum

Signal Name

Period

Setup

Hold

TCK

TDI

125 ns

–

20 ns

–

0 ns

–

TMS

TDO

–

100 ns

–

0 ns

–

JTAG_TRST

250 ns

–

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CYW43364

14. Power-Up Sequence and Timing

14.1 Sequencing of Reset and Regulator Control Signals

The CYW43364 WL_REG_ON signal allows the host to control power consumption by enabling or disabling the WLAN and internal

regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals

for various operational states (see Figure 27 and Figure 28). The timing values indicated are minimum required values; longer delays

are also acceptable.

Note:

■ The CYW43364 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC

and VDDIO have both passed the POR threshold (see Table 17 on page 45). Wait at least 150 ms after VDDC and VDDIO are

available before initiating SDIO accesses.

■ VBAT and VDDIO should not rise faster than 40 µs. VBAT should be up before or at the same time as VDDIO. VDDIO should not

be present first or be held high before VBAT is high.

14.1.1 Control Signal Timing Diagrams

Figure 27. WLAN = ON

32.678 kHz

Sleep Clock

VBAT

90% of VH

VDDIO

~ 2 Sleep cycles

WL_REG_ON

Figure 28. WLAN = OFF

32.678 kHz

Sleep Clock

VBAT

VDDIO

WL_REG_ON

Document Number: 002-14781 Rev. *C

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CYW43364

15. Package Information

15.1 Package Thermal Characteristics

Table 31. Package Thermal Characteristics^a

Characteristic

Value in Still Air

_JA(°C/W)

_JB(°C/W)

_JC(°C/W)

53.11

13.14

6.36

0.04

14.21

125



(°C/W)

JT



(°C/W)

JB

b

Maximum Junction Temperature T (°C)

j

Maximum Power Dissipation (W)

1.2

a. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W continuous

dissipation.

b. Absolute junction temperature limits maintained through active thermal monitoring and dynamic TX duty cycle limiting.

15.1.1 Junction Temperature Estimation and PSI Versus Theta_jc

Package thermal characterization parameter PSI-JT ( ) yields a better estimation of actual junction temperature (T ) versus using

JT

J

the junction-to-case thermal resistance parameter Theta-J (_JC). The reason for this is _JCassumes that all the power is dissipated

C

through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of

the package.  takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating

JT

the device junction temperature is as follows:

T_J= T_T+ P _JT

Where:

■ T = junction temperature at steady-state condition, °C

J

■ T = package case top center temperature at steady-state condition, °C

T

■ P = device power dissipation, Watts

■  = package thermal characteristics (no airflow), °C/W

JT

Document Number: 002-14781 Rev. *C

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PRELIMINARY

CYW43364

16. Mechanical Information

Figure 29 shows the mechanical drawing for the CYW43364 WLBGA package.

Figure 29. 74-Ball WLBGA Mechanical Information

Document Number: 002-14781 Rev. *C

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PRELIMINARY

CYW43364

Figure 30. WLBGA Package Keep-Out Areas—Top View with the Bumps Facing Down

Document Number: 002-14781 Rev. *C

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PRELIMINARY

CYW43364

17. Ordering Information

Operating Ambi-

ent Temperature

Part Number ^a

Package

Description

74-ball WLBGA halogen-free package

(4.87 mm x 2.87 mm, 0.40 pitch)

2.4 GHz single-band WLAN

IEEE 802.11n

CYW43364KUBG

–30°C to +70°C

a. Add a “T” to the end of the part number to specify “Tape and Reel.”

Document Number: 002-14781 Rev. *C

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PRELIMINARY

CYW43364

Document History

Document Title: CYW43364 Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio

Document Number: 002-14781

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

43364-DS100-R

Initial release

**

–

12/08/14

43364-DS101-R

Updated:

■ Figure 3: “Typical Power Topology (1 of 2),” on page 14.

■ Figure 4: “Typical Power Topology (2 of 2),” on page 15.

■ Figure 22: “74-Ball WLBGA Ball Map (Bottom View),” on page 44.

■ Table 7: “BCM43364 WLBGA Ball List — Ordered By Ball Number,” on page 45.

■ Table 8: “BCM43364 WLBGA Ball List — Ordered By Ball Name,” on page 48.

■ Table 9: “WLBGA Signal Descriptions,” on page 49.

*A

–

08/06/15

■ Table 12: “I/O States,” on page 53.

■ Table 18: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 59.

■ Table 19: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 62.

■ Table 25: “2.4 GHz Mode WLAN Power Consumption,” on page 70.

43364-DS102-R

Updated:

*B

*C

–

10/05/15

11/18/16

■ Table 10, “WLBGA Signal Descriptions,” on page 38

■ Table 13, “I/O States,” on page 42

Updated to Cypress format

5525641

UTSV

Document Number: 002-14781 Rev. *C

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CYW43364

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

®

ARM Cortex Microcontrollers

Automotive

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Lighting & Power Control

Memory

Technical Support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

68

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-14781 Rev. *C

Revised November 18, 2016

Page 68 of 68


型号：	BCM43364KUBGT
厂家：	CYPRESS
描述：	Single-band 2.4 GHz IEEE 802.11b/g/n
文件：	总68页 (文件大小：5794K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BCM43364KUBGT [CYPRESS]

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