BCM4354KKWBGT_技术文档

The following document contains information on Cypress products. Although the document is marked with the name

“Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to

new and existing customers.

CONTINUITY OF SPECIFICATIONS

There is no change to this document as a result of offering the device as a Cypress product. Any changes that have

been made are the result of normal document improvements and are noted in the document history page, where

supported. Future revisions will occur when appropriate, and changes will be noted in a document history page.

CONTINUITY OF ORDERING PART NUMBERS

Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part

Numbers listed in this document.

FOR MORE INFORMATION

Please visit our website at www.cypress.com or contact your local sales office for additional information about

Cypress products and services.

OUR CUSTOMERS

Cypress is for true innovators – in companies both large and small.

Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that

revolutionize their industries or create new industries with products and solutions that nobody ever thought of before.

ABOUT CYPRESS

Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative

automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress’s

programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity

solutions and reliable, high-performance memories help engineers design differentiated products and get them to

market first.

Cypress is committed to providing customers with the best support and engineering resources on the planet enabling

innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn

more, go to www.cypress.com.

Cypress Semiconductor Corporation

Document Number: 002-14809 Rev. *I

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Revised July 1, 2016

DataSheet

BCM4354

Single-Chip 5G Wi-Fi IEEE 802.11ac 2×2 MAC/

Baseband/Radio with Integrated Bluetooth 4.1

and FM Receiver

GENERAL DESCRIPTION

The Broadcom^®BCM4354 is a complete dual–band

The BCM4354 uses advanced design techniques and

process technology to reduce active and idle power,

and includes an embedded power management unit

that simplifies the system power topology.

(2.4 GHz and 5 GHz) 5G Wi–Fi 2 × 2 MIMO^®MAC/

PHY/Radio System–on–a–Chip. This Wi–Fi single–

chip device provides a high level of integration with

dual–stream IEEE 802.11ac MAC/baseband/radio,

Bluetooth 4.1, and FM radio receiver. In IEEE

802.11ac mode, the WLAN operation supports rates

of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz,

and 80 MHz channels for data rates up to 867 Mbps.

In addition, all the rates specified in IEEE 802.11a/b/

g/n are supported. Included on–chip are 2.4 GHz and

5 GHz transmit power amplifiers and receive low

noise amplifiers.

In addition, the BCM4354 implements highly

sophisticated enhanced collaborative coexistence

hardware mechanisms and algorithms that ensure

that WLAN and Bluetooth collaboration is optimized

for maximum performance. Coexistence support for

external radios (such as LTE cellular and GPS) is

provided via an external interface. As a result,

enhanced overall quality for simultaneous voice,

video, and data transmission on a handheld system is

achieved.

For the WLAN section, several alternative host

interface options are included: an SDIO v3.0 interface

that can operate in 4b or 1b modes, a high-speed

inter-chip (HSIC) interface, and a PCIe v3.0 compliant

interface running at Gen1 speeds. For the Bluetooth

section, host interface options of a high-speed 4-wire

UART and USB 2.0 full-speed (12 Mbps) are

provided.

Figure 1: Functional Block Diagram

VIO

VBAT

WL_REG_ON

WLAN

Host I/F

PCIe

SDIO

HSIC

T/R Switch

5G WLAN

2G WLAN

5G WLAN

Ant1

Ant0

Diplexer

External

Coexistence I/F

COEX

CLK_REQ

BT_REG_ON

UART

BCM4354

USB 2.0

2G WLAN Tx

2.G WL/BT Rx

Bluetooth Host I/F

FM Rx Host I/F

I²S

3PST Switch

PCM

BT_DEV_WAKE

BT_HOST_WAKE

BT Tx

FM Rx

FM Audio Out

I²S

FM I/F

4354-DS109-R

5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203

October 15, 2014

BCM4354 Data Sheet

Revision History

FEATURES

IEEE 802.11X Key Features

•

PCIe mode complies with PCI Express base

specification revision 3.0 for ×1 lane and power

management running at Gen1 speeds.

•

IEEE 802.11ac Draft compliant.

Dual–stream spatial multiplexing up to

867 Mbps data rate.

Integrated ARMCR4™ processor with tightly coupled

memory for complete WLAN subsystem functionality,

minimizing the need to wake up the applications

processor for standard WLAN functions. This allows for

further minimization of power consumption, while

maintaining the ability to field upgrade with future

features. On–chip memory includes 768 KB SRAM and

640 KB ROM.

•

Supports 20, 40, and 80 MHz channels with

optional SGI (256 QAM modulation).

Full IEEE 802.11a/b/g/n legacy compatibility

with enhanced performance.

TX and RX low–density parity check (LDPC)

support for improved range and power

efficiency.

•

OneDriver™ software architecture for easy migration

from existing embedded WLAN and Bluetooth devices

as well as future devices.

•

Supports IEEE 802.11ac/n beamforming.

On–chip power amplifiers and low–noise

amplifiers for both bands.

Bluetooth and FM Key Features

•

Supports various RF front–end architectures

including:

•

Complies with Bluetooth Core Specification Version 4.1

with provisions for supporting future specifications.

– Two antennas with one each dedicated to

Bluetooth and WLAN.

•

Bluetooth Class 1 or Class 2 transmitter operation.

Supports extended synchronous connections (eSCO),

for enhanced voice quality by allowing for retransmission

of dropped packets.

– Two antennas with WLAN diversity and a

shared Bluetooth antenna.

•

Shared Bluetooth and WLAN receive signal

path eliminates the need for an external

power splitter while maintaining excellent

sensitivity for both Bluetooth and WLAN.

•

Adaptive frequency hopping (AFH) for reducing radio

frequency interference.

Interface support, host controller interface (HCI) using a

USB or high–speed UART interface and PCM for audio

data.

•

Internal fractional nPLL allows support for a

wide range of reference clock frequencies

•

USB 2.0 full–speed (12 Mbps) supported for Bluetooth.

The FM unit supports HCI for communication.

Supports IEEE 802.15.2 external

coexistence interface to optimize bandwidth

utilization with other co–located wireless.

technologies such as LTE or GPS.

Low power consumption improves battery life of

handheld devices.

•

FM receiver: 65 MHz to 108 MHz FM bands; supports

the European radio data systems (RDS) and the North

American radio broadcast data system (RBDS)

standards.

•

Supports standard SDIO v3.0 (up to SDR104

mode at 208 MHz, 4–bit and 1-bit) host

interfaces.

•

Backward compatible with SDIO v2.0 host

interfaces.

•

Supports multiple simultaneous Advanced Audio

Distribution Profiles (A2DP) for stereo sound.

Alternative host interface supports HSIC v1.0

Automatic frequency detection for standard crystal and

TCXO values.

Supports serial flash interfaces.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 2

BROADCOM CONFIDENTIAL

FEATURES

General Features

•

Security:

•

Supports battery range from 3.0V to 5.25V

supplies with internal switching regulator.

– WPA™ and WPA2™ (Personal) support for powerful

encryption and authentication

•

Programmable dynamic power management

– AES and TKIP in hardware for faster data encryption

and IEEE 802.11i compatibility

– Reference WLAN subsystem provides Cisco^®

Compatible Extensions (CCX, CCX 2.0, CCX 3.0,

CCX 4.0, CCX 5.0)

484 bytes of user-accessible OTP for storing

board parameters

•

GPIOs: 11 in WLBGA, 16 in WLCSP

Package options:

– Reference WLAN subsystem provides Wi-Fi

Protected Setup (WPS)

– 192-ball WLBGA (4.87 mm × 7.67 mm,

0.4 mm pitch

•

Worldwide regulatory support: Global products

supported with worldwide homologated design.

– 395-bump WLCSP (4.87 mm × 7.67 mm,

0.2 mm pitch)

Broadcom Corporation

5300 California Avenue

Irvine, CA 92617

Printed in the U.S.A.

Broadcom^®, the pulse logo, Connecting everything^®, the Connecting everything logo, OneDriver™, and

SmartAudio^®are among the trademarks of Broadcom Corporation and/or its affiliates in the United States,

certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their

respective owners.

This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed,

intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations,

pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES

THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL

WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-

BCM4354 Data Sheet

Revision History

Revision

Date

Change Description

4354-DS109-R

10/15/14

Updated:

•

“I/O States” on page 122.

Figure 52: “WLBGA Keep-Out Areas for PCB Layout (Top View, Balls

Facing Down),” on page 187.

4354-DS108-R

4354-DS107-R

08/08/14

06/30/14

Updated:

Changed document type from “Preliminary Data Sheet” to “Data

Sheet”.

Updated:

•

“BCM4354 PMU Features” on page 22

Figure 3: “Typical Power Topology for the BCM4354,” on page 23

Table 18: “Pin List by Pin Number (192-Pin WLBGA Package),” on

page 85

•

Table 19: “Pin List by Pin Name (192-Pin WLBGA Package),” on page

88

•

Table 20: “395-Bump WLCSP Coordinates,” on page 91

Table 21: “WLCSP Signal Descriptions,” on page 102

Table 60: “PCI Express Interface Parameters,” on page 175

Added:

•

“Electrostatic Discharge Specifications” on page 124

4354-DS106-R

4354-DS105-R

05/20/14

04/02/14

Updated:

•

Section 24: “Ordering Information,” on page 189.

Updated:

•

Table 4: “External 32.768 kHz Sleep Clock Specifications,” on page

28

Figure 34: “WLBGA Ball Map, 4.87 × 7.67 Array, 192-Ball, A7–V12

(Bottom View — Balls Facing Up),” on page 84

Table 49: “Bluetooth BLE and FM Current Consumption,” on page

164

•

“Receiver Path” on page 80

Figure 32: “Radio Functional Block Diagram (core 0),” on page 81

Table 38: “WLAN 2.4 GHz Receiver Performance Specifications,” on

page 139

•

Table 39: “WLAN 2.4 GHz Transmitter Performance Specifications,”

on page 145

Table 40: “WLAN 5 GHz Receiver Performance Specifications,” on

page 147

Table 41: “WLAN 5 GHz Transmitter Performance Specifications,” on

page 154

General Spurious Emissions Specifications (deleted)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 4

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Revision History

Revision

Date

Change Description

4354-DS104-R

03/24/14

Updated:

•

Table 4: “External 32.768 kHz Sleep Clock Specifications,” on page

28

Figure 33: “WLBGA Ball Map, 4.87 × 7.67 Array, 192-Balls, A7–V12

(Bottom View — Balls Facing Up),” on page 83

Table 20: “395-Bump WLCSP Coordinates,” on page 90 (Modified

Bump 230, see note at end of the Table 20.)

Table 32: “Bluetooth Receiver RF Specifications,” on page 129

(footnotes modified)

Table 50: “Bluetooth BLE and FM Current Consumption,” on page

167

4354-DS103-R

4354-DS102-R

12/20/13

12/12/13

Updated:

Table 33: “Environmental Ratings,” on page 141: Ambient

temperature range for functional operation is now –30°C to +85°C.

Updated:

•

The BCM4354 now supports PCI Express base specification v3.0

running at Gen1 speeds.

“WLAN 2.4 GHz Receiver Performance Specifications” on page 158:

Note update.

“WLAN 2.4 GHz Transmitter Performance Specifications” on page

170: Note update.

“WLAN 5 GHz Receiver Performance Specifications” on page 174:

Note update.

“WLAN 5 GHz Transmitter Performance Specifications” on page 187:

Note update.

•

“Package Thermal Characteristics” on page 219: Note update.

Section 24: “Ordering Information,” on page 227.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 5

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Revision History

Revision

Date

Change Description

4354-DS101-R

11/06/13

Updated:

•

Section 2: “Power Supplies and Power Management,” on page 27.

“WLAN Power Management” on page 29.

“Crystal Interface and Clock Generation” on page 32.

Table 4: “Crystal Oscillator and External Clock — Requirements and

Performance,” on page 33: Frequency conditions.

•

Figure 7: “Startup Signaling Sequence,” on page 43.

“Receiver Path” on page 88.

“Transmit Path” on page 88.

Section 13: “Pinout and Signal Descriptions,” on page 89.

Table 29: “GPIO Alternative Signal Functions,” on page 135.

Table 34: “Recommended Operating Conditions and DC

Characteristics,” on page 142: DC supply voltage for digital I/O

(minimum value).

•

Table 42: “WLAN 2.4 GHz Receiver Performance Specifications,” on

page 163: SISO/MIMO RX sensitivity.

Table 46: “WLAN 5 GHz Receiver Performance Specifications,” on

page 180: SISO/MIMO RX sensitivity.

•

Table 51: “LDO3P3 Specifications,” on page 192.

Table 57: “Typical WLAN Power Consumption,” on page 199.

Table 58: “Bluetooth BLE and FM Current Consumption,” on page

201.

•

Section 22: “Package Information,” on page 219.

Section 23: “Mechanical Information,” on page 221.

Section 24: “Ordering Information,” on page 226.

Added:

•

Figure 4: “Typical Power Topology for the BCM435X,” on page 28.

“External 32.768 kHz Low-Power Oscillator” on page 35.

Table 30: “GPIO Status Vs. Test Modes,” on page 136.

Table 52: “LDO3P3_B Specifications,” on page 193.

4354-DS100-R

07/31/13

Initial release

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 6

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Table of Contents

About This Document ................................................................................................................................ 16

Purpose and Audience.......................................................................................................................... 16

Acronyms and Abbreviations................................................................................................................. 16

References............................................................................................................................................ 16

Technical Support ...................................................................................................................................... 16

Section 1: Overview .......................................................................................................... 17

Overview...................................................................................................................................................... 17

Features....................................................................................................................................................... 19

Standards Compliance...............................................................................................................................20

Section 2: Power Supplies and Power Management ..................................................... 22

Power Supply Topology............................................................................................................................. 22

BCM4354 PMU Features ............................................................................................................................ 22

WLAN Power Management........................................................................................................................ 24

PMU Sequencing ........................................................................................................................................ 25

Power-Off Shutdown.................................................................................................................................. 26

Power-Up/Power-Down/Reset Circuits..................................................................................................... 26

Section 3: Frequency References.................................................................................... 27

Crystal Interface and Clock Generation ................................................................................................... 27

External Frequency Reference.................................................................................................................. 28

External 32.768 kHz Low-Power Oscillator .............................................................................................. 30

Section 4: Bluetooth + FM Subsystem Overview ........................................................... 31

Features....................................................................................................................................................... 31

Bluetooth Radio.......................................................................................................................................... 33

Transmit ................................................................................................................................................ 33

Digital Modulator ................................................................................................................................... 33

Digital Demodulator and Bit Synchronizer............................................................................................. 33

Power Amplifier..................................................................................................................................... 33

Receiver................................................................................................................................................ 34

Digital Demodulator and Bit Synchronizer............................................................................................. 34

Receiver Signal Strength Indicator........................................................................................................ 34

Local Oscillator Generation................................................................................................................... 34

Calibration ............................................................................................................................................. 34

Section 5: Bluetooth Baseband Core .............................................................................. 35

Bluetooth 4.1 Features...............................................................................................................................35

Bluetooth Low Energy ...............................................................................................................................35

Link Control Layer...................................................................................................................................... 36

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 7

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Table of Contents

Test Mode Support..................................................................................................................................... 36

Bluetooth Power Management Unit.......................................................................................................... 37

RF Power Management ........................................................................................................................ 37

Host Controller Power Management ..................................................................................................... 37

BBC Power Management...................................................................................................................... 39

FM Power Management........................................................................................................................ 39

Wideband Speech................................................................................................................................. 39

Packet Loss Concealment..................................................................................................................... 40

Audio Rate-Matching Algorithms........................................................................................................... 40

Codec Encoding.................................................................................................................................... 41

Multiple Simultaneous A2DP Audio Stream.......................................................................................... 41

FM Over Bluetooth ................................................................................................................................ 41

Burst Buffer Operation........................................................................................................................... 41

Adaptive Frequency Hopping.................................................................................................................... 41

Advanced Bluetooth/WLAN Coexistence................................................................................................. 42

Fast Connection (Interlaced Page and Inquiry Scans) ........................................................................... 42

Section 6: Microprocessor and Memory Unit for Bluetooth.......................................... 43

RAM, ROM, and Patch Memory................................................................................................................. 43

Reset............................................................................................................................................................ 43

Section 7: Bluetooth Peripheral Transport Unit ............................................................. 44

SPI Interface................................................................................................................................................ 44

SPI/UART Transport Detection.................................................................................................................. 44

PCM Interface.............................................................................................................................................. 45

Slot Mapping ......................................................................................................................................... 45

Frame Synchronization ......................................................................................................................... 45

Data Formatting..................................................................................................................................... 45

Wideband Speech Support ................................................................................................................... 46

Multiplexed Bluetooth and FM Over PCM............................................................................................. 46

Burst PCM Mode................................................................................................................................... 47

PCM Interface Timing............................................................................................................................ 47

Short Frame Sync, Master Mode ................................................................................................... 47

Short Frame Sync, Slave Mode ..................................................................................................... 48

Long Frame Sync, Master Mode.................................................................................................... 49

Long Frame Sync, Slave Mode...................................................................................................... 50

Short Frame Sync, Burst Mode...................................................................................................... 51

Long Frame Sync, Burst Mode ...................................................................................................... 52

USB Interface.............................................................................................................................................. 53

Features................................................................................................................................................ 53

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 8

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Table of Contents

Operation............................................................................................................................................... 53

USB Hub and UHE Support .................................................................................................................. 54

USB Full-Speed Timing......................................................................................................................... 55

UART Interface............................................................................................................................................ 56

I²S Interface................................................................................................................................................. 58

I²S Timing.............................................................................................................................................. 59

Section 8: FM Receiver Subsystem................................................................................. 61

FM Radio ..................................................................................................................................................... 61

Digital FM Audio Interfaces ....................................................................................................................... 61

FM Over Bluetooth ..................................................................................................................................... 61

eSCO............................................................................................................................................................ 61

Wide Band Speech Link............................................................................................................................. 62

A2DP............................................................................................................................................................ 62

Autotune and Search Algorithms ............................................................................................................. 62

Audio Features ........................................................................................................................................... 63

RDS/RBDS................................................................................................................................................... 65

Section 9: WLAN Global Functions ................................................................................. 66

WLAN CPU and Memory Subsystem........................................................................................................ 66

One-Time Programmable Memory............................................................................................................ 66

GPIO Interface............................................................................................................................................. 66

External Coexistence Interface ................................................................................................................. 67

UART Interface............................................................................................................................................ 68

JTAG Interface............................................................................................................................................ 68

SPROM Interface ........................................................................................................................................ 68

SFLASH Interface ....................................................................................................................................... 68

Section 10: WLAN Host Interfaces................................................................................... 69

SDIO v3.0..................................................................................................................................................... 69

SDIO Pins.............................................................................................................................................. 69

HSIC Interface ............................................................................................................................................ 70

PCI Express Interface................................................................................................................................. 71

Transaction Layer Interface................................................................................................................... 72

Data Link Layer..................................................................................................................................... 72

Physical Layer....................................................................................................................................... 73

Logical Subblock................................................................................................................................... 73

Scrambler/Descrambler......................................................................................................................... 73

8B/10B Encoder/Decoder...................................................................................................................... 73

Elastic FIFO........................................................................................................................................... 73

Electrical Subblock................................................................................................................................ 74

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 9

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Table of Contents

Configuration Space.............................................................................................................................. 74

Section 11: Wireless LAN MAC and PHY ........................................................................ 75

IEEE 802.11ac Draft MAC........................................................................................................................... 75

PSM ............................................................................................................................................... 76

WEP............................................................................................................................................... 77

TXE................................................................................................................................................ 77

RXE................................................................................................................................................ 77

IFS.................................................................................................................................................. 77

TSF ................................................................................................................................................ 78

NAV................................................................................................................................................ 78

MAC-PHY Interface........................................................................................................................ 78

IEEE 802.11ac Draft PHY............................................................................................................................ 79

Section 12: WLAN Radio Subsystem ............................................................................. 81

Receiver Path.............................................................................................................................................. 81

Transmit Path.............................................................................................................................................. 81

Calibration................................................................................................................................................... 83

Section 13: Pinout and Signal Descriptions ................................................................... 84

Ball Maps..................................................................................................................................................... 84

Pin Lists....................................................................................................................................................... 86

Signal Descriptions.................................................................................................................................. 103

WLAN/BT GPIO Signals and Strapping Options ................................................................................... 119

GPIO Alternative Signal Functions......................................................................................................... 120

I/O States................................................................................................................................................... 122

Section 14: DC Characteristics ...................................................................................... 125

Absolute Maximum Ratings .................................................................................................................... 125

Environmental Ratings ............................................................................................................................ 126

Electrostatic Discharge Specifications .................................................................................................. 126

Recommended Operating Conditions and DC Characteristics ........................................................... 127

Section 15: Bluetooth RF Specifications ...................................................................... 129

Section 16: FM Receiver Specifications........................................................................ 135

Section 17: WLAN RF Specifications ............................................................................ 140

Introduction............................................................................................................................................... 140

2.4 GHz Band General RF Specifications............................................................................................... 140

WLAN 2.4 GHz Receiver Performance Specifications .......................................................................... 141

WLAN 2.4 GHz Transmitter Performance Specifications ..................................................................... 147

WLAN 5 GHz Receiver Performance Specifications ............................................................................. 149

WLAN 5 GHz Transmitter Performance Specifications ........................................................................ 156

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 10

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Table of Contents

Section 18: Internal Regulator Electrical Specifications ............................................. 158

Core Buck Switching Regulator.............................................................................................................. 158

3.3V LDO (LDO3P3) .................................................................................................................................. 159

3.3V LDO (LDO3P3_B).............................................................................................................................. 160

2.5V LDO (BTLDO2P5) ............................................................................................................................. 161

CLDO ......................................................................................................................................................... 162

LNLDO ....................................................................................................................................................... 163

Section 19: System Power Consumption...................................................................... 164

WLAN Current Consumption................................................................................................................... 164

Bluetooth and FM Current Consumption............................................................................................... 166

Section 20: Interface Timing and AC Characteristics.................................................. 167

SDIO Timing.............................................................................................................................................. 167

SDIO Default Mode Timing ................................................................................................................. 167

SDIO High-Speed Mode Timing.......................................................................................................... 169

SDIO Bus Timing Specifications in SDR Modes ................................................................................. 170

Clock Timing ................................................................................................................................ 170

Device Input Timing ..................................................................................................................... 171

Device Output Timing................................................................................................................... 172

SDIO Bus Timing Specifications in DDR50 Mode............................................................................... 174

Data Timing, DDR50 Mode.......................................................................................................... 175

HSIC Interface Specifications.................................................................................................................. 176

PCI Express Interface Parameters.......................................................................................................... 177

JTAG Timing ............................................................................................................................................. 179

Section 21: Power-Up Sequence and Timing ............................................................... 180

Sequencing of Reset and Regulator Control Signals ........................................................................... 180

Description of Control Signals............................................................................................................. 180

Control Signal Timing Diagrams.......................................................................................................... 181

Section 22: Package Information................................................................................... 184

Package Thermal Characteristics........................................................................................................... 184

Junction Temperature Estimation and PSI_JTVersus Theta_JC.............................................................. 185

Environmental Characteristics................................................................................................................ 185

Section 23: Mechanical Information .............................................................................. 186

Section 24: Ordering Information .................................................................................. 190

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 11

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

List of Figures

Figure 1: Functional Block Diagram................................................................................................................... 1

Figure 2: BCM4354 Block Diagram ................................................................................................................. 18

Figure 3: Typical Power Topology for the BCM4354 ....................................................................................... 23

Figure 4: Recommended Oscillator Configuration ........................................................................................... 27

Figure 5: Recommended Circuit to Use with an External Reference Clock..................................................... 28

Figure 6: Startup Signaling Sequence ............................................................................................................. 38

Figure 7: CVSD Decoder Output Waveform Without PLC............................................................................... 40

Figure 8: CVSD Decoder Output Waveform After Applying PLC..................................................................... 40

Figure 9: Functional Multiplex Data Diagram................................................................................................... 46

Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode).............................................................. 47

Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)................................................................ 48

Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 49

Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 50

Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)......................................................... 51

Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 52

Figure 16: USB Compounded Device Configuration ....................................................................................... 53

Figure 17: USB Full-Speed Timing .................................................................................................................. 55

Figure 18: UART Timing .................................................................................................................................. 57

Figure 19: I²S Transmitter Timing.................................................................................................................... 60

Figure 20: I²S Receiver Timing........................................................................................................................ 60

Figure 21: Example Blend/Switch Usage......................................................................................................... 63

Figure 22: Example Blend/Switch Separation.................................................................................................. 64

Figure 23: Example Soft Mute Characteristic .................................................................................................. 64

Figure 24: Broadcom GCI Mode LTE Coexistence Interface........................................................................... 67

Figure 25: Legacy 3-Wire LTE Coexistence Interface ..................................................................................... 67

Figure 26: Signal Connections to SDIO Host (SD 4-Bit Mode)........................................................................ 70

Figure 27: Signal Connections to SDIO Host (SD 1-Bit Mode)........................................................................ 70

Figure 28: HSIC Device Block Diagram........................................................................................................... 71

Figure 29: PCI Express Layer Model............................................................................................................... 72

Figure 30: WLAN MAC Architecture ................................................................................................................ 75

Figure 31: WLAN PHY Block Diagram............................................................................................................. 80

Figure 32: Radio Functional Block Diagram (core 0)....................................................................................... 82

Figure 33: WLBGA Ball Map, 4.87 mm × 7.67 mm Array, 192-Ball, A1–V6 (Bottom View—Balls Facing Up)84

Figure 34: WLBGA Ball Map, 4.87 × 7.67 Array, 192-Ball, A7 – V12 (Bottom View—Balls Facing Up) ......... 85

Figure 35: RF Port Location for Bluetooth Testing......................................................................................... 129

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 12

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

List of Figures

Figure 36: Port Locations (Applies to 2.4 GHz and 5 GHz) ........................................................................... 140

Figure 37: SDIO Bus Timing (Default Mode) ................................................................................................. 167

Figure 38: SDIO Bus Timing (High-Speed Mode).......................................................................................... 169

Figure 39: SDIO Clock Timing (SDR Modes) ................................................................................................ 170

Figure 40: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 171

Figure 41: SDIO Bus Output Timing (SDR Modes up to 100 MHz)............................................................... 172

Figure 42: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)..................................................... 172

Figure 43: ∆t_OPConsideration for Variable Data Window (SDR 104 Mode) ................................................. 173

Figure 44: SDIO Clock Timing (DDR50 Mode).............................................................................................. 174

Figure 45: SDIO Data Timing (DDR50 Mode) ............................................................................................... 175

Figure 46: WLAN = ON, Bluetooth = ON ....................................................................................................... 181

Figure 47: WLAN = OFF, Bluetooth = OFF.................................................................................................... 181

Figure 48: WLAN = ON, Bluetooth = OFF ..................................................................................................... 182

Figure 49: WLAN = OFF, Bluetooth = ON ..................................................................................................... 182

Figure 50: WLAN Boot-Up Sequence............................................................................................................ 183

Figure 51: 192-Ball WLBGA Package Mechanical Information ..................................................................... 186

Figure 52: WLBGA Keep-Out Areas for PCB Layout (Top View, Balls Facing Down) .................................. 187

Figure 53: 395-Bump WLCSP Package ........................................................................................................ 188

Figure 54: WLCSP Keep-Out Areas for PCB Layout (Top View, Balls Facing Down)................................... 189

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 13

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

List of Tables

Table 1: Device Options and Features ............................................................................................................ 17

Table 2: Power-Up/Power-Down/Reset Control Signals.................................................................................. 26

Table 3: Crystal Oscillator and External Clock—Requirements and Performance ......................................... 28

Table 4: External 32.768 kHz Sleep Clock Specifications ............................................................................... 30

Table 5: Power Control Pin Description........................................................................................................... 37

Table 6: SPI to UART Signal Mapping............................................................................................................. 44

Table 7: PCM Interface Timing Specifications (Short Frame Sync, Master Mode).......................................... 47

Table 8: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)............................................ 48

Table 9: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) .......................................... 49

Table 10: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) .......................................... 50

Table 11: PCM Burst Mode (Receive Only, Short Frame Sync)...................................................................... 51

Table 12: PCM Burst Mode (Receive Only, Long Frame Sync) ...................................................................... 52

Table 13: USB Full-Speed Timing Specifications ............................................................................................ 55

Table 14: Example of Common Baud Rates.................................................................................................... 56

Table 15: UART Timing Specifications ............................................................................................................ 57

Table 16: Timing for I²S Transmitters and Receivers...................................................................................... 59

Table 17: SDIO Pin Descriptions ..................................................................................................................... 69

Table 18: Pin List by Pin Number (192-Pin WLBGA Package)........................................................................ 86

Table 19: Pin List by Pin Name (192-Pin WLBGA Package)........................................................................... 89

Table 20: 395-Bump WLCSP Coordinates ...................................................................................................... 92

Table 21: WLCSP Signal Descriptions .......................................................................................................... 103

Table 22: WLBGA Signal Descriptions .......................................................................................................... 111

Table 23: WLAN GPIO Functions and Strapping Options ............................................................................. 119

Table 24: BT GPIO Functions and Strapping Options................................................................................... 119

Table 25: GPIO_[10, 9, 8] Host Interface Selection....................................................................................... 119

Table 26: GPIO Alternative Signal Functions ................................................................................................ 120

Table 27: GPIO Status Vs. Test Modes......................................................................................................... 121

Table 28: I/O States....................................................................................................................................... 122

Table 29: Absolute Maximum Ratings ........................................................................................................... 125

Table 30: Environmental Ratings................................................................................................................... 126

Table 31: Electrostatic Discharge Specifications........................................................................................... 126

Table 32: Recommended Operating Conditions and DC Characteristics...................................................... 127

Table 33: Bluetooth Receiver RF Specifications............................................................................................ 129

Table 34: Bluetooth Transmitter RF Specifications........................................................................................ 132

Table 35: Local Oscillator Performance......................................................................................................... 134

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 14

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

List of Tables

Table 36: BLE RF Specifications ................................................................................................................... 134

Table 37: FM Receiver Specifications ........................................................................................................... 135

Table 38: 2.4 GHz Band General RF Specifications...................................................................................... 140

Table 39: WLAN 2.4 GHz Receiver Performance Specifications .................................................................. 141

Table 40: WLAN 2.4 GHz Transmitter Performance Specifications .............................................................. 147

Table 41: WLAN 5 GHz Receiver Performance Specifications ..................................................................... 149

Table 42: WLAN 5 GHz Transmitter Performance Specifications ................................................................. 156

Table 43: Core Buck Switching Regulator (CBUCK) Specifications.............................................................. 158

Table 44: LDO3P3 Specifications.................................................................................................................. 159

Table 45: LDO3P3_B Specifications.............................................................................................................. 160

Table 46: BTLDO2P5 Specifications ............................................................................................................. 161

Table 47: CLDO Specifications...................................................................................................................... 162

Table 48: LNLDO Specifications.................................................................................................................... 163

Table 49: Typical WLAN Power Consumption............................................................................................... 164

Table 50: Bluetooth BLE and FM Current Consumption................................................................................ 166

Table 51: SDIO Bus Timing Parameters (Default Mode)............................................................................... 168

Table 52: SDIO Bus Timing Parameters (High-Speed Mode) ....................................................................... 169

Table 53: SDIO Bus Clock Timing Parameters (SDR Modes)....................................................................... 170

Table 54: SDIO Bus Input Timing Parameters (SDR Modes)........................................................................ 171

Table 55: SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)............................................. 172

Table 56: SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) .................................. 173

Table 57: SDIO Bus Clock Timing Parameters (DDR50 Mode) .................................................................... 174

Table 58: SDIO Bus Timing Parameters (DDR50 Mode) .............................................................................. 175

Table 59: HSIC Interface Parameters............................................................................................................ 176

Table 60: PCI Express Interface Parameters ................................................................................................ 177

Table 61: JTAG Timing Characteristics ......................................................................................................... 179

Table 62: WLCSP Package Thermal Characteristics .................................................................................... 184

Table 63: WLBGA Package Thermal Characteristics.................................................................................... 184

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 15

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

About This Document

Purpose and Audience

This data sheet provides details on the functional, operational, and electrical characteristics for the Broadcom®

BCM4354. It is intended for hardware design, application, and OEM engineers.

Acronyms and Abbreviations

In most cases, acronyms and abbreviations are defined on first use.

For a comprehensive list of acronyms and other terms used in Broadcom documents, go to:

http://www.broadcom.com/press/glossary.php.

References

The references in this section may be used in conjunction with this document.

Note: Broadcom provides customer access to technical documentation and software through its

Customer Support Portal (CSP) and Downloads & Support site (see Technical Support).

For Broadcom documents, replace the “xx” in the document number with the largest number available in the

repository to ensure that you have the most current version of the document.

Document (or Item) Name

Number

Source

[1] Bluetooth MWS Coexistence 2–wire Transport Interface –

www.bluetooth.com

Specification

Technical Support

Broadcom provides customer access to a wide range of information, including technical documentation,

schematic diagrams, product bill of materials, PCB layout information, and software updates through its

customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering

support representative.

In addition, Broadcom provides other product support through its Downloads & Support site

(http://www.broadcom.com/support/).

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 16

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Overview

Section 1: Overview

Overview

The Broadcom^®BCM4354 single-chip device provides the highest level of integration for a mobile or handheld

wireless system, with integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio, Bluetooth 4.1 + EDR (enhanced

data rate), and FM receiver. It provides a small form-factor solution with minimal external components to drive

down cost for mass volumes and allows for handheld device flexibility in size, form, and function.

Comprehensive power management circuitry and software ensure the system can meet the needs of highly

mobile devices that require minimal power consumption and reliable operation.

Figure 2 on page 18 shows the interconnect of all the major physical blocks in the BCM4354 and their

associated external interfaces, which are described in greater detail in the following sections.

Table 1: Device Options and Features

Feature

WLBGA

WLCSP

Package ball count

PCIe

192 pins

395 bumps

Yes

USB2.0 (Bluetooth)

HSIC

Yes

I²S

Multiplexed onto six parallel flash pins

No

GPIO

SDIO 3.0

11

16

Yes

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 17

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Features

The BCM4354 supports the following features:

•

IEEE 802.11a/b/g/n/ac dual-band 2x2 MIMO radio with virtual-simultaneous dual-band operation

Bluetooth v4.1 + EDR with integrated Class 1 PA

Concurrent Bluetooth, FM (RX) RDS/RBDS, and WLAN operation

On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality

Single- and dual-antenna support

– Single antenna with shared LNA

– Simultaneous BT/WLAN receive with single antenna

WLAN host interface options:

•

– SDIO v3.0 (1-bit/4-bit)—up to 208 MHz clock rate in SDR104 mode

– HSIC (USB device interface for short distance on-board applications)

– PCIe 2.0

•

BT host digital interface (can be used concurrently with above interfaces):

– UART (up to 4 Mbps)

•

BT supports full-speed USB 2.0-compliant interface

ECI—enhanced coexistence support, ability to coordinate BT SCO transmissions around WLAN receives

I²S/PCM for FM/BT audio, HCI for FM block control

HCI high-speed UART (H4, H4+, H5) transport support

Wideband speech support (16 bits linear data, MSB first, left justified at 4K samples/s for transparent air

coding, both through I²S and PCM interface)

•

Bluetooth SmartAudio^®technology improves voice and music quality to headsets

Bluetooth low power inquiry and page scan

Bluetooth Low Energy (BLE) support

Bluetooth Packet Loss Concealment (PLC)

Bluetooth Wide Band Speech (WBS)

FM advanced internal antenna support

FM auto search/tuning functions

FM multiple audio routing options: I²S, PCM, eSCO, and A2DP

FM mono-stereo blend and switch, and soft mute support

FM audio pause detect support

Audio rate-matching algorithms

Multiple simultaneous A2DP audio stream

FM over Bluetooth operation and on-chip stereo headset emulation (SBC)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 19

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Standards Compliance

The BCM4354 supports the following standards:

•

Bluetooth 2.1 + EDR

Bluetooth 3.0 + HS

Bluetooth 4.1 (Bluetooth Low Energy)

65 MHz to 108 MHz FM bands (US, Europe, and Japan)

IEEE802.11ac mandatory and optional requirements for 20 MHz, 40 MHz, and 80 MHz channels

IEEE 802.11n—Handheld Device Class (Section 11)

IEEE 802.11a

IEEE 802.11b

IEEE 802.11g

IEEE 802.11d

IEEE 802.11h

IEEE 802.11i

Security:

– WEP

– WPA™ Personal

– WPA2™ Personal

– WMM

– WMM-PS (U-APSD)

– WMM-SA

– AES (Hardware Accelerator)

– TKIP (HW Accelerator)

– CKIP (SW Support)

•

Proprietary Protocols:

– CCXv2

– CCXv3

– CCXv4

– CCXv5

IEEE 802.15.2 Coexistence Compliance—on silicon solution compliant with IEEE 3 wire requirements

The BCM4354 will support the following future drafts/standards:

•

IEEE 802.11r—Fast Roaming (between APs)

IEEE 802.11w—Secure Management Frames

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 20

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Standards Compliance

•

IEEE 802.11 Extensions:

– IEEE 802.11e QoS Enhancements (In accordance with the WMM^®specification, QoS is already

supported.)

– IEEE 802.11h 5 GHz Extensions

– IEEE 802.11i MAC Enhancements

– IEEE 802.11k Radio Resource Measurement

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 21

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Power Supplies and Power Management

Section 2: Power Supplies and Power

Management

Power Supply Topology

One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the

BCM4354. All regulators are programmable via the PMU. These blocks simplify power supply design for

Bluetooth, WLAN, and FM functions in embedded designs.

A single VBAT (3.0V to 5.25V DC max.) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages

being provided by the regulators in the BCM4354.

Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the

respective section out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are

deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted.

The CLDO and LNLDO may be turned off/on based on the dynamic demands of the digital baseband.

The BCM4354 allows for an extremely low power-consumption mode by completely shutting down the CBUCK,

CLDO, and LNLDO regulators. When in this state, LPLDO1 (which is a low-power linear regulator supplied by

the system VIO supply) provides the BCM4354 with all the voltages it requires, further reducing leakage

currents.

BCM4354 PMU Features

•

VBAT to 1.35Vout (600 mA maximum) Core-Buck (CBUCK) switching regulator

VBAT to 3.3Vout (600 mA maximum) LDO3P3

VBAT to 3.3Vout (150 mA maximum) LDO3P3_B

VBAT to 2.5V out (70 mA maximum) BTLDO2P5

1.35V to 1.2Vout (150 mA maximum) LNLDO

1.35V to 1.2Vout (300 mA maximum) CLDO with bypass mode for deep-sleep

Additional internal LDOs (not externally accessible)

Figure 3 on page 23 illustrates the typical power topology for the BCM4354. The shaded areas are internal to

the BCM4354.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 22

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN Power Management

The BCM4354 has been designed with the stringent power consumption requirements of mobile devices in

mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell

libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM4354 integrated

RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is

leakage current only. Additionally, the BCM4354 includes an advanced WLAN power management unit (PMU)

sequencer. The PMU sequencer provides significant power savings by putting the BCM4354 into various power

management states appropriate to the current environment and activities that are being performed. The power

management unit enables and disables internal regulators, switches, and other blocks based on a computation

of the required resources and a table that describes the relationship between resources and the time needed to

enable and disable them. Power up sequences are fully programmable. Configurable, free-running counters

(running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and

power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock

speeds are used wherever possible.

The BCM4354 WLAN power states are described as follows:

•

Active mode— All WLAN blocks in the BCM4354 are powered up and fully functional with active carrier

sensing and frame transmission and receiving. All required regulators are enabled and put in the most

efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer.

Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators

are powered off. All main clocks (PLL, crystal oscillator, or TCXO) are shut down to reduce active power to

the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is

necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. Logic states in

the digital core are saved and preserved into a retention memory in the always-ON domain before the

digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a

host resume through the HSIC or SDIO bus, logic states in the digital core are restored to their pre-deep-

sleep settings to avoid lengthy HW reinitialization. In Deep-sleep mode, the primary source of power

consumption is leakage current.

•

Power-down mode—The BCM4354 is effectively powered off by shutting down all internal regulators. The

chip is brought out of this mode by external logic re-enabling the internal regulators.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 24

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PMU Sequencing

The PMU sequencer is responsible for minimizing system power consumption. It enables and disables various

system resources based on a computation of the required resources and a table that describes the relationship

between resources and the time needed to enable and disable them.

Resource requests may come from several sources: clock requests from cores, the minimum resources defined

in the ResourceMin register, and the resources requested by any active resource request timers. The PMU

sequencer maps clock requests into a set of resources required to produce the requested clocks.

Each resource is in one of four states: enabled, disabled, transition_on, and transition_off and has a timer that

contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. The timer is

loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be

enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state

changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can

go immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can go

immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the

immediate transition or the timer load-decrement sequence.

During each clock cycle, the PMU sequencer performs the following actions:

•

Computes the required resource set based on requests and the resource dependency table.

Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the

ResourcePending bit for the resource and inverts the ResourceState bit.

•

Compares the request with the current resource status and determines which resources must be enabled

or disabled.

Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no

powered up dependents.

Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its

dependencies enabled.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 25

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Power-Off Shutdown

The BCM4354 provides a low-power shutdown feature that allows the device to be turned off while the host, and

any other devices in the system, remain operational. When the BCM4354 is not needed in the system,

VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM4354 to be effectively

off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected

to the I/O.

During a low-power shut-down state, provided VDDIO remains applied to the BCM4354, all outputs are tristated,

and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation.

This is done to prevent current paths or create loading on any digital signals in the system, and enables the

BCM4354 to be fully integrated in an embedded device and take full advantage of the lowest power-savings

modes.

When the BCM4354 is powered on from this state, it is the same as a normal power-up and the device does not

retain any information about its state from before it was powered down.

Power-Up/Power-Down/Reset Circuits

The BCM4354 has two signals (see Table 2) that enable or disable the Bluetooth and WLAN circuits and the

internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals

and the required power-up sequences, see Section 21: “Power-Up Sequence and Timing,” on page 180.

Table 2: Power-Up/Power-Down/Reset Control Signals

Signal

Description

WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power up the WLAN section. It is also

OR-gated with the BT_REG_ON input to control the internal BCM4354 regulators. When this

pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is

low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the

regulators are disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by

default. It can be disabled through programming.

BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down

the internal BCM4354 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators

will be disabled. This pin has an internal 200 kΩ pull-down resistor that is enabled by default.

It can be disabled through programming.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 26

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Frequency References

Section 3: Frequency References

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative,

an external frequency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower

power mode timing.

Crystal Interface and Clock Generation

The BCM4354 can use an external crystal to provide a frequency reference. The recommended configuration

for the crystal oscillator including all external components is shown in Figure 4. Consult the reference

schematics for the latest configuration.

Figure 4: Recommended Oscillator Configuration

C*

WRF_XTAL_I N

37.4 MHz

C*

X ohms*

WRF_XTAL_OUT

* Values determined by crystal

drive level. See reference

schematics for details.

A fractional-N synthesizer in the BCM4354 generates the radio frequencies, clocks, and data/packet timing,

enabling it to operate using a wide selection of frequency references.

For SDIO, HSIC, and PCIe WLAN host applications, the recommended default frequency reference is a 37.4

MHz crystal. For PCIe applications, see Table 3 on page 28 for details on alternatives for the external frequency

reference. The signal characteristics for the crystal oscillator interface are also listed in Table 3.

Note: Although the fractional-N synthesizer can support alternative reference frequencies,

frequencies other than the default require support to be added in the driver, plus additional extensive

system testing. Contact Broadcom for further details.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 27

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

External Frequency Reference

For operation in SDIO and HSIC modes only, an alternative to a crystal (an external precision frequency

reference) can be used. The recommended default frequency is 52 MHz ±10 ppm, and it must meet the phase

noise requirements listed in Table 3.

If used, the external clock should be connected to the WRF_XTAL_IN pin through an external 1000 pF coupling

capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the

BCM4354 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance

variation. Power must be supplied to the WRF_XTAL_VDD1P5 pin.

Figure 5: Recommended Circuit to Use with an External Reference Clock

1000 pF

Reference

WRF_XTAL_IN

Clock

NC

WRF_XTAL_OUT

Table 3: Crystal Oscillator and External Clock—Requirements and Performance

External Frequency

Crystal^a

Reference^b,c

Parameter

Conditions/Notes

Min. Typ. Max. Min. Typ. Max. Units

Frequency

2.4G and 5G bands: IEEE

802.11ac operation, SDIO3.0,

HSIC and PCIe WLAN

interfaces

35

37.4

–

52

–

MHz

2.4G and 5G bands, IEEE

802.11ac operation, PCIe

interface alternative frequency

–

40

–

MHz

5G band: IEEE 802.11n

operation only

19

52

35

52

Ranges between 19 MHz and 52 MHz^d,e

2.4G band: IEEE 802.11n

operation, and both bands

legacy 802.11a/b/g operation

only

Frequency tolerance Without trimming

over the lifetime of the

–20

–

20

–20

–

20

ppm

equipment, including

temperature^f

Crystal load

capacitance

–

12

–

pF

ESR

60

Ω

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 28

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

External Frequency Reference

Table 3: Crystal Oscillator and External Clock—Requirements and Performance (Cont.)

External Frequency

Reference^b,c

Crystal^a

Parameter

Conditions/Notes

Min. Typ. Max. Min. Typ. Max. Units

Drive level

External crystal must be able to 200

tolerate this drive level.

–

µW

Input impedance

(WRF_XTAL_IN)

Resistive

–

30

–

100

–

kΩ

pF

V

Capacitive

7.5

–

7.5

0.2

WRF_XTAL_IN

Input low level

DC-coupled digital signal

0

–

WRF_XTAL_IN

Input high level

DC-coupled digital signal

AC-coupled analog signal

–

1.0

–

1.26

V

WRF_XTAL_IN

input voltage

400

1200 mV_p-p

(see Figure 5)

Duty cycle

37.4 MHz clock

–

40

–

50

–

60

%

Phase Noise^g

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–129 dBc/Hz

–136 dBc/Hz

–

(IEEE 802.11b/g)

Phase Noise^g

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–137 dBc/Hz

–144 dBc/Hz

(IEEE 802.11a)

Phase Noise^g

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–134 dBc/Hz

–141 dBc/Hz

(IEEE 802.11n,

2.4 GHz)

Phase Noise^g,h

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–142 dBc/Hz

–149 dBc/Hz

(IEEE 802.11n,

5 GHz)

Phase Noise^g

37.4 MHz clock at 10 kHz offset –

37.4 MHz clock at 100 kHz offset –

–

–150 dBc/Hz

–157 dBc/Hz

(IEEE 802.11ac,

5 GHz)

a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT.

b. See “External Frequency Reference” on page 28 for alternate connection methods.

c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the

reference clock frequency in MHz.

d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high.

Note that 52 MHz is not an auto–detected frequency using the LPO clock.

e. The frequency step size is approximately 80 Hz resolution.

f. It is the responsibility of the equipment designer to select oscillator components that comply with these

specifications.

g. Assumes that external clock has a flat phase noise response above 100 kHz.

h. If the reference clock frequency is <35 MHz the phase noise requirements must be tightened by an additional

2 dB.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 29

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

External 32.768 kHz Low-Power Oscillator

The BCM4354 uses a secondary low-frequency clock for Low-Power mode timing. Either the internal low-

precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is

approximately 33 kHz (± 30%) over process, voltage, and temperature, which is adequate for some

applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase

during power save mode that is incurred by the need to wake up earlier to avoid missing beacons.

Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock which meets the

requirements listed in Table 4.

Table 4: External 32.768 kHz Sleep Clock Specifications

Parameter

LPO Clock

Unit

Nominal input frequency

Frequency accuracy

Duty cycle

32.768

kHz

ppm

%

±200

30–70

Input signal amplitude

Signal type

200-3300

mV, p-p

–

Square-wave or sine-wave

Input impedance^a

> 100k

< 5

Ω

pF

Clock jitter (during initial start-up)

< 10,000

ppm

a. When power is applied or switched off.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 30

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth + FM Subsystem Overview

Section 4: Bluetooth + FM Subsystem

Overview

The Broadcom BCM4354 is a Bluetooth 4.1 + EDR-compliant, baseband processor/2.4 GHz transceiver with

an integrated FM/RDS/RBDS receiver. It features the highest level of integration and eliminates all critical

external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth plus

FM radio solution.

The BCM4354 is the optimal solution for any Bluetooth voice and/or data application that also requires an FM

radio receiver. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high-speed

UART and PCM for audio. The FM subsystem supports the HCI control interface, analog output, as well as I²S

and PCM interfaces. The BCM4354 incorporates all Bluetooth 4.1 features including Secure Simple Pairing,

Sniff Subrating, and Encryption Pause and Resume.

The BCM4354 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent

mobile phone temperature applications and the tightest integration into mobile handsets and portable devices.

It is fully compatible with any of the standard TCXO frequencies and provides full radio compatibility to operate

simultaneously with GPS, WLAN, and cellular radios.

The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability.

Features

Major Bluetooth features of the BCM4354 include:

•

Supports key features of upcoming Bluetooth standards

Fully supports Bluetooth Core Specification version 4.1 + (Enhanced Data Rate) EDR features:

– Adaptive Frequency Hopping (AFH)

– Quality of Service (QoS)

– Extended Synchronous Connections (eSCO)—Voice Connections

– Fast Connect (interlaced page and inquiry scans)

– Secure Simple Pairing (SSP)

– Sniff Subrating (SSR)

– Encryption Pause Resume (EPR)

– Extended Inquiry Response (EIR)

– Link Supervision Timeout (LST)

•

UART baud rates up to 4 Mbps

Supports all Bluetooth 4.1 packet types

Supports maximum Bluetooth data rates over HCI UART

BT supports full-speed USB 2.0-compliant interface

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 31

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Features

•

Multipoint operation with up to seven active slaves

– Maximum of seven simultaneous active ACL links

– Maximum of three simultaneous active SCO and eSCO connections with scatternet support

Trigger Broadcom fast connect (TBFC)

•

Narrowband and wideband packet loss concealment

Scatternet operation with up to four active piconets with background scan and support for scatter mode

High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and

BT_HOST_WAKE signaling (see “Host Controller Power Management” on page 37)

•

Channel quality driven data rate and packet type selection

Standard Bluetooth test modes

Extended radio and production test mode features

Full support for power savings modes

– Bluetooth clock request

– Bluetooth standard sniff

– Deep-sleep modes and software regulator shutdown

•

TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power

crystal, which can be used during power save mode for better timing accuracy.

Major FM Radio features include:

•

65 MHz to 108 MHz FM bands supported (US, Europe, and Japan)

FM subsystem control using the Bluetooth HCI interface

FM subsystem operates from reference clock inputs.

Improved audio interface capabilities with full-featured bidirectional PCM and I²S

I²S can be master or slave.

FM Receiver-Specific Features Include:

•

Excellent FM radio performance with 1 µV sensitivity for 26 dB (S+N)/N

Signal-dependent stereo/mono blending

Signal dependent soft mute

Auto search and tuning modes

Audio silence detection

RSSI, IF frequency, status indicators

RDS and RBDS demodulator and decoder with filter and buffering functions

Automatic frequency jump

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 32

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Radio

The BCM4354 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless

systems. It has been designed to provide low-power, low-cost, robust communications for applications operating

in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification

and EDR specification and meets or exceeds the requirements to provide the highest communication link quality

of service.

Transmit

The BCM4354 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated

in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path

consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also

incorporates /4–DQPSK for 2 Mbps and 8–DPSK for 3 Mbps to support EDR. The transmitter section is

compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted to provide

Bluetooth class 1 or class 2 operation.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, /4–DQPSK, and

8–DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation

characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency

tracking and bit-synchronization algorithm.

Power Amplifier

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated

design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA

combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory

harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is

integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for

spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength

indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage,

and temperature.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 33

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Radio

Receiver

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital

demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic

range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The

front-end topology with built-in out-of-band attenuation enables the BCM4354 to be used in most applications

with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated

close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by

the cellular transmit signal.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency

tracking and bit synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the BCM4354 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband,

so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver

signal strength to determine whether the transmitter should increase or decrease its output power.

Local Oscillator Generation

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum

available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during

PA operation. The BCM4354 uses an internal RF and IF loop filter.

Calibration

The BCM4354 radio transceiver features an automated calibration scheme that is fully self contained in the

radio. No user interaction is required during normal operation or during manufacturing to provide the optimal

performance. Calibration optimizes the performance of all the major blocks within the radio to within 2% of

optimal conditions, including gain and phase characteristics of filters, matching between key components, and

key gain blocks. This takes into account process variation and temperature variation. Calibration occurs

transparently during normal operation during the settling time of the hops and calibrates for temperature

variations as the device cools and heats during normal operation in its environment.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 34

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Baseband Core

Section 5: Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance

Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It

also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions,

monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages

connection status indicators, and composes and decodes HCI packets. In addition to these functions, it

independently handles HCI event types, and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability

and security of the TX/RX data before sending over the air:

•

Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data dewhitening in the receiver.

•

Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and

data whitening in the transmitter.

Bluetooth 4.1 Features

The BBC supports all Bluetooth 4.1 features, with the following benefits:

•

Dual-mode bluetooth Low Energy (BT and BLE operation)

Extended Inquiry Response (EIR): Shortens the time to retrieve the device name, specific profile, and

operating mode.

•

Encryption Pause Resume (EPR): Enables the use of Bluetooth technology in a much more secure

environment.

Sniff Subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which

subsequently extends battery life.

Secure Simple Pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no

user interaction required.

Link Supervision Time Out (LSTO): Additional commands added to HCI and Link Management Protocol

(LMP) for improved link time-out supervision.

QoS enhancements: Changes to data traffic control, which results in better link performance. Audio, human

interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data

(ED) and packet boundary flag (PBF) enhancements.

Bluetooth Low Energy

The BCM4354 supports the Bluetooth Low Energy operating mode.

Broadcom^®

October 15, 2014 • 4354-DS109-R

BROADCOM CONFIDENTIAL

Page 35

BCM4354 Data Sheet

Link Control Layer

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the

link control unit (LCU). This layer consists of the command controller that takes commands from the software,

and other controllers that are activated or configured by the command controller, to perform the link control

tasks. Each task performs a different state in the Bluetooth Link Controller.

•

Major states:

– Standby

– Connection

Substates:

– Page

•

– Page Scan

– Inquiry

– Inquiry Scan

– Sniff

Test Mode Support

The BCM4354 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth

System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced

hopping sequence.

In addition to the standard Bluetooth Test Mode, the BCM4354 also supports enhanced testing features to

simplify RF debugging and qualification and type-approval testing. These features include:

•

Fixed frequency carrier wave (unmodulated) transmission

– Simplifies some type-approval measurements (Japan)

– Aids in transmitter performance analysis

•

Fixed frequency constant receiver mode

– Receiver output directed to I/O pin

– Allows for direct BER measurements using standard RF test equipment

– Facilitates spurious emissions testing for receive mode

Fixed frequency constant transmission

•

– Eight-bit fixed pattern or PRBS-9

– Enables modulated signal measurements with standard RF test equipment

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 36

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Power Management Unit

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by

either software through power management registers or packet handling in the baseband core. The power

management functions provided by the BCM4354 are:

•

RF Power Management

Host Controller Power Management

BBC Power Management

FM Power Management

RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to

the 2.4 GHz transceiver. The transceiver then processes the power-down functions accordingly.

Host Controller Power Management

When running in UART mode, the BCM4354 may be configured so that dedicated signals are used for power

management hand-shaking between the BCM4354 and the host. The basic power saving functions supported

by those hand-shaking signals include the standard Bluetooth defined power savings modes and standby

modes of operation. Table 5 describes the power-control hand-shake signals used with the UART interface.

Table 5: Power Control Pin Description

Signal

Mapped to Pin

Type Description

BT_DEV_WAKE

BT_GPIO_0

I

Bluetooth device wake-up: Signal from the host to the

BCM4354 indicating that the host requires attention.

•

Asserted: The Bluetooth device must wake-up or remain

awake.

•

Deasserted: The Bluetooth device may sleep when sleep

criteria are met.

The polarity of this signal is software configurable and can be

asserted high or low.

BT_HOST_WAKE BT_GPIO_1

O

Host wake up. Signal from the BCM4354 to the host

indicating that the BCM4354 requires attention.

•

Asserted: host device must wake-up or remain awake.

Deasserted: host device may sleep when sleep criteria

are met.

The polarity of this signal is software configurable and can be

asserted high or low.

CLK_REQ

BT_CLK_REQ_OUT O

WL_CLK_REQ_OUT

The BCM4354 asserts CLK_REQ when Bluetooth or WLAN

wants the host to turn on the reference clock. The CLK_REQ

polarity is active-high. Add an external 100 kΩ pull-down

resistor to ensure the signal is deasserted when the

BCM4354 powers up or resets when VDDIO is present.

Note: Pad function Control Register is set to 0 for these pins. See “DC Characteristics” on page 125 for more

details.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 37

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Power Management Unit

The timing for the startup sequence is defined in Figure 6.

Figure 6: Startup Signaling Sequence

LPO

VDDIO

Host I/Os

unconfigured

Host I/Os

configured

HostResetX

T1

BT_GPIO_0

(BT_DEV_WAKE

)

BTH I/Os

unconfigured

T2

BT_REG_ON

BTH I/Os

configured

BT_GPIO_1

(BT_HOST_WAKE)

T3

Host side drives

this line low

BT_UART_CTS_N

BTH device drives this line low

indicating transport is ready

T4

BT_UART_RTS_N

CLK_REQ_OUT

T5

Driven

Pulled

Notes:



T1 is the time for Host to settle it’s IOs after a reset.

T2 is the time for Host to drive BT_REG_ON high after the Host IOs are configured.

T3 is the time for BTH (Bluetooth) device to settle its IOs after a reset and reference clock settling time has elapsed.

T4 is the time for BTH device to drive BT_UART_RTS_N low after the Host drives BT_UART_CTS_N low. This assumes the BTH device has already

completed initialization.



T5 is the time for BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. Note this pin is used for designs that use an external reference

clock source from the Host. This pin is irrelevant for Crystal reference clock based designs where the BTH device generates it’s own reference clock from

an external crystal connected to it’s oscillator circuit.



Timing diagram assumes VBAT is present.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 38

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Power Management Unit

BBC Power Management

The following are low-power operations for the BBC:

•

Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets.

Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the

BCM4354 runs on the low-power oscillator and wakes up after a predefined time period.

•

A low-power shutdown feature allows the device to be turned off while the host and any other devices in the

system remain operational. When the BCM4354 is not needed in the system, the RF and core supplies are

shut down while the I/O remains powered. This allows the BCM4354 to effectively be off while keeping the

I/O pins powered so they do not draw extra current from any other devices connected to the I/O.

During the low-power shut-down state, provided VDDIO remains applied to the BCM4354, all outputs are

tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal

operation. This is done to prevent current paths or create loading on any digital signals in the system and

enables the BCM4354 to be fully integrated in an embedded device to take full advantage of the lowest

power-saving modes.

Two BCM4354 input signals are designed to be high-impedance inputs that do not load the driving signal

even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN)

and the 32.768 kHz input (LPO). When the BCM4354 is powered on from this state, it is the same as a

normal power-up, and the device does not contain any information about its state from the time before it was

powered down.

FM Power Management

The BCM4354 FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC

subsystems. The FM subsystem power management scheme operates in conjunction with the Bluetooth RF and

BBC subsystems. The FM block does not have a low power state, it is either on or off.

Wideband Speech

The BCM4354 provides support for wideband speech (WBS) using on-chip SmartAudio technology. The

BCM4354 can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at

16 kHz (256 Kbps rate) transferred over the PCM bus.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 39

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Power Management Unit

Packet Loss Concealment

Packet Loss Concealment (PLC) improves apparent audio quality for systems with marginal link performance.

Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream.

Packet loss can be mitigated in several ways:

•

Fill in zeros.

Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets).

Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat).

These techniques cause distortion and popping in the audio stream. The BCM4354 uses a proprietary waveform

extension algorithm to provide dramatic improvement in the audio quality. Figure 7 and Figure 8 show audio

waveforms with and without Packet Loss Concealment. Broadcom PLC/BEC algorithms also support wide band

speech.

Figure 7: CVSD Decoder Output Waveform Without PLC

Packet Loss Causes Ramp-down

Figure 8: CVSD Decoder Output Waveform After Applying PLC

Audio Rate-Matching Algorithms

The BCM4354 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio

stream jitter that may be present when the rate of audio data coming from the host is not the same as the

Bluetooth or FM audio data rates.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 40

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Adaptive Frequency Hopping

Codec Encoding

The BCM4354 can support SBC and mSBC encoding and decoding for wideband speech.

Multiple Simultaneous A2DP Audio Stream

The BCM4354 has the ability to take a single audio stream and output it to multiple Bluetooth devices

simultaneously. This allows a user to share his or her music (or any audio stream) with a friend.

FM Over Bluetooth

FM Over Bluetooth enables the BCM4354 to stream data from FM over Bluetooth without requiring the host to

be awake. This can significantly extend battery life for usage cases where someone is listening to FM radio on

a Bluetooth headset.

Burst Buffer Operation

The BCM4354 has a data buffer that can buffer data being sent over the HCI and audio transports, then send

the data at an increased rate. This mode of operation allows the host to sleep for the maximum amount of time,

dramatically reducing system current consumption.

Adaptive Frequency Hopping

The BCM4354 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and

channel map selection. The link quality is determined using both RF and baseband signal processing to provide

a more accurate frequency-hop map.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 41

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Advanced Bluetooth/WLAN Coexistence

The BCM4354 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN

integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell

phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High

Fidelity BT Stereo.

Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna

applications are also supported. The BCM4354 radio architecture allows for lossless simultaneous Bluetooth

and WLAN reception for shared antenna applications. This is possible only via an integrated solution (shared

LNA and joint AGC algorithm). It has superior performance versus implementations that need to arbitrate

between Bluetooth and WLAN reception.

The BCM4354 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via

an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without

host processor involvement.

The BCM4354 also supports Transmit Power Control on the STA together with standard Bluetooth TPC to limit

mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP

transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been

implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including non-

WLAN 2.4 GHz interference).

The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information.

Fast Connection (Interlaced Page and Inquiry Scans)

The BCM4354 supports page scan and inquiry scan modes that significantly reduce the average inquiry

response and connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and

inquiry procedures.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 42

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Microprocessor and Memory Unit for Bluetooth

Section 6: Microprocessor and Memory

Unit for Bluetooth

The Bluetooth microprocessor core is based on the ARM^®Cortex-M3™ 32-bit RISC processor with embedded

ICE-RT debug and JTAG interface units. It runs software from the link control (LC) layer, up to the host controller

interface (HCI).

The ARM core is paired with a memory unit that contains 668 KB of ROM memory for program storage and boot

ROM, 200 KB of RAM for data scratchpad and patch RAM code. The internal ROM allows for flexibility during

power-on reset to enable the same device to be used in various configurations. At power-up, the lower-layer

protocol stack is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features

additions. These patches may be downloaded from the host to the BCM4354 through the UART transports. The

mechanism for downloading via UART is identical to the proven interface of the BCM4330 device.

RAM, ROM, and Patch Memory

The BCM4354 Bluetooth core has 200 KB of internal RAM which is mapped between general purpose scratch

pad memory and patch memory and 668 KB of ROM used for the lower-layer protocol stack, test mode software,

and boot ROM. The patch memory capability enables the addition of code changes for purposes of feature

additions and bug fixes to the ROM memory.

Reset

The BCM4354 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The

BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the

POR circuit is held in reset.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 43

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth Peripheral Transport Unit

Section 7: Bluetooth Peripheral Transport

Unit

SPI Interface

The BCM4354 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates

can be possible. The physical interface between the SPI master and the BCM4354 consists of the four SPI

signals (SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO) and one interrupt signal (SPI_INT). The SPI signals are

muxed onto the UART signals, see Table 6. The BCM4354 can be configured to accept active-low or active-high

polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high

SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-

endian or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented

between the SPI master and the BCM4354. The SPI_INT is required to negotiate the start of a transaction. The

SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the

largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB

and SPI_CLK. Flow control should be implemented in the higher layer protocols.

Table 6: SPI to UART Signal Mapping

SPI Signals

UART Signals

SPI_CLK

SPI_CSB

SPI_MISO

SPI_MOSI

SPI_INT

UART_CTS_N

UART_RTS_N

UART_TXD

UART_RXD

BT_DEV_WAKE

SPI/UART Transport Detection

The BT_HOST_WAKE (BT_GPIO1) pin is also used for BT transport detection. The transport detection occurs

during the power-up sequence. It selects either UART or SPI transport operation based on the following pin

state:

•

If the BT_HOST_WAKE (BT_GPIO1) pin is pulled low by an external pull-down during power-up, it selects

the SPI transport interface.

•

If the BT_HOST_WAKE (BT_GPIO1) pin is not pulled low externally during power-up, then the default

internal pull-up is detected as a high and it selects the UART transport interface.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 44

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

The BCM4354 supports two independent PCM interfaces that share the pins with the I²S interfaces. The PCM

Interface on the BCM4354 can connect to linear PCM Codec devices in master or slave mode. In master mode,

the BCM4354 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided

by another master on the PCM interface and are inputs to the BCM4354.

The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI

commands.

Slot Mapping

The BCM4354 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM

interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting

scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of

slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number

of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO

channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to

allow other devices to share the same PCM interface signals. The data output driver tristates its output after the

falling edge of the PCM clock during the last bit of the slot.

Frame Synchronization

The BCM4354 supports both short- and long-frame synchronization in both master and slave modes. In short-

frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate

that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks

for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge

of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse

at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first

bit of the first slot.

Data Formatting

The BCM4354 may be configured to generate and accept several different data formats. For conventional

narrowband speech mode, the BCM4354 uses 13 of the 16 bits in each PCM frame. The location and order of

these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits

are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The

default format is 13-bit 2’s complement data, left justified, and clocked MSB first.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 45

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Wideband Speech Support

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are

transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured

in master mode for a 4 kHz sync rate with 16-bit samples, resulting in a 64 Kbps bit rate. The BCM4354 also

supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit

data at 16 kHz (256 Kbps rate) is transferred over the PCM bus.

Multiplexed Bluetooth and FM Over PCM

In this mode of operation, the BCM4354 multiplexes both FM and Bluetooth audio PCM channels over the same

interface, reducing the number of required I/Os. This mode of operation is initiated through an HCI command

from the host. The format of the data stream consists of three channels: a Bluetooth channel followed by two

FM channels (audio left and right). In this mode of operation, the bus data rate only supports 48 kHz operation

per channel with 16 bits sent for each channel. This is done to allow the low data rate Bluetooth data to coexist

in the same interface as the higher speed I²S data. To accomplish this, the Bluetooth data is repeated six times

for 8 kHz data and three times for 16 kHz data. An initial sync pulse on the PCM_SYNC line is used to indicate

the beginning of the frame.

To support multiple Bluetooth audio streams within the Bluetooth channel, both 16 kHz and 8 kHz streams can

be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 9 shows

the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate

additional SCO channels, the transport clock speed is increased. To change between modes of operation, the

transport must be halted and restarted in the new configuration.

Figure 9: Functional Multiplex Data Diagram

1 Frame

BT SCO 1 Rx

BT SCO 1 Tx

BT SCO 2 Rx

BT SCO 2 Tx

BT SCO 3 Rx

FM Right

FM Left

PCM_OUT

PCM_IN

BT SCO 3 Tx

PCM_SYNC

PCM_CLK

CLK

16 bits per SCO frame

16 bits per frame

Each SCO channel duplicates the data 6 times. Each WBS

frame duplicates the data three times per frame

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 46

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Burst PCM Mode

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty

cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to

24 MHz. This mode of operation is initiated with an HCI command from the host.

PCM Interface Timing

Short Frame Sync, Master Mode

Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM _SYNC

PCM _OUT

8

HIGH IMPEDANCE

5

7

6

PCM_IN

Table 7: PCM Interface Timing Specifications (Short Frame Sync, Master Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

41

0

–

ns

25

–

ns

0

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 47

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Short Frame Sync, Slave Mode

Figure 11: PCM Timing Diagram (Short Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM_SYNC

PCM_OUT

9

HIGH IMPEDANCE

8

6

7

PCM_IN

Table 8: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

41

8

–

ns

–

ns

8

–

ns

0

25

–

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 48

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Long Frame Sync, Master Mode

Figure 12: PCM Timing Diagram (Long Frame Sync, Master Mode)

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

HIGH IMPEDANCE

7

Bit 0

Bit 1

5

6

Bit 0

PCM_IN

Table 9: PCM Interface Timing Specifications (Long Frame Sync, Master Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

41

0

–

ns

25

–

ns

0

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 49

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Long Frame Sync, Slave Mode

Figure 13: PCM Timing Diagram (Long Frame Sync, Slave Mode)

1

2

3

PCM_BCLK

4

5

PCM _SYNC

PCM_OUT

9

Bit 0

HIGH IMPEDANCE

Bit 1

6

7

8

PCM_IN

Bit 1

Table 10: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

8

9

PCM bit clock frequency

–

12

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_OUT delay

PCM_IN setup

41

8

–

ns

–

ns

8

–

ns

0

25

–

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 50

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Short Frame Sync, Burst Mode

Figure 14: PCM Burst Mode Timing (Receive Only, Short Frame Sync)

1

2

3

PCM_BCLK

PCM_SYNC

4

5

6

7

PCM_IN

Table 11: PCM Burst Mode (Receive Only, Short Frame Sync)

Ref No. Characteristics

Minimum Typical Maximum Unit

1

2

3

4

5

6

7

PCM bit clock frequency

–

24

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

20.8

8

–

ns

–

ns

8

–

ns

8

–

ns

PCM_IN hold

8

–

ns

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 51

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCM Interface

Long Frame Sync, Burst Mode

Figure 15: PCM Burst Mode Timing (Receive Only, Long Frame Sync)

1

3

2

PCM_BCLK

PCM_SYNC

4

5

6

7

PCM_IN

Bit 0

Bit 1

Table 12: PCM Burst Mode (Receive Only, Long Frame Sync)

Ref No. Characteristics Minimum Typical Maximum Unit

1

2

3

4

5

6

7

PCM bit clock frequency

–

24

–

MHz

ns

PCM bit clock LOW

PCM bit clock HIGH

PCM_SYNC setup

PCM_SYNC hold

PCM_IN setup

20.8

8

–

ns

–

ns

8

–

ns

8

–

ns

PCM_IN hold

8

–

ns

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 52

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

USB Interface

Features

The following USB interface features are supported:

•

USB Protocol, Revision 2.0, full-speed (12 Mbps) compliant including the hub

Optional hub compound device with up to three device cores internal to device

Bus or self-power, dynamic configuration for the hub

Global and selective suspend and resume with remote wake-up

Bluetooth HCI

HID, DFU, UHE (proprietary method to emulate an HID device at system bootup)

Integrated detach resistor

Operation

The BCM4354 can be configured to boot up as either a single USB peripheral or a USB hub with several USB

peripherals attached. As a single peripheral, the host detects a single USB Bluetooth device. In hub mode, the

host detects a hub with one to three of the ports already connected to USB devices (see Figure 16).

Figure 16: USB Compounded Device Configuration

Host

USB Compounded Device

Hub Controller

USB Device 1

HID Keyboard

USB Device 2

HID Mouse

USB Device 3

Bluetooth

Depending on the desired hub mode configuration, the BCM4354 can boot up showing the three ports

connected to logical USB devices internal to the BCM4354: a generic Bluetooth device, a mouse, and a

keyboard. In this mode, the mouse and keyboard are emulated devices, since they connect to real HID devices

via a Bluetooth link. The Bluetooth link to these HID devices is hidden from the USB host. To the host, the mouse

and/or keyboard appear to be directly connected to the USB port. This Broadcom proprietary architecture is

called USB HID Emulation (UHE).

The USB device, configuration, and string descriptors are fully programmable, allowing manufacturers to

customize the descriptors, including vendor and product IDs, the BCM4354 uses to identify itself on the USB

port. To make custom USB descriptor information available at boot time, stored it in external NVRAM.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 53

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

USB Interface

Despite the mode of operation (single peripheral or hub), the Bluetooth device is configured to include the

following interfaces:

Interface 0

Interface 1

Interface 2

Contains a Control endpoint (Endpoint 0x00) for HCI commands, a Bulk In Endpoint (Endpoint

0x82) for receiving ACL data, a Bulk Out Endpoint (Endpoint 0x02) for transmitting ACL data,

and an Interrupt Endpoint (Endpoint 0x81) for HCI events.

Contains Isochronous In and Out endpoints (Endpoints 0x83 and 0x03) for SCO traffic. Several

alternate Interface 1 settings are available for reserving the proper bandwidth of isochronous

data (depending on the application).

Contains Bulk In and Bulk Out endpoints (Endpoints 0x84 and 0x04) used for proprietary testing

and debugging purposes. These endpoints can be ignored during normal operation.

USB Hub and UHE Support

The BCM4354 supports the USB hub and device model (USB, Revision 2.0, full-speed compliant). Optional

mouse and keyboard devices utilize Broadcom’s proprietary USB HID Emulation (UHE) architecture, which

allows these devices appear as standalone HID devices even though connected through a Bluetooth link.

The presence of UHE devices requires the hub to be enabled. The BCM4354 cannot appear as a single

keyboard or a single mouse device without the hub. Once either mouse or keyboard UHE device is enabled, the

hub must also be enabled.

When the hub is enabled, the BCM4354 handles all standard USB functions for the following devices:

•

HID keyboard

HID mouse

Bluetooth

All hub and device descriptors are firmware-programmable. This USB compound device configuration (see

Figure 16 on page 53) supports up to three downstream ports. This configuration can also be programmed to a

single USB device core. The device automatically detects activity on the USB interface when connected.

Therefore, no special configuration is needed to select HCI as the transport.

The hub’s downstream port definition is as follows:

•

Port 1 USB lite device core (for HID applications)

Port 2 USB lite device core (for HID applications)

Port 3 USB full device core (for Bluetooth applications)

When operating in hub mode, all three internal devices do not have to be enabled. Each internal USB device

can be optionally enabled. The configuration record in NVRAM determines which devices are present.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 54

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

USB Interface

USB Full-Speed Timing

Table 13 shows timing specifications for the VDD_USB = 3.3V, V_SS= 0V, and T_A= 0°C to 85°C operating

temperature range.

Table 13: USB Full-Speed Timing Specifications

Reference Characteristics

Minimum

Maximum

Unit

1

2

3

4

Transition rise time

Transition fall time

4

20

ns

4

20

ns

Rise/fall timing matching

Full-speed data rate

90

111

%

12 – 0.25%

12 + 0.25%

Mb/s

Figure 17: USB Full-Speed Timing

2

1

D+

D-

90%

V_CRS

10%

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 55

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

UART Interface

The BCM4354 shares a single UART for Bluetooth and FM. The UART is a standard 4-wire interface (RX, TX,

RTS, and CTS) with adjustable baud rates from 9600 bps to 4.1 Mbps. The interface features an automatic baud

rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through

a vendor-specific UART HCI command.

UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is

conducted through the AHB interface through either DMA or the CPU. The UART supports the Bluetooth 4.1

UART HCI specification: H4, a custom Extended H4, and H5. The default baud rate is 115.2 Kbaud.

The UART supports the 3-wire H5 UART transport, as described in the Bluetooth specification (“Three-wire

UART Transport Layer”). Compared to H4, the H5 UART transport reduces the number of signal lines required

by eliminating the CTS and RTS signals.

The BCM4354 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line

Input Protocol (SLIP). It can also perform wake-on activity. For example, activity on the RX or CTS inputs can

wake the chip from a sleep state.

Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic

baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate

during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust

the contents of the baud rate registers. The BCM4354 UARTs operate correctly with the host UART as long as

the combined baud rate error of the two devices is within ±2%.

Table 14: Example of Common Baud Rates

Desired Rate

Actual Rate

Error (%)

4000000

3692000

3000000

2000000

1500000

1444444

921600

460800

230400

115200

57600

4000000

3692308

3000000

2000000

1500000

1454544

923077

461538

230796

115385

57692

0.00

0.01

0.00

0.70

0.16

0.17

0.16

0.00

0.16

0.00

0.16

0.00

38400

28800

28846

19200

14400

14423

9600

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 56

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

UART Interface

Figure 18: UART Timing

UART_CTS_N

UART_TXD

1

2

Midpoint of STOP bit

UART_RXD

3

UART_RTS_N

Table 15: UART Timing Specifications

Ref No. Characteristics

Minimum Typical

Maximum Unit

1

2

3

Delay time, UART_CTS_N low to UART_TXD

valid

–

1.5

0.5

Bit periods

Setup time, UART_CTS_N high before midpoint of –

stop bit

–

Bit periods

Delay time, midpoint of stop bit to UART_RTS_N –

high

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 57

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

I²S Interface

The BCM4354 supports two independent I²S digital audio ports: one for Bluetooth audio, and one for high-

fidelity FM audio. The I²S interface for FM audio supports both master and slave modes. The I²S signals are:

•

I²S clock: BT_I2S_CLK

I²S Word Select: BT_I2S_WS

I²S Data Out: BT_I2S_DO

I²S Data In: BT_I2S_DI

BT_I2S_CLK and BT_I2S_WS become outputs in master mode and inputs in slave mode, whereas BT_I2S_DO

always stays as an output. The channel word length is 16 bits, and the data is justified so that the MSB of the

left-channel data is aligned with the MSB of the I²S bus, in accord with the I²S specification. The MSB of each

data word is transmitted one bit clock cycle after the BT_I2S_WS transition, synchronous with the falling edge

of the bit clock. Left-channel data is transmitted when IBT_I2S_WS is low, and right-channel data is transmitted

when BT_I2S_WS is high. Data bits sent by the BCM4354 are synchronized with the falling edge of

BT_I2S_CLK and should be sampled by the receiver on the rising edge of BT_I2S_CLK.

The clock rate in master mode is either of the following:

48 kHz x 32 bits per frame = 1.536 MHz

48 kHz x 50 bits per frame = 2.400 MHz

The master clock is generated from the input reference clock using a N/M clock divider.

In the slave mode, any clock rate is supported to a maximum of 3.072 MHz.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 58

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

I²S Interface

2

I S Timing

Note: Timing values specified in Table 16 are relative to high and low threshold levels.

Table 16: Timing for I²S Transmitters and Receivers

Transmitter

Lower LImit Upper Limit

Receiver

Lower Limit Upper Limit

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Notes

a

Clock Period T

T_tr

–

T_r

–

Master Mode: Clock generated by transmitter or receiver

b

HIGH t_HC

LOWt_LC

0.35T_tr

–

0.35T_tr

–

Slave Mode: Clock accepted by transmitter or receiver

c

d

HIGH t_HC

–

0.35T_tr

–

0.35T_tr

–

LOW t_LC

Rise time t_RC

0.15T_tr

Transmitter

Delay t_dtr

e

d

–

0

–

0.8T

–

Hold time t_htr

Receiver

f

Setup time t_sr

Hold time t_hr

–

0.2T_r

0

–

a. The system clock period T must be greater than T_trand T_rbecause both the transmitter and receiver have to be

able to handle the data transfer rate.

b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space

ratio. For this reason, t_HCand t_LCare specified with respect to T.

c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that

they can detect the signal. So long as the minimum periods are greater than 0.35T_r, any clock that meets the

requirements can be used.

d. Because the delay (t_dtr) and the maximum transmitter speed (defined by T_tr) are related, a fast transmitter driven

by a slow clock edge can result in t_dtrnot exceeding t_RCwhich means t_htrbecomes zero or negative. Therefore,

the transmitter has to guarantee that t_htris greater than or equal to zero, so long as the clock rise-time t_RCis not

more than t_RCmax, where t_RCmaxis not less than 0.15T_tr.

e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the

clock signal and T, always giving the receiver sufficient setup time.

f. The data setup and hold time must not be less than the specified receiver setup and hold time.

Note: The time periods specified in Figure 19 and Figure 20 are defined by the transmitter speed. The

receiver specifications must match transmitter performance.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 59

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

I²S Interface

Figure 19: I²S Transmitter Timing

T

t_RC

*

t_LC> 0.35T

t_HC> 0.35T

V_H= 2.0V

V_L= 0.8V

SCK

t_htr> 0

t_otr< 0.8T

SD and WS

T = Clock period

T

_tr= Minimum allowed clock period for transmitter

T = T_tr

* t_RCis only relevant for transmitters in slave mode.

Figure 20: I²S Receiver Timing

T

t_LC> 0.35T

t_HC> 0.35

V_H= 2.0V

V_L= 0.8V

SCK

t_sr> 0.2T

t_hr> 0

SD and WS

T = Clock period

T_r= Minimum allowed clock period for transmitter

T > T_r

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 60

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

FM Receiver Subsystem

Section 8: FM Receiver Subsystem

FM Radio

The BCM4354 includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from

65 MHz to 108 MHz. The receiver is controlled through commands on the HCI. FM received audio is available

as stereo or in digital form through I²S or PCM. The FM radio operates from the external clock reference.

Digital FM Audio Interfaces

The FM audio can be transmitted via the shared PCM and I²S pins, and the sampling rate is programmable.

The BCM4354 supports a three-wire PCM or I²S audio interface in either master or slave configuration. The

master or slave configuration is selected using vendor specific commands over the HCI interface. In addition,

multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master mode, the clock

rate is either of the following:

•

48 kHz × 32 bits per frame = 1.536 MHz

48 kHz × 50 bits per frame = 2.400 MHz

In slave mode, any clock rate is supported up to a maximum of 3.072 MHz.

FM Over Bluetooth

The BCM4354 can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS,

and A2DP. In all of the above modes, once the link has been set up, the host processor can enter sleep mode

while the BCM4354 continues to stream FM audio to the remote Bluetooth device, allowing the system current

consumption to be minimized.

eSCO

In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is then sent through

the Bluetooth eSCO link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections

must be used to transport stereo.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 61

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Wide Band Speech Link

In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is then sent through

the Bluetooth wideband speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice

connections must be used to transport stereo.

A2DP

In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a

remote Bluetooth device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP

“lite” stack is implemented in the BCM4354 to support this use case, which eliminates the need to route the SBC-

encoded audio back to the host to create the A2DP packets.

Autotune and Search Algorithms

The BCM4354 supports a number of FM search and tune functions that allows the host to implement many

convenient user functions, which are accessed through the Broadcom FM stack.

•

Tune to Play: Allows the FM receiver to be programmed to a specific frequency.

Search for SNR > Threshold: Checks the power level of the available channel and the estimated SNR of

the channel to help achieve precise control of the expected sound quality for the selected FM channel.

Specifically, the host can adjust its SNR requirements to retrieve a signal with a specific sound quality, or

adjust this to return the weakest channels.

•

Alternate Frequency Jump: Allows the FM receiver to automatically jump to an alternate FM channel that

carries the same information, but has a better SNR. For example, when traveling, a user may pass through

a region where a number of channels carry the same station. When the user passes from one area to the

next, the FM receiver can automatically switch to another channel with a stronger signal to spare the user

from having to manually change the channel to continue listening to the same station.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 62

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Audio Features

A number of features are implemented in the BCM4354 to provide the best possible audio experience for the

user.

•

Mono/Stereo Blend or Switch: The BCM4354 provides automatic control of the stereo or mono settings

based on the FM signal carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio

SNR based on the FM channel condition. Two modes of operation are supported:

– Blend: In this mode, fine control of stereo separation is used to achieve optimal audio quality over a

wide range of input C/N. The amount of separation is fully programmable. In Figure 21, the separation is

programmed to maintain a minimum 50 dB SNR across the blend range.

– Extended blend: In this mode, stereo separation is maximized across a wide range of input CNR.

Broadcom static suppression typically gives a static-free user experience to within 3 dB of ultimate

sensitivity.

Figure 21: Example Blend/Switch Usage

– Switch: In this mode, the audio switches from full stereo to full mono at a predetermined level to

maintain optimal audio quality. The stereo-to-mono switch point and the mono-to-stereo switch points

are fully programmable to provide the desired amount of audio SNR. In Figure 22, the switch point is

programmed to switch to mono to maintain a 40 dB SNR.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 63

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Audio Features

Figure 22: Example Blend/Switch Separation

•

Soft Mute: Improves the user experience by dynamically muting the output audio proportionate to the FM

signal C/N. This prevents the user from being assaulted with a blast of static. The mute characteristic is

fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic

is shown in Figure 23.

Figure 23: Example Soft Mute Characteristic

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 64

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

RDS/RBDS

•

High Cut: A programmable high-cut filter is provided to reduce the amount of high-frequency noise caused

by static in the output audio signal. Like the soft mute circuit, it is fully programmable to allow for any

amount of high cut based on the FM signal C/N.

Audio Pause Detect: The FM receiver monitors the magnitude of the audio signal and notifies the host

through an interrupt when the magnitude of the signal has fallen below the threshold set for a

programmable period. This feature can be used to provide alternate frequency jumps during periods of

silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause

detection block to provide more robust presence-to-silence detection and silence-to-presence detection.

•

Automatic Antenna Tuning: The BCM4354 has an on-chip automatic antenna tuning network. When used

with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching

component to obtain the highest signal strength for the desired frequency. The high-Q nature of this

matching network simultaneously provides out-of-band blocking protection as well as a reduction of

radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external

wire antennas.

RDS/RBDS

The BCM4354 integrates a RDS/RBDS modem and codec, the decoder includes programmable filtering and

buffering functions, and the encoder includes the option to encode messages to PS or RT frame format with

programmable scrolling in PS mode. The RDS/RBDS data can be read out in receive mode or delivered in

transmit mode through either the HCI interface.

In addition, the RDS/RBDS functionality supports the following:

Receive

•

Block decoding, error correction and synchronization

Flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and

loss of sync. (It is possible to set up the BCM4354 such that synch is achieved when a minimum of two

good blocks (error free) are decoded in sequence. The number of good blocks required for sync is

programmable.)

•

Storage capability up to 126 blocks of RDS data

Full or partial block B match detect and interrupt to host

Audio pause detection with programmable parameters

Program Identification (PI) code detection and interrupt to host

Automatic frequency jump

Block E filtering

Soft mute

Signal dependent mono/stereo blend

Programmable pre-emphasis

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 65

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN Global Functions

Section 9: WLAN Global Functions

WLAN CPU and Memory Subsystem

The BCM4354 WLAN section includes an integrated ARM Cortex-R4™ 32-bit processor with internal RAM and

ROM. The ARM Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and low-

cost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response

features. Delivering a performance gain of more than 30% over the ARM7TDMI® processor, the ARM Cortex-

R4 processor implements the ARM v7-R architecture with support for the Thumb^®-2 instruction set.

At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available,

outperforming 8- and 16-bit devices on MIPS/µW.

Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin

overhead, and reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode

and System buses), integrated sleep modes, and extensive debug features including real time trace of program

execution.

On-chip memory for the CPU includes 768 KB SRAM and 640 KB ROM.

One-Time Programmable Memory

Various hardware configuration parameters may be stored in an internal One-Time Programmable (OTP)

memory, which is read by the system software after device reset. In addition, customer-specific parameters,

including the system vendor ID and the MAC address can be stored, depending on the specific board design.

Up to 484 bytes of user-accessible OTP are available.

The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be

reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with

the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively

program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle.

Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is

provided with the reference board design package.

GPIO Interface

The BCM4354 has 11 general-purpose I/O (GPIO) pins in the WLAN section that can be used to connect to

various external devices.

Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either

input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other

functions, see Table 26: “GPIO Alternative Signal Functions,” on page 120.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 66

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

External Coexistence Interface

An external handshake interface is available to enable signaling between the device and an external co-located

wireless device, such as GPS, or LTE, to manage wireless medium sharing for optimal performance.

Figure 24 and Figure 25 on page 67 show the LTE coexistence interface (including UART) for each BCM4354

package type. See Table 26: “GPIO Alternative Signal Functions,” on page 120 for further details on multiplexed

signals, such as the GPIO pins.

See Table 15: “UART Timing Specifications,” on page 57 for the UART baud rate.

Figure 24: Broadcom GCI Mode LTE Coexistence Interface

SECI_OUT

UART_IN

WLAN

SECI_IN

UART_OUT

GCI

BTFM

BCM4354

LTE/IC

Notes:

 OR’ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by

setting the GPIO mask registers appropriately.

 SECI_OUT and SECI_IN are multiplexed on the GPIOs.

Figure 25: Legacy 3-Wire LTE Coexistence Interface

GCI_GPIO_2

WCN_PRIORITY

WLAN

GCI_GPIO_1

GCI

MWS_RX, LTE_PRIORITY

LTE_FRAME_SYNC

GCI_GPIO_0

BT/FM

BCM4354

LTE/IC

Note: OR’ing to generate WCN_PRIORITY FOR ERCX_TXCONF or BT_RX_PRIORITY is achieved by

setting the GPIO mask registers appropriately.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 67

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

UART Interface

One 2-wire UART interface can be enabled by software as an alternate function on GPIO pins. Refer to

Table 26: “GPIO Alternative Signal Functions,” on page 120. Provided primarily for debugging during

development, this UART enables the BCM4354 to operate as RS-232 data termination equipment (DTE) for

exchanging and managing data with other serial devices. It is compatible with the industry standard 16550

UART, and provides a FIFO size of 64 × 8 in each direction.

JTAG Interface

The BCM4354 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and

PCB assembly testing during manufacturing. In addition, the JTAG interface allows Broadcom to assist

customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is

highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs.

Refer to Table 26: “GPIO Alternative Signal Functions,” on page 120 for JTAG pin assignments.

SPROM Interface

Various hardware configuration parameters may be stored in an external SPROM instead of the OTP. The

SPROM is read by system software after device reset. In addition, depending on the board design, customer-

specific parameters may be stored in SPROM.

The four SPROM control signals —SPROM_CS, SPROM_CLK, SPROM_MI, and SPROM_MO are

multiplexed on the SDIO interface (see Table 26: “GPIO Alternative Signal Functions,” on page 120 for

additional details). By default, the SPROM interface supports 2 kbit serial SPROMs, and it can also support

4 kbit and 16 kbit serial SPROMs by using the appropriate strapping option.

SFLASH Interface

For use only when the HSIC interface mode is selected, an interface to external SFLASH is available.

The four SFLASH control signals —SFLASH_CS#, SFLASH_CLK, SFLASH_MI, and SFLASH_MO are

multiplexed on the SDIO interface (see Table 26: “GPIO Alternative Signal Functions,” on page 120 for

additional details).

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 68

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN Host Interfaces

Section 10: WLAN Host Interfaces

SDIO v3.0

All three package options of the BCM4354 WLAN section provide support for SDIO version 3.0, including the

new UHS-I modes:

•

DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).

HS: High-speed up to 50 MHz (3.3V signaling).

SDR12: SDR up to 25 MHz (1.8V signaling).

SDR25: SDR up to 50 MHz (1.8V signaling).

SDR50: SDR up to 100 MHz (1.8V signaling).

SDR104: SDR up to 208 MHz (1.8V signaling)

DDR50: DDR up to 50 MHz (1.8V signaling).

Note: The BCM4354 is backward compatible with SDIO v2.0 host interfaces.

The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an

interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks

from within the device is also provided. SDIO mode is enabled by strapping options. Refer to Table 23 on

page 119 WLAN GPIO Functions and Strapping Options.

The following three functions are supported:

•

Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B)

Function 1 Backplane Function to access the internal system-on-chip (SoC) address space

(max. BlockSize/ByteCount = 64B)

•

Function 2 WLAN Function for efficient WLAN packet transfer through DMA

(max. BlockSize/ByteCount = 512B)

SDIO Pins

Table 17: SDIO Pin Descriptions

SD 4-Bit Mode

SD 1-Bit Mode

DATA0

DATA1

DATA2

DATA3

CLK

Data line 0

DATA Data line

Data line 1 or Interrupt IRQ

Data line 2 or Read Wait RW

Interrupt

Read Wait

Not used

Clock

Data line 3

Clock

N/C

CLK

CMD

Command line

CMD Command line

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 69

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

HSIC Interface

Figure 26: Signal Connections to SDIO Host (SD 4-Bit Mode)

CLK

BCM4354

CMD

SD Host

DAT[3:0]

Figure 27: Signal Connections to SDIO Host (SD 1-Bit Mode)

CLK

CMD

BCM4354

DATA

IRQ

SD Host

RW

Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on

the four DATA lines and the CMD line. This requirement must be met during all operating states either

through the use of external pull-up resistors or through proper programming of the SDIO host’s internal

pull-ups.

HSIC Interface

As an alternative to SDIO, an HSIC host interface can be enabled using the strapping option pins

strap_host_ifc_[3:1]. HSIC is a simplified derivative of the USB2.0 interface designed to replace a standard USB

PHY and cable for short distances (up to 10 cm) on board point-to-point connections. Using two signals, a

bidirectional data strobe (STROBE) and a bidirectional DDR data signal (DATA), it provides high-speed serial

480 Mbps data transfers that are 100% host driver compatible with traditional USB 2.0 cable-connected

topologies.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 70

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCI Express Interface

Figure 28 shows the blocks in the HSIC device core.

Key features of HSIC include:

•

High-speed 480 Mbps data rate

Source-synchronous serial interface using 1.2V LVCMOS signal levels

No power consumed except when a data transfer is in progress

Maximum trace length of 10 cm.

No Plug-n-Play support, no hot attach/removal

Figure 28: HSIC Device Block Diagram

32-Bit On-Chip Communication System

DMA Engines

F I O s F T X

F I F T O X

s O F I F T X

F I O s F T X

F I F T O X

s

RX FIFO

TX FIFOs

Endpoint Management Unit

USB 2.0 Protocol Engine

HSIC PHY

Strobe

Data

PCI Express Interface

The PCI Express (PCIe™) core on the BCM4354 is a high-performance serial I/O interconnect that is protocol

compliant and electrically compatible with the PCI Express Base Specification v3.0 running at Gen1 speeds.

This core contains all the necessary blocks, including logical and electrical functional subblocks to perform PCIe

functionality and maintain high-speed links, using existing PCI system configuration software implementations

without modification.

Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as

shown in Figure 29. A configuration or link management block is provided for enumerating the PCIe

configuration space and supporting generation and reception of System Management Messages by

communicating with PCIe layers.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 71

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCI Express Interface

Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication

between the host and BCM4354 device. The transmit side processes outbound packets whereas the receive

side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for

transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to

indicate the packet type and any other optional fields.

Figure 29: PCI Express Layer Model

HW/SW Interface

Transaction

Layer

Transaction

Layer

Data Link

Layer

Data Link

Layer

Physical Layer

Logical Subblock

Electrical Subblock

TX

RX

TX

RX

Transaction Layer Interface

The PCIe core employs a packet-based protocol to transfer data between the host and BCM4354 device,

delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer. The

Transaction layer is primarily responsible for assembly and disassembly of Transaction Layer Packets (TLPs).

TLP structure contains header, data payload, and End-to-End CRC (ECRC) fields, which are used to

communicate transactions, such as read and write requests and other events.

A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication

between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries.

Data Link Layer

The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its

primary responsibility is to provide reliable, efficient mechanism for the exchange of TLPs between two directly

connected components on the link. Services provided by the data link layer include data exchange, initialization,

error detection and correction, and retry services.

Data Link Layer Packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the

mechanism used to transfer link management information between data link layers of the two directly connected

components on the link, including TLP acknowledgement, power management, and flow control.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 72

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCI Express Interface

Physical Layer

The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed

signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks.

Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between

the host and BCM4354 device. The transmit section prepares outgoing information passed from the data link

layer for transmission, and the receiver section identifies and prepares received information before passing it to

the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a

specific format.

Logical Subblock

The logical sub block primary functions are to prepare outgoing data from the data link layer for transmission

and identify received data before passing it to the data link layer.

Scrambler/Descrambler

This PCIe PHY component generates pseudo-random sequence for scrambling of data bytes and the idle

sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive

side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and

recovery for testing and debugging purposes.

8B/10B Encoder/Decoder

The PCIe core on the BCM4354 uses an 8b/10b encoder/decoder scheme to provide DC balancing,

synchronizing clock and data recovery, and error detection. The transmission code is specified in the ANSI

X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4.

Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a

6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to

encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are

concatenated to form a 10-bit symbol, which is then transmitted serially. Special Symbols are used for link

management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.

Elastic FIFO

An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock

domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a

result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively

adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique

reduces the elastic FIFO size and the average receiver latency by half.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 73

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCI Express Interface

Electrical Subblock

The high-speed signals utilize the Common Mode Logic (CML) signaling interface with on-chip termination and

de-emphasis for best-in-class signal integrity. A de-emphasis technique is employed to reduce the effects of

Intersymbol Interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case

channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to

receive data with acceptable Bit-Error Rate (BER).

To further minimize ISI, multiple bits of the same polarity that are output in succession are de-emphasized.

Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for

maximum interoperability while minimizing the complexity of controlling the de-emphasis values. The high-

speed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the

receiver. The range of AC capacitance allowed is 75 nF to 200 nF.

Configuration Space

The PCIe function in the BCM4354 implements the configuration space as defined in the PCI Express Base

Specification v3.0.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 74

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Wireless LAN MAC and PHY

Section 11: Wireless LAN MAC and PHY

IEEE 802.11ac Draft MAC

The BCM4354 WLAN MAC is designed to support high-throughput operation with low-power consumption. It

does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over

both networks. In addition, several power saving modes have been implemented that allow the MAC to consume

very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC

is shown in Figure 30.

The following sections provide an overview of the important modules in the MAC.

Figure 30: WLAN MAC Architecture

Embedded CPU Interface

Host Registers, DMA Engines

TX-FIFO

32 KB

RX-FIFO

10 KB

PSM

PMQ

PSM

UCODE

Memory

IFS

Backoff, BTCX

WEP

TKIP, AES, WAPI

TSF

SHM

BUS

IHR

NAV

BUS

Shared Memory

6 KB

RXE

RX A-MPDU

TXE

TX A-MPDU

EXT- IHR

MAC-PHY Interface

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 75

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

IEEE 802.11ac Draft MAC

The BCM4354 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base

standard, and amended by IEEE 802.11n. The key MAC features include:

•

Enhanced MAC for supporting IEEE 802.11ac Draft features

Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT)

Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and

multiphase PSMP operation

•

Support for immediate ACK and Block-ACK policies

Interframe space timing support, including RIFS

Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges

Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification

Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon

transmission time (TBTT) generation in hardware

•

Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key

management

•

Support for coexistence with Bluetooth and other external radios

Programmable independent basic service set (IBSS) or infrastructure basic service set functionality

Statistics counters for MIB support

PSM

The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control

to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for

flow control operations, which are predominant in implementations of communication protocols. The instruction

set and fundamental operations are simple and general, which allows algorithms to be optimized until very late

in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications.

The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for

instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the

SHM bus). The PSM also uses a scratchpad memory (similar to a register bank) to store frequently accessed

and temporary variables.

The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers

(IHR). These IHRs are co-located with the hardware functions they control, and are accessed by the PSM via

the IHR bus.

The PSM fetches instructions from the microcode memory using an address determined by the program

counter, instruction literal, or a program stack. For ALU operations the operands are obtained from shared

memory, scratchpad, IHRs, or instruction literals, and the results are written into the shared memory, scratchpad,

or IHRs.

There are two basic branch instructions: conditional branches and ALU based branches. To better support the

many decision points in the IEEE 802.11 algorithms, branches can depend on either a readily available signals

from the hardware modules (branch condition signals are available to the PSM without polling the IHRs), or on

the results of ALU operations.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 76

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

IEEE 802.11ac Draft MAC

WEP

The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the

encryption and decryption, and MIC computation and verification. The accelerators implement the following

cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP.

The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to

be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the

TXE to encrypt and compute the MIC on transmit frames, and the RXE to decrypt and verify the MIC on receive

frames.

TXE

The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to

store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the

frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms.

The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical

queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel

access information from the IFS module to schedule a queue from which the next frame is transmitted. Once

the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from

the IFS module.

The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for

transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad

delimiters as needed.

RXE

The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to

drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with

the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO.

The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames

based on several criteria such as receiver address, BSSID, and certain frame types.

The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers,

and disaggregate them into component MPDUS.

IFS

The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also

contains multiple backoff engines required to support prioritized access to the medium as specified by WMM.

The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by

the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this

information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a

TXOP).

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 77

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

IEEE 802.11ac Draft MAC

The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine

whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified,

so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the

same time, the hardware resolves the conflict based on policies provided by the PSM.

The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating

under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A

sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over

which the MAC remains in this suspended state. Once the timer expires the MAC is restored to its functional

state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF is synchronized to

the network.

The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions.

TSF

The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the

target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of

adopting timestamps received from beacon and probe response frames in order to maintain synchronization

with the network.

The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such

as uplink and downlink transmission times used in PSMP.

NAV

The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed

through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms

specified in the standard.

The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based

on received frames. This timing information is provided to the IFS module, which uses it as a virtual carrier-

sense indication.

MAC-PHY Interface

The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition,

there is an programming interface, which can be controlled either by the host or the PSM to configure and control

the PHY.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 78

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

IEEE 802.11ac Draft PHY

The BCM4354 WLAN Digital PHY (see Figure 31 on page 80) is designed to comply with IEEE 802.11ac Draft

and IEEE 802.11a/b/g/n dual-stream specifications to provide wireless LAN connectivity supporting data rates

from 1 Mbps to 866.7 Mbps for low-power, high-performance handheld applications.

The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other

impairments. It incorporates optimized implementations of the filters, FFT and Viterbi decoder algorithms.

Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for

carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. The

PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to

provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been

designed for sharing an antenna between WL and BT to support simultaneous RX-RX.

The key PHY features include:

•

Programmable data rates from MCS0–15 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in

IEEE 802.11ac Draft

•

Supports Optional Short GI and Green Field modes in TX and RX

TX and RX LDPC for improved range and power efficiency

Beamforming support

All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse

operations in the receive direction.

•

Supports IEEE 802.11h/k for worldwide operation

Advanced algorithms for low power, enhanced sensitivity, range, and reliability

Algorithms to improve performance in presence of Bluetooth

Closed loop transmit power control

Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities

On-the-fly channel frequency and transmit power selection

Supports per packet RX antenna diversity

Available per-packet channel quality and signal strength measurements

Designed to meet FCC and other worldwide regulatory requirements

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 79

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

IEEE 802.11ac Draft PHY

Figure 31: WLAN PHY Block Diagram

CCK/DSSS

Demodulate

Filters and

Radio Comp

Frequency and

Timing Synch

Descramble

and Deframe

OFDM

Demodulate

Viterbi Decoder

Carrier Sense,

AGC, and Rx FSM

Radio Control

Block

Buffers

MAC

Interface

FFT/IFFT

AFE

and

Radio

Tx FSM

Modulation

and Coding

Common Logic

Block

Frame and

Scramble

Filters and Radio

Comp

Modulate/

Spread

PA Comp

COEX

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 80

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN Radio Subsystem

Section 12: WLAN Radio Subsystem

The BCM4354 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in

2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust

communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII

bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions.

Sixteen RF control signals are available (eight per core) to drive external RF switches and support optional

external power amplifiers and low-noise amplifiers for each band. See the reference board schematics for

further details.

A block diagram of the radio subsystem (core 0) is shown in Figure 32 on page 82. Core 1, is identical to Core 0

without the Bluetooth blocks. The integrated on-chip baluns (not shown) convert the fully differential transmit

and receive paths to single-ended signal pins.

Receiver Path

The BCM4354 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. An on-chip

low noise amplifier (LNA) in the 2.4 GHz path in core 0 is shared between the Bluetooth and WLAN receivers,

whereas the 5 GHz receive path and the core 1 2.4 GHz receive path have dedicated on-chip LNAs. Control

signals are available that can support the use of external LNAs for each band, which can increase the receive

sensitivity by several dB.

Transmit Path

Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5 GHz U-NII bands, respectively. Linear

on-chip power amplifiers are included, which are capable of delivering high output power while meeting IEEE

802.11ac and IEEE 802.11a/b/g/n specifications, and without the need for external PAs. When using the internal

PAs, closed-loop output power control is completely integrated.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 81

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Transmit Path

Figure 32: Radio Functional Block Diagram (core 0)

WL DAC

WL PA

WL PAD

WL PGA

WL TXLPF

WL TX G-Mixer

WL DAC

WL A-PA

WL A-PAD

WL A-PGA

WL TXLPF

WL TX A-Mixer

WL RX A-Mixer

Voltage

Regulators

WLAN BB

WL ADC

WL A-LNA11

WL A-LNA12

WL RXLPF

MUX

WL ADC

SLNA

WL G-LNA12

WL RXLPF

WL RX G-Mixer

WL ATX

WL ARX

WL GTX

WL GRX

CLB

WL LOGEN

WL PLL

Gm

BT LNA GM

Shared XO

BT RX

BT TX

BT LOGEN

BT PLL

LPO/Ext LPO/RCAL

BT ADC

BT RXLPF

BT ADC

BT LNA Load

BT PA

BT RX Mixer

BT BB

BT FM

BT DAC

BT TX Mixer

BT TXLPF

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 82

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Calibration

The BCM4354 features dynamic and automatic on-chip calibration to continually compensate for temperature

and process variations across components. These calibration routines are performed periodically in the course

of normal radio operation. Examples of some of the automatic calibration algorithms are baseband filter

calibration for optimum transmit and receive performance, and LOFT calibration for carrier leakage reduction.

In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip. No per-board calibration

is required in manufacturing test, which helps to minimize the test time and cost in large volume production.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 83

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pinout and Signal Descriptions

Section 13: Pinout and Signal Descriptions

Ball Maps

Figure 33 and Figure 34 on page 85 show the WLBGA ball map.

Figure 33: WLBGA Ball Map, 4.87 mm × 7.67 mm Array, 192-Ball, A1–V6 (Bottom View—Balls Facing Up)

6

5

4

3

2

1

HSIC_DATA

PCIE_REFCLKN

PCIE_REFCLKP

PCIE_TDN

PCIE_TDP

A

B

C

D

E

PCIE_PLL

_AVDD1P2

PCIE_RXTX

_AVDD1P2

HSIC_AGND12PLL

HSIC_DVDD12

VSSC

PCIE_PLL_AVSS

PCIE_PME_L

PCIE_RXTX_AVSS

PCIE_PERST_L

VDDC

PCIE_RDN

PCIE_RDP

PCIE_TESTP

VSSC

PCIE_TESTN

PCIE_CLKREQ_L

BT_USB_DN

GPIO_9

BT_VDDC

FM_AUDIOVDD1P2

FM_AOUT1

FM_AOUT2

LPO_IN

BT_USB_DP

CLK_REQ

FM_PLLVDD1P2

FM_PLLVSS

F

FM_AUDIOVSS

FM_VCOVSS

BT_I2S_DO

BT_I2S_DI

VSSC

FM_LNAVCOVDD1P2

FM_RFIN

G

H

J

BT_UART_RXD

BT_UART_TXD

BT_UART_RTS_L

BT_UART_CTS_L

BT_VDDC

BT_PCM_OUT

BT_PCM_IN

BT_GPIO_4

BT_DEV_WAKE

VSSC

BT_VDDC

FM_LNAVSS

BT_VCOVSS

BT_PLLVDD1P2

BT_PAVSS

BT_I2S_CLK

BT_PCM_SYNC

BT_I2S_WS

BT_HOST_WAKE

BT_IFVDD1P2

BT_PLLVSS

BT_VCOVDD1P2

BT_LNAVDD1P2

BT_RF

K

L

BT_PCM_CLK

BT_IFVSS

BT_PAVDD2P5

M

N

P

R

T

WRF_RX2G

_GND1P2_CORE0

WRF_LNA_2G

_GND1P2_CORE0

WRF_RFIN

_2G_CORE0

RF_SW_CTRL_4

RF_SW_CTRL_6

WRF_AFE

_GND1P2_CORE0

WRF_TX

_GND1P2_CORE0

WRF_PA2G_VBAT

_GND3P3_CORE0

WRF_RFOUT

_2G_CORE0

WRF_LOGEN

_GND1P2

WRF_LOGENG

_GND1P2

WRF_GPIO

_OUT_CORE0

WRF_PADRV_VBAT

_VDD3P3_CORE0

WRF_PA2G_VBAT

_GND3P3_CORE0

WRF_PA2G_VBAT

_VDD3P3_CORE0

WRF_MMD

_GND1P2

WRF_MMD

_VDD1P2

WRF_PFD

_VDD1P2

WRF_PADRV_VBAT

_GND3P3_CORE0

WRF_PA5G_VBAT

_GND3P3_CORE0

WRF_PA5G_VBAT

_VDD3P3_CORE0

WRF_BUCK

_VDD1P5

CORE0

WRF_VCO

_GND1P2

WRF_PFD

_GND1P2

WRF_TSSI_A

_CORE0

WRF_PA5G_VBAT

_GND3P3_CORE0

WRF_RFOUT

_5G_CORE0

U

V

WRF_SYNTH

_VBAT_VDD3P3

WRF_CP

_GND1P2

WRF_BUCK

_GND1P5_CORE0

WRF_RX5G

_GND1P2_CORE0

WRF_LNA_5G

_GND1P2_CORE0

WRF_RFIN

_5G_CORE0

6

5

4

3

2

1

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 84

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Ball Maps

Figure 34: WLBGA Ball Map, 4.87 × 7.67 Array, 192-Ball, A7 – V12 (Bottom View—Balls Facing Up)

12

11

10

9

8

7

SR

_PVSS

SR

_VLX

A

B

C

D

E

WL_REG_ON

SDIO_CMD

SDIO_CLK

HSIC_STROBE

SR

PMU_AVSS

VSSC

SDIO_DATA_0

SDIO_DATA_1

JTAG_SEL

SDIO_DATA_2

SDIO_DATA_3

VDDC

HSIC_AVDD12PLL

RREFHSIC

_VDDBATP5V

_VDDBATA5V

LDO

_VDD1P5

VOUT

_CLDO

VOUT

_BTLDO2P5

VOUT

_LNLDO

BT_REG_ON

VDDIO

LDO

_VDDBAT5V

VOUT

_LDO3P3_B

VDDC

VDDIO_SD

GPIO_6

VSSC

GPIO_7

VOUT

_3P3

F

GPIO_2

GPIO_0

GPIO_1

VDDC

GPIO_5

GPIO_8

G

H

J

VSSC

GPIO_10

VDDC

GPIO_3

AVSS_BBPLL

AVDD_BBPLL

VDDIO_RF

GPIO_4

RF_SW

_CTRL_9

RF_SW_CTRL_12

VDDC

RF_SW

_CTRL_8

RF_SW

_CTRL_13

K

L

BT_VDDIO

VSSC

VDDC

RF_SW_CTRL_11

RF_SW_CTRL_2

RF_SW_CTRL_15

RF_SW_CTRL_7

RF_SW_CTRL_1

RF_SW

_CTRL_10

RF_SW

_CTRL_14

M

N

P

R

T

VDDC

WRF_XTAL

_OUT

WRF_XTAL

_GND1P2

WRF_XTAL

_VDD1P2

RF_SW_CTRL_3

RF_SW_CTRL_5

RF_SW_CTRL_0

WRF_XTAL

_IN

WRF_XTAL

_VDD1P5

WRF_BUCK

_GND1P5_CORE1

WRF_BUCK

_VDD1P5_CORE1

WRF_GPIO_OUT

_CORE1

WRF_AFE

_GND1P2_CORE1

WRF_RX5G

_GND1P2_CORE1

WRF_TSSI

_A_CORE1

WRF_PADRV_VBAT

_GND3P3_CORE1

WRF_PADRV_VBAT

_VDD3P3_CORE1

WRF_TX

_GND1P2_CORE1

WRF_RX2G

_GND1P2_CORE1

WRF_LNA

_5G_GND1P2_CORE1

WRF_PA5G_VBAT

_GND3P3_CORE1

WRF_PA5G_VBAT

_GND3P3_CORE1

WRF_PA2G_VBAT

_GND3P3_CORE1

WRF_PA2G_VBAT

_GND3P3_CORE1

WRF_LNA_2G

_GND1P2_CORE1

U

V

WRF_RFIN

_5G_CORE1

WRF_RFOUT

_5G_CORE1

WRF_PA5G_VBAT

_VDD3P3_CORE1

WRF_PA2G_VBAT

_VDD3P3_CORE1

WRF_RFOUT

_2G_CORE1

WRF_RFIN

_2G_CORE1

12

11

10

9

8

7

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 85

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 18: Pin List by Pin Number (192-Pin WLBGA Package)

WLBGA

Ball#

Pin Name

D11

D12

D3

D4

D5

D6

D7

D9

E1

VOUT_LNLDO

VOUT_BTLDO2P5

VSSC/VSS

A10

A11

A12

A2

WL_REG_ON

SR_VLX

SR_PVSS

VDD/VDDC

PCIE_CLKREQ_L

VSSC/VSS

PCIE_TDP0

A3

PCIE_TDN0

A4

PCIE_REFCLKP

PCIE_REFCLKN

HSIC_DATA

RREFHSIC

JTAG_SEL

A5

A6

FM_AOUT1

VDDIO

A7

HSIC_STROBE

SDIO_CLK

E10

E11

E12

E2

A8

VOUT_LDO3P3_B

LDO_VDDBAT5V

FM_AUDIOVDD1P2

BT_VDD/VDDC

BT_USB_DN

GPIO_9

A9

SDIO_CMD

B1

PCIE_RDN0

B10

B11

B12

B2

PMU_AVSS

E4

SR_VDDBATA5V

SR_VDDBATP5V

PCIE_RXTX_AVDD1P2

PCIE_PLL_AVDD1P2

PCIE_RXTX_AVSS

PCIE_PLL_AVSS

HSIC_AGND12PLL

VDD/VDDC

E5

E6

E7

GPIO_7

B3

E8

VDDIO_SD

VDD/VDDC

FM_AOUT2

GPIO_1

B4

E9

B5

F1

B6

F10

F11

F12

F2

B7

GPIO_2

B8

SDIO_DATA_2

SDIO_DATA_0

PCIE_RDP0

VOUT_3P3

FM_AUDIOVSS

FM_PLLVDD1P2

CLK_REQ

B9

C1

C10

C11

C12

C2

C3

C4

C5

C6

C7

C8

C9

D10

F3

VSSC/VSS

F4

VOUT_CLDO

LDO_VDD1P5

PCIE_TESTN

PCIE_TESTP

PCIE_PERST_L

PCIE_PME_L

HSIC_DVDD12

HSIC_AVDD12PLL

SDIO_DATA_3

SDIO_DATA_1

BT_REG_ON

F5

BT_USB_DP

LPO_IN

F6

F7

GPIO_8

F8

GPIO_6

F9

GPIO_5

G1

G10

G11

G12

G2

FM_LNAVCOVDD1P2

VDD/VDDC

GPIO_0

VSSC/VSS

FM_VCOVSS

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 86

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

WLBGA

Ball#

WLBGA

Ball#

Pin Name

G3

G4

G5

G6

G7

G8

G9

H1

H11

H12

H2

H3

H4

H5

H7

H9

J1

FM_PLLVSS

VSSC/VSS

L4

BT_DEV_WAKE

L5

BT_UART_CTS_L

BT_I2S_WS

BT_I2S_DI

L6

BT_I2S_DO

L7

VSSC/VSS

AVSS_BBPLL

VSSC/VSS

L8

RF_SW_CTRL_15

RF_SW_CTRL_11

BT_PAVDD2P5

L9

GPIO_3

M1

M10

M12

M3

M4

M5

M6

M7

M8

N1

N10

N11

N12

N2

N3

N5

N7

N8

P1

FM_RFIN

RF_SW_CTRL_14

RF_SW_CTRL_10

BT_IFVSS

VDDIO_RF

GPIO_10

FM_LNAVSS

BT_VDD/VDDC

BT_PCM_OUT

BT_UART_RXD

AVDD_BBPLL

GPIO_4

VSSC/VSS

BT_VDD/VDDC

BT_PCM_CLK

VDD/VDDC

RF_SW_CTRL_7

WRF_RFIN_2G_CORE0

WRF_XTAL_VDD1P2

WRF_XTAL_GND1P2

WRF_XTAL_OUT

WRF_LNA_2G_GND1P2_CORE0

WRF_RX2G_GND1P2_CORE0

RF_SW_CTRL_4

RF_SW_CTRL_3

RF_SW_CTRL_1

WRF_RFOUT_2G_CORE0

WRF_XTAL_VDD1P5

WRF_XTAL_IN

BT_VCOVDD1P2

RF_SW_CTRL_9

VDD/VDDC

J11

J12

J2

BT_VCOVSS

BT_HOST_WAKE

BT_PCM_IN

BT_UART_TXD

BT_I2S_CLK

VDD/VDDC

J3

J4

J5

J6

J8

J9

RF_SW_CTRL_12

BT_LNAVDD1P2

RF_SW_CTRL_13

RF_SW_CTRL_8

BT_PLLVDD1P2

BT_IFVDD1P2

BT_GPIO_4

P11

P12

P2

K1

K10

K12

K2

K3

K4

K5

K6

K7

L1

WRF_PA2G_VBAT_GND3P3_CORE0

WRF_TX_GND1P2_CORE0

WRF_AFE_GND1P2_CORE0

RF_SW_CTRL_6

P3

P4

P5

P7

RF_SW_CTRL_5

BT_UART_RTS_L

BT_PCM_SYNC

BT_VDDIO

P9

RF_SW_CTRL_2

R1

R11

R12

R2

R3

R4

R5

WRF_PA2G_VBAT_VDD3P3_CORE0

WRF_BUCK_VDD1P5_CORE1

WRF_BUCK_GND1P5_CORE1

WRF_PA2G_VBAT_GND3P3_CORE0

WRF_PADRV_VBAT_VDD3P3_CORE0

WRF_GPIO_OUT_CORE0

WRF_LOGENG_GND1P2

BT_RF

L10

L11

L2

VDD/VDDC

VSSC/VSS

BT_PAVSS

L3

BT_PLLVSS

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 87

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

WLBGA

Ball#

Pin Name

R6

R7

R8

R9

T1

WRF_LOGEN_GND1P2

RF_SW_CTRL_0

WRF_AFE_GND1P2_CORE1

WRF_GPIO_OUT_CORE1

WRF_PA5G_VBAT_VDD3P3_CORE0

WRF_PADRV_VBAT_GND3P3_CORE1

WRF_TSSI_A_CORE1

T10

T11

T12

T2

WRF_RX5G_GND1P2_CORE1

WRF_PA5G_VBAT_GND3P3_CORE0

WRF_PADRV_VBAT_GND3P3_CORE0

WRF_PFD_VDD1P2

T3

T4

T5

WRF_MMD_VDD1P2

T6

WRF_MMD_GND1P2

T7

WRF_RX2G_GND1P2_CORE1

WRF_TX_GND1P2_CORE1

WRF_PADRV_VBAT_VDD3P3_CORE1

WRF_RFOUT_5G_CORE0

T8

T9

U1

U10

U11

U12

U2

U3

U4

U5

U6

U7

U8

U9

V1

V10

V11

V12

V2

V3

V4

V5

V6

V7

V8

WRF_PA5G_VBAT_GND3P3_CORE1

WRF_LNA_5G_GND1P2_CORE1

WRF_PA5G_VBAT_GND3P3_CORE0

WRF_TSSI_A_CORE0

WRF_BUCK_VDD1P5_CORE0

WRF_PFD_GND1P2

WRF_VCO_GND1P2

WRF_LNA_2G_GND1P2_CORE1

WRF_PA2G_VBAT_GND3P3_CORE1

WRF_RFIN_5G_CORE0

WRF_PA5G_VBAT_VDD3P3_CORE1

WRF_RFOUT_5G_CORE1

WRF_RFIN_5G_CORE1

WRF_LNA_5G_GND1P2_CORE0

WRF_RX5G_GND1P2_CORE0

WRF_BUCK_GND1P5_CORE0

WRF_CP_GND1P2

WRF_SYNTH_VBAT_VDD3P3

WRF_RFIN_2G_CORE1

WRF_RFOUT_2G_CORE1

V9

WRF_PA2G_VBAT_VDD3P3_CORE1

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 88

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 19: Pin List by Pin Name (192-Pin WLBGA Package)

WLBGA

Ball#

Pin Name

Ball#

FM_PLLVSS

FM_RFIN

G3

H1

G2

G11

F10

H12

F11

G9

H9

F9

AVDD_BBPLL

AVSS_BBPLL

BT_DEV_WAKE

BT_GPIO_4

H7

G7

L4

FM_VCOVSS

GPIO_0

K4

J3

GPIO_1

BT_HOST_WAKE

BT_I2S_CLK

GPIO_10

J6

GPIO_2

BT_I2S_DI

G5

G6

L6

GPIO_3

BT_I2S_DO

GPIO_4

BT_I2S_WS

GPIO_5

BT_IFVDD1P2

BT_IFVSS

K3

M3

K1

M1

L2

GPIO_6

F8

GPIO_7

E7

F7

BT_LNAVDD1P2

BT_PAVDD2P5

BT_PAVSS

GPIO_8

GPIO_9

E6

B6

C7

A6

C6

A7

D9

C12

E12

F6

HSIC_AGND12PLL

HSIC_AVDD12PLL

HSIC_DATA

HSIC_DVDD12

HSIC_STROBE

JTAG_SEL

BT_PCM_CLK

BT_PCM_IN

M6

J4

BT_PCM_OUT

BT_PCM_SYNC

BT_PLLVDD1P2

BT_PLLVSS

H4

K6

K2

L3

LDO_VDD1P5

LDO_VDDBAT5V

LPO_IN

BT_REG_ON

BT_RF

D10

L1

BT_UART_CTS_L

BT_UART_RTS_L

BT_UART_RXD

BT_UART_TXD

BT_USB_DN

BT_USB_DP

L5

PCIE_PME_L

PCIE_CLKREQ_L

PCIE_PERST_L

PCIE_PLL_AVDD1P2

PCIE_PLL_AVSS

PCIE_RDN0

PCIE_RDP0

PCIE_REFCLKN

PCIE_REFCLKP

PCIE_RXTX_AVDD1P2

PCIE_RXTX_AVSS

PCIE_TDN0

PCIE_TDP0

PCIE_TESTN

PCIE_TESTP

PMU_AVSS

C5

D5

C4

B3

B5

B1

C1

A5

A4

B2

B4

A3

A2

C2

C3

B10

K5

H5

J5

E5

F5

J1

BT_VCOVDD1P2

BT_VCOVSS

BT_VDDIO

J2

K7

F4

E1

F1

E2

F2

G1

H2

F3

CLK_REQ

FM_AOUT1

FM_AOUT2

FM_AUDIOVDD1P2

FM_AUDIOVSS

FM_LNAVCOVDD1P2

FM_LNAVSS

FM_PLLVDD1P2

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 89

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

WLBGA

Ball#

WLBGA

Ball#

Pin Name

RF_SW_CTRL_0

RF_SW_CTRL_1

RF_SW_CTRL_10

RF_SW_CTRL_11

RF_SW_CTRL_12

RF_SW_CTRL_13

RF_SW_CTRL_14

RF_SW_CTRL_15

RF_SW_CTRL_2

RF_SW_CTRL_3

RF_SW_CTRL_4

RF_SW_CTRL_5

RF_SW_CTRL_6

RF_SW_CTRL_7

RF_SW_CTRL_8

RF_SW_CTRL_9

RREFHSIC

R7

VDDIO_SD

E8

N8

VOUT_3P3

F12

D12

C11

E11

D11

C10

D3

M12

L9

VOUT_BTLDO2P5

VOUT_CLDO

J9

VOUT_LDO3P3_B

K10

M10

L8

VOUT_LNLDO

VSSC/VSS

P9

VSSC/VSS

D6

N7

VSSC/VSS

G12

G4

G8

L11

L7

N5

VSSC/VSS

P7

VSSC/VSS

P5

VSSC/VSS

M8

K12

J11

D7

VSSC/VSS

M4

A10

P4

WL_REG_ON

WRF_AFE_GND1P2_CORE0

WRF_AFE_GND1P2_CORE1

WRF_BUCK_GND1P5_CORE0

WRF_BUCK_GND1P5_CORE1

WRF_BUCK_VDD1P5_CORE0

WRF_BUCK_VDD1P5_CORE1

WRF_CP_GND1P2

SDIO_CLK

A8

R8

SDIO_CMD

A9

V4

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

SR_PVSS

B9

R12

U4

C9

B8

R11

V5

C8

A12

B11

B12

A11

B7

WRF_GPIO_OUT_CORE0

WRF_GPIO_OUT_CORE1

WRF_LNA_2G_GND1P2_CORE0

WRF_LNA_2G_GND1P2_CORE1

WRF_LNA_5G_GND1P2_CORE0

WRF_LNA_5G_GND1P2_CORE1

WRF_LOGEN_GND1P2

WRF_LOGENG_GND1P2

WRF_MMD_GND1P2

WRF_MMD_VDD1P2

R4

SR_VDDBATA5V

SR_VDDBATP5V

SR_VLX

R9

N2

U7

VDD/VDDC

V2

VDD/VDDC

D4

U12

R6

BT_VDD/VDDC

VDD/VDDC

E4

E9

R5

VDD/VDDC

G10

H3

T6

BT_VDD/VDDC

VDD/VDDC

T5

J12

J8

WRF_PA2G_VBAT_GND3P3_CORE0

WRF_PA2G_VBAT_GND3P3_CORE1

WRF_PA2G_VBAT_VDD3P3_CORE0

WRF_PA2G_VBAT_VDD3P3_CORE1

WRF_PA5G_VBAT_GND3P3_CORE0

P2

VDD/VDDC

R2

VDD/VDDC

L10

M5

M7

E10

H11

U8

BT_VDD/VDDC

VDD/VDDC

U9

R1

VDDIO

V9

VDDIO_RF

T2

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 90

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

WLBGA

Ball#

Pin Name

WRF_PA5G_VBAT_GND3P3_CORE0

WRF_PA5G_VBAT_GND3P3_CORE1

WRF_PA5G_VBAT_VDD3P3_CORE0

WRF_PA5G_VBAT_VDD3P3_CORE1

U2

U10

U11

T1

V10

WRF_PADRV_VBAT_GND3P3_CORE0 T3

WRF_PADRV_VBAT_GND3P3_CORE1 T10

WRF_PADRV_VBAT_VDD3P3_CORE0

WRF_PADRV_VBAT_VDD3P3_CORE1

WRF_PFD_GND1P2

R3

T9

U5

WRF_PFD_VDD1P2

T4

WRF_RFIN_2G_CORE0

WRF_RFIN_2G_CORE1

WRF_RFIN_5G_CORE0

WRF_RFIN_5G_CORE1

WRF_RFOUT_2G_CORE0

WRF_RFOUT_2G_CORE1

WRF_RFOUT_5G_CORE0

WRF_RFOUT_5G_CORE1

WRF_RX2G_GND1P2_CORE0

WRF_RX2G_GND1P2_CORE1

WRF_RX5G_GND1P2_CORE0

WRF_RX5G_GND1P2_CORE1

WRF_SYNTH_VBAT_VDD3P3

WRF_TSSI_A_CORE0

N1

V7

V1

V12

P1

V8

U1

V11

N3

T7

V3

T12

V6

U3

T11

P3

WRF_TSSI_A_CORE1

WRF_TX_GND1P2_CORE0

WRF_TX_GND1P2_CORE1

WRF_VCO_GND1P2

T8

U6

WRF_XTAL_GND1P2

N11

P12

N12

N10

P11

WRF_XTAL_IN

WRF_XTAL_OUT

WRF_XTAL_VDD1P2

WRF_XTAL_VDD1P5

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 91

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

1

PCIE_RXTX_AVSS

2300.51

1966.81

1800.31

2134.01

2300.51

1966.81

1800.31

508.44

3659.87

3434.87

3547.37

3322.37

3068.53

3209.87

3434.87

3209.87

3322.37

3481.00

3062.57

3281.00

3062.57

3681.00

3481.00

3281.00

3481.00

3281.00

3681.00

3281.00

3481.00

3681.00

3062.57

2860.07

3595.19

2792.39

3394.49

2993.09

3193.79

2792.39

–2300.51

–1966.81

–1800.31

–2134.01

–2300.51

–1966.81

–1800.31

–508.44

–768.62

–508.44

–1177.22

–972.92

–553.11

3659.87

3434.87

3547.37

3322.37

3068.53

3209.87

3434.87

3209.87

3322.37

3481.00

3062.57

3281.00

3062.57

3681.00

3481.00

3281.00

3481.00

3281.00

3681.00

3281.00

3481.00

3681.00

3062.57

2860.07

3595.19

2792.39

3394.49

2993.09

3193.79

2792.39

2

PCIE_PLL_AVSS

PCIE_REFCLKP

PCIE_REFCLKN

PCIE_TDN0

3

4

5

6

PCIE_TDP0

7

PCIE_RXTX_AVDD1P2

PCIE_RDP0

8

9

PCIE_RDN0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

PCIE_PLL_AVSS

PCIE_PLL_AVDD1P2

USB3_REFCLKN

USB3_PVDD1P2

USB3_REFCLKP

USB3_RVDD1P2

USB3_TVDD1P2

USB3_PGND

768.62

508.44

1177.22

972.92

553.11

USB3_PGND

753.11

–753.11

USB3_PTESTP

USB3_PTESTN

USB3_TDP

773.17

–773.17

–974.72

–982.37

–1176.88

–1186.67

–526.91

–1177.22

–768.62

–1601.79

–1401.09

–1601.79

–1401.09

773.17

974.72

USB3_TDN

974.72

USB3_TGND

982.37

USB3_RDP

1176.88

1186.67

526.91

USB3_RDN

USB3_RGND

USB3_PVDD1P2

USB3_DVDD1P2

USB2_AVSS

1177.22

768.62

1601.79

1401.09

1601.79

1401.09

USB2_MONCDR

USB2_RREF

USB2_DP

USB2_AVDD3P3

USB2_DM

USB2_AVDD1P2

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 92

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

USB2_AVSSBG

1401.09

2217.95

2017.95

1768.91

1568.92

2228.18

1843.60

2176.03

1768.91

1568.92

2252.39

2227.01

1967.62

2044.00

2244.00

1614.95

1793.21

1686.40

2273.40

2260.02

2060.02

2273.40

–2202.33

–661.10

740.99

3595.19

2993.09

3193.79

–736.50

–1298.03

–392.72

–524.82

–1164.53

–223.55

–936.50

–189.65

–45.40

–1401.09

–2217.95

–2017.95

–1768.91

–1568.92

–2228.18

–1843.60

–2176.03

–1768.91

–1568.92

–2252.39

–2227.01

–1967.62

–2044.00

–2244.00

–1614.95

–1793.21

–1686.40

–2273.40

–2260.02

–2060.02

–2273.40

2202.33

661.10

3595.19

2993.09

3193.79

–736.50

–1298.03

–392.72

–524.82

–1164.53

–223.55

–936.50

–189.65

–45.40

USB2_MONPLL

USB2_DVSS

BT_PAVSS

BT_AGPIO

BT_IFVDD1P2

BT_IFVSS

BT_LNAVDD1P2

BT_LNAVSS

BT_PAVDD2P5

BT_PLLVDD1P2

BT_PLLVSS

BT_RF

BT_VCOVDD1P2

BT_VCOVSS

FM_AUDIOVDD1P2

FM_AUDIOAVSS

FM_AOUT1

FM_AOUT2

FM_IFVDD1P2

FM_IFVSS

931.81

1143.58

931.81

1143.58

931.81

371.79

171.80

FM_PLLVSS

FM_PLLVDD1P2

FM_RFAUX

FM_RFIN

871.61

695.87

68.08

313.69

FM_LNAVDD1P2

FM_LNAVSS

FM_VCOVDD1P2

FM_VCOVSS

RF_SW_CTRL_0

VDDC

354.59

154.59

731.81

531.81

–1494.00

–1355.99

2052.00

–408.01

–198.00

–1008.00

–708.00

252.00

–1494.00

–1355.99

2052.00

–408.01

–198.00

–1008.00

–708.00

252.00

VSSC

–740.99

616.50

VSSC

–616.50

–459.00

–546.71

–459.00

VSSC

459.00

VSSC

546.71

VSSC

546.71

VSSC

459.00

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 93

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side

Top Side

No. Net Name

X

Y

X

Y

74

VDDC

–661.10

740.99

–21.01

661.10

–21.01

75

VSSC

2352.00

2299.50

2531.57

2731.57

2931.58

3131.59

3331.59

3531.60

–408.01

–1008.00

–708.00

–1125.00

–21.01

–740.99

405.00

337.05

316.50

266.51

2072.12

261.11

259.00

159.00

459.00

67.05

2352.00

2299.50

2531.57

2731.57

2931.58

3131.59

3331.59

3531.60

–408.01

–1008.00

–708.00

–1125.00

–21.01

76

VDDIO_SD

SDIO_DATA_1

SDIO_CLK

SDIO_DATA_3

SDIO_DATA_2

SDIO_CMD

SDIO_DATA_0

VSSC

–405.00

–337.05

–316.50

–266.51

–2072.12

–261.11

–259.00

–159.00

–459.00

–67.05

77

78

79

80

81

82

83

84

VSSC

85

VSSC

86

RF_SW_CTRL_4

VDDC

87

88

VSSC

1651.99

252.00

1651.99

252.00

89

VSSC

90

VSSC

552.00

91

VSSC

851.99

92

VSSC

1151.99

1451.99

2052.00

552.00

1151.99

1451.99

2052.00

552.00

93

VSSC

94

VSSC

95

VSSC

96

DGNDHSIC

AGND12PLL

AVDD12PLL

RREFHSIC

STROBE

DATA

2286.36

2486.57

2686.57

2886.58

3086.59

3286.59

3486.60

–1220.99

–1008.00

–708.00

–408.01

–21.01

2286.36

2486.57

2686.57

2886.58

3086.59

3286.59

3486.60

–1220.99

–1008.00

–708.00

–408.01

–21.01

97

–67.05

67.05

98

–67.05

67.05

99

–67.05

67.05

100

101

102

103

104

105

106

107

108

109

110

–67.05

67.05

–67.05

67.05

DVDD12HSIC

VDDC

–67.05

67.05

–61.11

61.11

VSSC

–61.11

61.11

VSSC

–61.11

61.11

VSSC

–61.11

61.11

VDDC

–61.11

61.11

VDDC

–61.11

1843.97

–1220.99

–1021.00

61.11

1843.97

–1220.99

–1021.00

VDDC

138.89

–138.89

VDDC

138.89

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 94

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

VDDC

138.89

–821.00

–1220.99

–421.00

–221.00

–21.01

–138.89

261.11

–821.00

–1220.99

–421.00

–221.00

–21.01

VDDC

–261.11

138.89

140.99

768.37

816.40

599.69

338.89

–459.00

440.99

468.37

538.88

601.19

620.91

655.50

1480.37

740.99

1480.37

VDDC

–138.89

–140.99

–768.37

–816.40

–599.69

–338.89

459.00

VDDC

VSSC

252.00

VSSC

552.00

VSSC

851.99

VSSC

1151.99

1451.99

1651.99

2052.00

2352.00

–1186.86

21.84

1151.99

1451.99

1651.99

2052.00

2352.00

–1186.86

21.84

VSSC

PACKAGEOPTION_4

BT_VSSC

VDDC

–715.49

443.99

–715.49

443.99

VDDC

643.99

VDDC

1843.97

851.99

1843.97

851.99

VSSC

PACKAGEOPTION_2

PACKAGEOPTION_3

BT_VSSC

VDDC

2352.00

2592.00

–1186.86

643.99

–440.99

–468.37

–538.88

–601.19

–620.91

–655.50

–1480.37

–740.99

–1480.37

2352.00

2592.00

–1186.86

643.99

VDDC

843.98

VDDC

1043.98

1243.98

1443.98

1643.98

1843.97

–970.04

–500.07

168.14

1043.98

1243.98

1443.98

1643.98

1843.97

–970.04

–500.07

168.14

VDDC

BT_VDDC_ISO_1

BT_VDDC_ISO_2

AVDD_BBPLL

AVSS_BBPLL

BT_VDDC

PACKAGEOPTION_1

BT_VDDC

437.48

555.67

2592.00

780.66

2592.00

780.66

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 95

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

BT_VDDIO

830.29

–445.06

–724.53

–245.06

–973.39

2592.00

420.67

–830.29

–445.06

–724.53

–245.06

–973.39

2592.00

420.67

BT_VDDIO

840.29

–840.29

BT_VDDIO

865.28

–865.28

BT_VDDIO

915.28

–915.28

PACKAGEOPTION_0

BT_GPIO_5

1040.99

1048.37

1444.06

1143.51

1348.51

1644.06

1343.51

1548.50

1844.06

1543.51

2044.05

1743.51

1858.50

–2002.32

2244.05

1943.51

2058.50

–1945.91

–2040.71

–1872.11

–1760.12

–1040.99

–1048.37

–1444.06

–1143.51

–1348.51

–1644.06

–1343.51

–1548.50

–1844.06

–1543.51

–2044.05

–1743.51

–1858.50

2002.32

BT_GPIO_3

620.67

BT_GPIO_2

820.67

BT_I2S_DI

1426.01

1643.00

1940.00

2237.00

2444.00

1426.01

1643.00

1940.00

2237.00

2444.00

1346.00

1643.00

1940.00

2237.00

1346.00

1643.00

1940.00

2237.00

2534.00

–1494.00

1346.00

1643.00

1940.00

2237.00

2534.00

–806.00

516.01

1426.01

1643.00

1940.00

2237.00

2444.00

1426.01

1643.00

1940.00

2237.00

2444.00

1346.00

1643.00

1940.00

2237.00

1346.00

1643.00

1940.00

2237.00

2534.00

–1494.00

1346.00

1643.00

1940.00

2237.00

2534.00

–806.00

516.01

BT_UART_TXD

BT_I2S_WS

LPO_IN

OTP_VDD33

BT_CLK_REQ

BT_UART_RXD

BT_PCM_SYNC

BT_USB_DN

PCIE_PME_L

BT_TM1

BT_I2S_CLK

BT_GPIO_4

BT_USB_DP

BT_HOST_WAKE

BT_I2S_DO

BT_UART_CTS_N

BT_PCM_IN

PCIE_CLKREQ_L

RF_SW_CTRL_1

BT_DEV_WAKE

BT_PCM_OUT

BT_UART_RTS_N

BT_PCM_CLK

PERST_L

–2244.05

–1943.51

–2058.50

1945.91

RF_SW_CTRL_8

GPIO_13

2040.71

RF_SW_CTRL_5

RF_SW_CTRL_12

–1125.00

–327.01

1872.11

–1125.00

–327.01

1760.12

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 96

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side

Top Side

No. Net Name

X

Y

X

Y

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

GPIO_10

–1959.30

–1802.31

–1745.90

–1840.71

–1853.50

–1672.10

–1560.11

–1759.91

–1602.31

–1545.89

–1640.70

–1593.91

–1472.09

–1360.11

–1559.91

–459.00

229.01

1959.30

1802.31

1745.90

1840.71

1853.50

1672.10

1560.11

1759.91

1602.31

1545.89

1640.70

1593.91

1472.09

1360.11

1559.91

459.00

229.01

RF_SW_CTRL_2

RF_SW_CTRL_9

GPIO_14

–1494.00

–806.00

516.01

–1494.00

–806.00

516.01

GPIO_7

–18.00

RF_SW_CTRL_6

RF_SW_CTRL_13

GPIO_11

–1125.00

–327.01

279.00

–1125.00

–327.01

279.00

RF_SW_CTRL_3

RF_SW_CTRL_10

GPIO_15

–1494.00

–806.00

516.01

–1494.00

–806.00

516.01

GPIO_8

22.00

RF_SW_CTRL_7

RF_SW_CTRL_14

GPIO_12

–1125.00

–327.01

279.00

–1125.00

–327.01

279.00

VSSC

1151.99

1451.99

–756.00

1651.99

1017.54

22.00

1151.99

1451.99

–756.00

1651.99

1017.54

22.00

VSSC

–459.00

459.00

RF_SW_CTRL_11

VDDC

–1346.09

–459.00

1346.09

459.00

VDDC

–1345.37

–1393.90

–1215.90

–1160.10

–1261.10

–1061.11

–1061.10

–1402.10

–1180.10

–1151.11

–1058.99

–816.10

1345.37

1393.90

1215.90

1160.10

1261.10

1061.11

1061.10

1402.10

1180.10

1151.11

1058.99

816.10

GPIO_9

VDDIO

576.00

RF_SW_CTRL_15

VDDC

–327.01

1843.97

–1156.00

–776.00

–1355.99

–1494.00

–587.00

–956.00

2052.00

1843.97

2052.00

2877.58

3077.59

3277.59

3477.60

–327.01

1843.97

–1156.00

–776.00

–1355.99

–1494.00

–587.00

–956.00

2052.00

1843.97

2052.00

2877.58

3077.59

3277.59

3477.60

VDDC

VDDC_ISO_PHY

VDDC

VDDC_ISO_PHY

VDDC_ISO_DIG

VSSC

–459.00

459.00

GPIO_0

–996.05

996.05

GPIO_1

–996.05

996.05

GPIO_2

–996.05

996.05

GPIO_3

–996.05

996.05

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 97

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side

Top Side

No. Net Name

X

Y

X

Y

222

223

224

225

226

227

228

229

230

VDDIO

–990.90

–960.10

–1061.10

–1058.99

–852.10

–461.11

–769.05

–759.00

576.00

990.90

960.10

576.00

VDDIO_RF

VDDC

–117.00

1843.97

843.98

–117.00

1843.97

843.98

1061.10

1058.99

852.10

461.11

VDDC_ISO_PHY

VDDIO_RF

VDDC

1151.99

–387.00

–1355.99

3196.59

252.00

1151.99

–387.00

–1355.99

3196.59

252.00

GPIO_4

769.05

759.00

VDDIO_PCIE^a

VDDIO

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

257

–759.00

–1359.90

–1319.39

–1358.99

–1351.11

–751.05

–745.50

–733.05

–729.00

–951.31

–861.10

–1440.90

–1159.90

–616.10

75.91

552.00

759.00

1359.90

1319.39

1358.99

1351.11

751.05

552.00

VSSC

279.00

VSSC

2052.00

2302.00

–956.00

2996.59

3396.60

2352.00

2796.58

–220.50

–956.00

–1355.99

576.00

2052.00

2302.00

–956.00

2996.59

3396.60

2352.00

2796.58

–220.50

–956.00

–1355.99

576.00

VSSC

GPIO_6

GPIO_5

751.05

VDDIO_SD

745.50

JTAG_SEL

733.05

VDDC_ISO_PHY

VDDC

729.00

951.31

VDDC

861.10

VSSC

1440.90

1159.90

616.10

VSSC

–98.00

VSSC

279.00

VDDC

1843.97

–3598.00

–1834.98

–2065.65

–3109.71

–2065.65

–2303.63

–1818.42

–1960.54

–2417.93

–2823.85

–2944.01

1843.97

–3598.00

–1834.98

–2065.65

–3109.71

–2065.65

–2303.63

–1818.42

–1960.54

–2417.93

–2823.85

–2944.01

WRF_SYNTH_VBAT_VDD3P3

WRF_XTAL_GND1P2

WRF_XTAL_VDD1P5

WRF_VCO_GND1P2

WRF_XTAL_IN

WRF_LOGEN_GND1P2

WRF_XTAL_OUT

WRF_XTAL_VDD1P2

WRF_TX_GND1P2_core1

WRF_BUCK_GND1P5_core1

WRF_RX5G_GND1P2_core1

–75.91

–2003.12

198.52

2003.12

–198.52

2205.82

–126.11

2205.82

1807.98

437.83

–2205.82

126.11

–2205.82

–1807.98

–437.83

–2137.36

–1968.14

2137.36

1968.14

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 98

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

258

259

260

261

262

263

264

WRF_GPIO_OUT_core1

–877.08

–167.27

–2253.44

–201.47

901.40

–2398.01

–2716.52

–3538.14

–3598.00

–2994.96

–3198.01

–2792.61

877.08

167.27

–2398.01

–2716.52

–3538.14

–3598.00

–2994.96

–3198.01

–2792.61

WRF_RX2G_GND1P2_core1

WRF_RFIN_5G_core1

WRF_RFIN_2G_core1

WRF_PFD_VDD1P2

2253.44

201.47

–901.40

–818.12

1090.70

WRF_PFD_GND1P2

818.12

WRF_PADRV_VBAT_VDD3P3_core –1090.70

1

265

WRF_PADRV_VBAT_GND3P3_core –1401.46

1

–2798.01

1401.46

–2798.01

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

WRF_PA5G_VBAT_VDD3P3_core1 –1401.46

–3679.00

–2293.35

–2798.01

–2998.01

–2994.96

–2798.01

–1940.22

–3673.49

–3598.00

–1598.02

–2716.77

–3433.91

–2353.01

–3679.00

–3198.01

–2028.11

–3198.01

–3276.89

–3144.01

–3697.00

–3225.01

–2798.01

1401.46

631.56

–3679.00

–2293.35

–2798.01

–2998.01

–2994.96

–2798.01

–1940.22

–3673.49

–3598.00

–1598.02

–2716.77

–3433.91

–2353.01

–3679.00

–3198.01

–2028.11

–3198.01

–3276.89

–3144.01

–3697.00

–3225.01

–2798.01

WRF_AFE_GND1P2_core1

–631.56

WRF_PA5G_VBAT_GND3P3_core0 1825.51

WRF_PA5G_VBAT_VDD3P3_core0 2297.50

–1825.51

–2297.50

–692.41

–499.12

–1744.51

–1877.39

–539.26

–1798.51

1839.15

–1024.35

–770.31

601.47

WRF_MMD_VDD1P2

WRF_MMD_GND1P2

692.41

499.12

WRF_PA2G_VBAT_GND3P3_core0 1744.51

WRF_LNA_5G_GND1P2_core0

WRF_CP_GND1P2

1877.39

539.26

WRF_LNA_2G_GND1P2_core0

WRF_TSSI_A_core1

1798.51

–1839.15

1024.35

770.31

WRF_BUCK_VDD1P5_core0

WRF_LOGENG_GND1P2

WRF_RFOUT_2G_core1

WRF_RFOUT_5G_core0

WRF_AFE_GND1P2_core0

WRF_LNA_2G_GND1P2_core1

WRF_LNA_5G_GND1P2_core1

–601.47

2288.50

880.13

–2288.50

–880.13

201.47

–201.47

–2276.94

2276.94

543.68

WRF_PA2G_VBAT_GND3P3_core1 –543.68

WRF_PA2G_VBAT_VDD3P3_core1 –801.47

WRF_PA5G_VBAT_GND3P3_core1 –1801.46

WRF_PA5G_VBAT_VDD3P3_core0 2279.50

801.47

1801.46

–2279.50

–1398.51

WRF_PADRV_VBAT_GND3P3_core 1398.51

0

289

WRF_PADRV_VBAT_VDD3P3_core 1393.11

0

–2487.25

–1393.11

–2487.25

290

291

WRF_RFIN_2G_core0

2198.50

1317.02

–1598.02

–1563.82

–2198.50

–1317.02

–1598.02

–1563.82

WRF_RX2G_GND1P2_core0

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 99

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

321

322

323

324

325

326

327

328

WRF_RX5G_GND1P2_core0

1544.51

1018.43

1317.27

1424.35

–2237.36

998.51

–3364.69

–1834.38

–3235.69

–3533.90

–2423.85

–2273.63

–1998.02

–3688.00

–2523.25

–3114.13

–3649.99

–3198.01

–3225.01

–2398.01

–2198.02

–1700.51

–3633.90

–3433.91

–2423.85

–2623.85

–3697.00

–3679.00

–2303.63

–2888.29

–3598.00

3277.01

–1544.51

–1018.43

–1317.27

–1424.35

2237.36

–998.51

–2279.50

1801.46

–1714.63

1126.70

–2138.64

–1825.51

1401.46

–2279.50

–2297.50

–1488.79

–1024.35

–1224.35

2037.36

2237.36

1601.46

1001.47

–326.11

303.96

–3364.69

–1834.38

–3235.69

–3533.90

–2423.85

–2273.63

–1998.02

–3688.00

–2523.25

–3114.13

–3649.99

–3198.01

–3225.01

–2398.01

–2198.02

–1700.51

–3633.90

–3433.91

–2423.85

–2623.85

–3697.00

–3679.00

–2303.63

–2888.29

–3598.00

3277.01

1721.37

1438.53

1155.69

WRF_TX_GND1P2_core0

WRF_TSSI_A_core0

WRF_BUCK_GND1P5_core0

WRF_BUCK_VDD1P5_core1

WRF_GPIO_OUT_core0

WRF_RFOUT_2G_core0

WRF_RFOUT_5G_core1

2279.50

–1801.46

WRF_PA2G_VBAT_GND3P3_core0 1714.63

WRF_PA2G_VBAT_GND3P3_core1 –1126.70

WRF_RFIN_5G_core0

2138.64

WRF_PA5G_VBAT_GND3P3_core0 1825.51

WRF_PA5G_VBAT_GND3P3_core1 –1401.46

WRF_PA2G_VBAT_VDD3P3_core0 2279.50

WRF_PA2G_VBAT_VDD3P3_core0 2297.50

WRF_RX2G_GND1P2_core0

WRF_BUCK_VDD1P5_core0

WRF_BUCK_VDD1P5_core1

1488.79

1024.35

1224.35

–2037.36

–2237.36

WRF_PA5G_VBAT_VDD3P3_core1 –1601.46

WRF_PA2G_VBAT_VDD3P3_core1 –1001.47

WRF_LOGEN_GND1P2

WRF_RX2G_GND1P2_core1

WRF_CP_GND1P2

WL_REG_ON

326.11

–303.96

339.26

–339.26

1710.77

1569.35

1852.20

1993.62

2135.04

1710.77

1852.20

2135.04

–1710.77

–1569.35

–1852.20

–1993.62

–2135.04

–1710.77

–1852.20

–2135.04

BT_REG_ON

1721.37

LDO_VDDBAT5V

VOUT_3P3

1721.37

1438.53

1155.69

1297.11

VOUT_3P3

1155.69

VDDIO_PMU

1297.11

LDO_VDDBAT5V

872.84

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 100

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

353

354

355

356

357

358

359

360

361

362

363

364

365

LDO_VDDBAT5V

–2276.46

–1710.77

–1993.62

–1569.35

–1852.20

–1993.62

–2135.04

–1710.77

–1993.62

–2276.46

1014.26

1297.11

1862.79

1579.95

1155.69

1438.53

2287.06

2852.74

3135.59

2852.74

2569.90

2287.06

2004.21

1014.26

1438.53

1721.37

2004.21

2287.06

2569.90

3135.59

1579.95

2145.64

2428.48

2711.32

2994.17

1862.79

2145.64

2428.48

2711.32

2994.17

3277.01

1862.79

2145.64

2428.48

3277.01

1579.95

2276.46

1710.77

1993.62

1569.35

1852.20

1993.62

2135.04

1710.77

1993.62

2276.46

1014.26

1297.11

1862.79

1579.95

1155.69

1438.53

2287.06

2852.74

3135.59

2852.74

2569.90

2287.06

2004.21

1014.26

1438.53

1721.37

2004.21

2287.06

2569.90

3135.59

1579.95

2145.64

2428.48

2711.32

2994.17

1862.79

2145.64

2428.48

2711.32

2994.17

3277.01

1862.79

2145.64

2428.48

3277.01

1579.95

VOUT_3P3_SENSE

LDO_VDDBAT5V

VOUT_3P3

VSSC

PMU_AVSS

SR_VLX

SR_PVSS

SR_VLX

SR_VDDBATA5V

VOUT_CLDO

LDO_VDD1P5

LDO_VDDBAT5V

VOUT_3P3

LDO_VDDBAT5V

VOUT_LDO3P3_B

LDO_VDD1P5

SR_VDDBATP5V

SR_PVSS

VDDIO_PMU

VOUT_LNLDO

VOUT_CLDO

SR_VLX

VOUT_LDO3P3_B

LDO_VDD1P5

VOUT_CLDO

SR_VDDBATP5V

SR_VLX

SR_PVSS

VOUT_3P3

VOUT_BTLDO2P5

LDO_VDD1P5

SR_PVSS

VOUT_3P3

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 101

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Pin Lists

Table 20: 395-Bump WLCSP Coordinates (Cont.)

Coordinates (0,0 center of die)

Bump Side Top Side

No. Net Name

X

Y

X

Y

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

385

386

387

388

389

390

391

392

393

394

395

SR_VDDBATP5V

–2276.46

1800.31

1966.81

1480.37

1408.19

1322.34

1060.28

666.40

2711.32

3068.53

2956.03

1005.66

1225.66

248.05

2276.46

–1800.31

–1966.81

–1480.37

–1408.19

–1322.34

–1060.28

–666.40

–617.61

–338.89

–1040.28

–1063.38

–1273.37

–440.99

1293.24

1202.10

1058.99

959.90

2711.32

3068.53

2956.03

1005.66

1225.66

248.05

PCIE_TESTP

PCIE_TESTN

BT_VDDC

BT_VSSC

VSSC

55.02

–1186.86

–198.15

–1324.61

–475.07

–724.53

1020.66

1320.66

505.67

–1186.86

–198.15

–1324.61

–475.07

–724.53

1020.66

1320.66

505.67

617.61

338.89

1040.28

1063.38

1273.37

440.99

705.66

1005.66

1225.66

2052.00

–1317.60

–1504.00

1451.99

2302.00

279.00

1005.66

1225.66

2052.00

–1317.60

–1504.00

1451.99

2302.00

279.00

VSSC

–1293.24

–1202.10

–1058.99

–959.90

–759.00

–746.31

VSSC

851.99

759.00

851.99

VSSC

1151.99

1451.99

2052.00

–956.00

–756.00

759.00

1151.99

1451.99

2052.00

–956.00

–756.00

VSSC

759.00

VSSC

759.00

VSSC

746.31

VSSC

746.31

a. This net name was changed to VDDIO_PCIE to correct an error in the pin definition of bump 230. The correction

applies to WLCSP package PCIe platform only, and is inconsequential for SDIO platforms.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 102

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

The signal name, type, and description of each pin in the BCM4354 is listed in Table 21 (WLCSP) and Table 22

on page 111 (WLBGA). The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O

= output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak

internal pull-down resistor), if any.

Table 21: WLCSP Signal Descriptions

Bump# Signal Name

Type Description

WLAN and Bluetooth Receive RF Signal Interface

290

261

WRF_RFIN_2G_CORE0

WRF_RFIN_2G_CORE1

I

2.4 GHz Bluetooth and WLAN CORE0 receiver

shared input

2.4 GHz Bluetooth and WLAN CORE1 receiver

shared input

302

260

298

279

280

299

294

WRF_RFIN_5G_CORE0

WRF_RFIN_5G_CORE1

WRF_RFOUT_2G_CORE0

WRF_RFOUT_2G_CORE1

WRF_RFOUT_5G_CORE0

WRF_RFOUT_5G_CORE1

WRF_TSSI_A_CORE0

I

5 GHz WLAN CORE0 receiver input

5 GHz WLAN CORE1 receiver input

2.4 GHz WLAN CORE0 PA output

2.4 GHz WLAN CORE1 PA output

5 GHz WLAN CORE0 PA output

5 GHz WLAN CORE1 PA output

I

O

I

5 GHz TSSI CORE0 input from an optional external

power amplifier/power detector.

276

297

258

WRF_TSSI_A_CORE1

I

5 GHz TSSI CORE1 input from an optional external

power amplifier/power detector.

WRF_GPIO_OUT_CORE0

WRF_GPIO_OUT_CORE1

I/O GPIO or 2.4 GHz TSSI CORE0 input from an optional

external power amplifier/power detector

I/O GPIO or 2.4 GHz TSSI CORE1 input from an optional

external power amplifier/power detector

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 103

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

RF Switch Control Lines

66

RF_SW_CTRL_0

RF_SW_CTRL_1

RF_SW_CTRL_2

RF_SW_CTRL_3

RF_SW_CTRL_4

RF_SW_CTRL_5

RF_SW_CTRL_6

RF_SW_CTRL_7

RF_SW_CTRL_8

RF_SW_CTRL_9

RF_SW_CTRL_10

RF_SW_CTRL_11

RF_SW_CTRL_12

RF_SW_CTRL_13

RF_SW_CTRL_14

RF_SW_CTRL_15

O

Programmable RF switch control lines. The control

lines are programmable via the driver and NVRAM

file.

175

186

193

86

183

190

197

181

187

194

202

184

191

198

207

WLAN PCI Express Interface

174

PCIE_CLKREQ_L

OD PCIe clock request signal which indicates when the

REFCLK to the PCIe interface can be gated.

1 = the clock can be gated

0 = the clock is required

180

PCIE_PERST_L

I (PU) PCIe System Reset. This input is the PCIe reset as

defined in the PCIe base specification version 1.1.

9

PCIE_RDN0

I

Receiver differential pair (×1 lane)

8

PCIE_RDP0

4

PCIE_REFCLKN

PCIE_REFCLKP

PCIE_TDN0

I

PCIE Differential Clock inputs (negative and positive).

100 MHz differential.

3

I

5

O

Transmitter differential pair (×1 lane)

6

PCIE_TDP0

165

PCIE_PME_L

OD PCI power management event output. Used to

request a change in the device or system power state.

The assertion and deassertion of this signal is

asynchronous to the PCIe reference clock. This signal

has an open-drain output structure, as per the PCI

Bus Local Bus Specification, revision 2.3.

367

368

PCIE_TESTP

PCIE_TESTN

–

PCIe test pin

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 104

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

WLAN SDIO Bus Interface

These signals can support alternate functionality depending on package and host interface mode. See

Table 26: “GPIO Alternative Signal Functions,” on page 120

78

81

82

77

80

79

SDIO_CLK

I

SDIO clock input

SDIO_CMD

I/O SDIO command line

I/O SDIO data line 0

I/O SDIO data line 1

I/O SDIO data line 2

I/O SDIO data line 3

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

WLAN HSIC Interface

100

101

99

HSIC_STROBE

I/O HSIC Strobe

I/O HSIC Data

HSIC_DATA

RREFHSIC

I

HSIC reference resistor input. If HSIC is used,

connect this pin to ground via a 51-ohm 5% resistor.

On SDIO designs this pin should not be connected.

WLAN GPIO Interface

The GPIO signals can be multiplexed via software and the JTAG_SEL pin to support other functions. See

Table 23: “WLAN GPIO Functions and Strapping Options,” on page 119 and Table 26: “GPIO Alternative Signal

Functions,” on page 120 for additional details.

218

219

220

221

229

237

236

189

196

205

185

192

199

182

188

195

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

I/O Programmable GPIO pins

I/O

JTAG Interface

239

JTAG_SEL

I/O JTAG select: pull high to select the JTAG interface. If

the JTAG interface is not used this pin may be left

floating or connected to ground.

Note: See Table 26: “GPIO Alternative Signal

Functions,” on page 120 for the JTAG signal pins.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 105

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

Clocks

251

253

159

161

WRF_XTAL_IN

WRF_XTAL_OUT

LPO_IN

I

XTAL oscillator input

XTAL oscillator output

O

I

External sleep clock input (32.768 kHz)

CLK_REQ

O

Reference clock request (shared by BT and WLAN).

If not used, this can be no-connect.

Bluetooth/FM Transceiver

49

–

BT_RF

O

I

Bluetooth PA output

SFLASH_CLK

BT_SF_CLK

BT_SF_CS_L

BT_SF_MISO

BT_SF_MOSI

FM_RFIN

–

I/O SFLASH_CSN

–

I/O SFLASH master input, slave output

I/O SFLASH master output, slave input

–

61

60

54

55

I

FM radio antenna port

FM radio auxiliary antenna port

FM DAC output 1

FM_RFAUX

FM_AOUT1

FM_AOUT2

I

O

FM DAC output 2

Bluetooth PCM

179

173

177

163

BT_PCM_CLK

I/O PCM clock; can be master (output) or slave (input)

BT_PCM_IN

I

PCM data input

PCM data output

BT_PCM_OUT

BT_PCM_SYNC

O

I/O PCM sync; can be master (output) or slave (input).

Bluetooth USB Interface

164

BT_USB_DN

I/O USB (Host) data negative. Negative terminal of the

USB transceiver.

169

BT_USB_DP

I/O USB (Host) data positive. Positive terminal of the USB

transceiver.

Bluetooth UART

172

178

162

157

BT_UART_CTS_L

I

UART clear-to-send. Active-low clear-to-send signal

for the HCI UART interface.

BT_UART_RTS_L

BT_UART_RXD

BT_UART_TXD

O

I

UART request-to-send. Active-low request-to-send

signal for the HCI UART interface. BT LED control pin.

UART serial input. Serial data input for the HCI UART

interface.

O

UART serial output. Serial data output for the HCI

UART interface.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 106

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

Bluetooth/FM I²S

I²S clock, can be master (output) or slave (input).

167

171

156

158

BT_I2S_CLK

BT_I2S_DO

BT_I2S_DI

I/O

I²S data output

I²S data input

I/O

I²S WS; can be master (output) or slave (input).

BT_I2S_WS

Bluetooth GPIOs

155

154

168

153

BT_GPIO_2

I/O Bluetooth general-purpose I/O

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

Miscellaneous

319

WL_REG_ON

I

Used by PMU to power up or power down the internal

BCM4354 regulators used by the WLAN section.

Also, when deasserted, this pin holds the WLAN

section in reset. This pin has an internal 200 kΩ pull-

down resistor that is enabled by default. It can be

disabled through programming.

320

BT_REG_ON

I

Used by PMU to power up or power down the internal

BCM4354 regulators used by the Bluetooth/FM

section. Also, when deasserted, this pin holds the

Bluetooth/FM section in reset. This pin has an internal

200 kΩ pull-down resistor that is enabled by default. It

can be disabled through programming.

176

170

BT_DEV_WAKE

BT_HOST_WAKE

I/O Bluetooth DEV_WAKE

I/O Bluetooth HOST_WAKE

Integrated Voltage Regulators

340

348

336

SR_VDDBATA5V

SR_VDDBATP5V

SR_VLX

I

Quiet VBAT

Power VBAT

O

CBuck switching regulator output. Refer to Table 43

on page 158 for details of the inductor and capacitor

required on this output.

342

327

249

254

351

341

362

346

324

LDO_VDD1P5

I

LNLDO input

LDO_VDDBAT5V

WRF_XTAL_VDD1P5

WRF_XTAL_VDD1P2

VOUT_LNLDO

I

LDO VBAT.

I

XTAL LDO input (1.35V)

XTAL LDO output (1.2V)

Output of LNLDO

Output of core LDO

Output of BT LDO

Output of 3.3V LDO

LDO 3.3V output

O

VOUT_CLDO

VOUT_BTLDO2P5

VOUT_LDO3P3_B

VOUT_3P3

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 107

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

330

VOUT_3P3_SENSE

O

Voltage sense pin for LDO 3.3V output

Bluetooth Supplies

46

44

42

47

50

BT_PAVDD2P5

PWR Bluetooth PA power supply

PWR Bluetooth LNA power supply

PWR Bluetooth IF block power supply

PWR Bluetooth RF PLL power supply

PWR Bluetooth RF power supply

PWR Core supply

BT_LNAVDD1P2

BT_IFVDD1P2

BT_PLLVDD1P2

BT_VCOVDD1P2

148, 149, BT_VDDIO

150,151

FM Transceiver Supplies

–

FM_LNAVCOVDD1P2

PWR FM LNA and VCO 1.2V power supply

PWR FM LNA 1.2V power supply

PWR FM VCO 1.2V power supply

PWR FM PLL 1.2V power supply

PWR FM AUDIO power supply

62

64

59

52

FM_LNAVDD1P2

FM_VCOVDD1P2

FM_PLLVDD1P2

FM_AUDIOVDD1P2

WLAN Supplies

277

296

262

289

WRF_BUCK_VDD1P5_CORE0

PWR Internal capacitor-less CORE0 LDO supply

PWR Internal capacitor-less CORE1 LDO supply

PWR Synth VDD 3.3V supply

WRF_BUCK_VDD1P5_CORE1

WRF_SYNTH_VBAT_VDD3P3

WRF_PADRV_VBAT_VDD3P3_CO PWR CORE0 PA Driver VBAT supply

RE0

264

269

266

305

285

WRF_PADRV_VBAT_VDD3P3_CO PWR CORE1 PA Driver VBAT supply

RE1

WRF_PA5G_VBAT_VDD3P3_COR PWR 5 GHz CORE0 PA 3.3V VBAT supply

E0

WRF_PA5G_VBAT_VDD3P3_COR PWR 5 GHz CORE1 PA 3.3V VBAT supply

E1

WRF_PA2G_VBAT_VDD3P3_COR PWR 2 GHz CORE0 PA 3.3V VBAT supply

E0

WRF_PA2G_VBAT_VDD3P3_COR PWR 2 GHz CORE1 PA 3.3V VBAT supply

E1

270

262

WRF_MMD_VDD1P2

WRF_PFD_VDD1P2

PWR 1.2V supply

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 108

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

Miscellaneous Supplies

160

OTP_VDD33

VDDC

PWR OTP 3.3V supply

67, 74,

PWR 1.2V core supply for WLAN

87, 103,

107–115,

127–129,

134–140,

203, 204,

208–211,

213, 224,

228, 241,

242, 246

206, 222, VDDIO

231

PWR 1.8V–3.3V supply for WLAN. Must be directly

connected to PMU_VDDIO and BT_VDDIO on the

PCB.

145, 147, BT_VDDC

369– 375,

PWR 1.2V core supply for BT

326

VDDIO_PMU

PWR 1.8V–3.3V supply for PMU controls. Must be directly

connected to VDDIO and BT_VDDIO on the PCB.

76

VDDIO_SD

PWR 1.8V–3.3V supply for SDIO pads

PWR IO supply for RF switch control pads (3.3V)

PWR 1.2V supply for HSIC PLL

223

98

VDDIO_RF

HSIC_AVDD12PLL

HSIC_DVDD12

AVDD_BBPLL

102

143

11

PWR 1.2V supply for HSIC digital

PWR Baseband PLL supply

PCIE_PLL_AVDD1P2

PCIE_RXTX_AVDD1P2

VDDIO_PCIE

PWR 1.2V supply for PCIe PLL

7

PWR 1.2V supply for PCIE TX and RX

230

PWR Supply the same voltage to this pin as used for the

PCIe out-of-band signals (that is, PCIE_PME_L). This

would be 1.8V or 3.3V, and cannot be turned off.

Ground

250

281

267

295

256

275

282

273

283

293

255

288

WRF_VCO_GND1P2

GND VCO/LOGEN ground

WRF_AFE_GND1P2_CORE0

WRF_AFE_GND1P2_CORE1

WRF_BUCK_GND1P5_CORE0

WRF_BUCK_GND1P5_CORE1

WRF_LNA_2G_GND1P2_CORE0

WRF_LNA_2G_GND1P2_CORE1

WRF_LNA_5G_GND1P2_CORE0

WRF_LNA_5G_GND1P2_CORE1

WRF_TX_GND1P2_CORE0

WRF_TX_GND1P2_CORE1

GND CORE0 AFE ground

GND CORE1 AFE ground

GND Internal capacitor-less CORE0 LDO ground

GND Internal capacitor-less CORE1 LDO ground

GND 2 GHz internal CORE0 LNA ground

GND 2 GHz internal CORE1 LNA ground

GND 5 GHz internal CORE0 LNA ground

GND 5 GHz internal CORE1 LNA ground

GND TX CORE0 ground

GND TX CORE1 ground

WRF_PADRV_VBAT_GND3P3_CO GND PAD CORE0 ground

RE0

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 109

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

265

WRF_PADRV_VBAT_GND3P3_CO GND PAD CORE1 ground

RE1

248

WRF_XTAL_GND1P2

GND XTAL ground

291, 307 WRF_RX2G_GND1P2_CORE0

259, 317 WRF_RX2G_GND1P2_CORE1

GND RX 2GHz CORE0 ground

GND RX 2GHz CORE1 ground

GND RX 5GHz CORE0 ground

GND RX 5GHz CORE1 ground

GND LOGEN ground

292

257

WRF_RX5G_GND1P2_CORE0

WRF_RX5G_GND1P2_CORE1

252, 316 WRF_LOGEN_GND1P2

278 WRF_LOGENG_GND1P2

GND LOGEN ground

268, 030 WRF_PA5G_VBAT_GND3P3_COR GND 5 GHz PA CORE0 ground

E0

286, 304 WRF_PA5G_VBAT_GND3P3_COR GND 5 GHz PA CORE1 ground

E1

272, 300 WRF_PA2G_VBAT_GND3P3_COR GND 2 GHz PA CORE0 ground

E0

284, 301 WRF_PA2G_VBAT_GND3P3_COR GND 2 GHz PA CORE1 ground

E1

271

WRF_MMD_GND1P2

GND Ground

274, 318 WRF_CP_GND1P2

GND Ground

263

WRF_PFD_GND1P2

VSSC

GND Ground

68–73,

GND Core ground for WLAN and BT

75,

83–85,

88–95,

104–106,

116–122,

130, 200,

201, 217,

232–235,

254–245,

333, 334,

384–395

338, 349, SR_PVSS

360, 364

GND Power ground

335

97

40

43

48

51

65

63

58

53

PMU_AVSS

GND Quiet ground

HSIC_AGND12PLL

BT_PAVSS

GND HSIC PLL ground

GND Bluetooth PA ground

GND Bluetooth IF block ground

GND Bluetooth PLL ground

GND Bluetooth VCO ground

GND FM VCO ground

BT_IFVSS

BT_PLLVSS

BT_VCOVSS

FM_VCOVSS

FM_LNAVSS

FM_PLLVSS

FM_AUDIOVSS

GND FM LNA ground

GND FM PLL ground

GND FM AUDIO ground

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 110

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 21: WLCSP Signal Descriptions (Cont.)

Type Description

Bump# Signal Name

144

10

1

AVSS_BBPLL

PCIE_AVSS

GND Baseband PLL ground

GND PCIe ground

GND Ground

PCIE_RXTX_AVSS

PCIE_PLL_AVSS

RGND

2

17, 18,

23, 26, 96

–

BTRGND

GND Ground

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

WLAN and Bluetooth Receive RF Signal Interface

N1

WRF_RFIN_2G_CORE0

I

2.4 GHz Bluetooth and WLAN CORE0 receiver

shared input

V7

WRF_RFIN_2G_CORE1

I

2.4 GHz Bluetooth and WLAN CORE1 receiver

shared input

V1

WRF_RFIN_5G_CORE0

WRF_RFIN_5G_CORE1

WRF_RFOUT_2G_CORE0

WRF_RFOUT_2G_CORE1

WRF_RFOUT_5G_CORE0

WRF_RFOUT_5G_CORE1

WRF_TSSI_A_CORE0

I

5 GHz WLAN CORE0 receiver input

5 GHz WLAN CORE1 receiver input

2.4 GHz WLAN CORE0 PA output

2.4 GHz WLAN CORE1 PA output

5 GHz WLAN CORE0 PA output

5 GHz WLAN CORE1 PA output

V12

P1

I

O

I

V8

U1

V11

U3

5 GHz TSSI CORE0 input from an optional external

power amplifier/power detector.

T11

R4

R9

WRF_TSSI_A_CORE1

I

5 GHz TSSI CORE1 input from an optional external

power amplifier/power detector.

WRF_GPIO_OUT_CORE0

WRF_GPIO_OUT_CORE1

I/O GPIO or 2.4 GHz TSSI CORE0 input from an optional

external power amplifier/power detector

I/O GPIO or 2.4 GHz TSSI CORE1 input from an optional

external power amplifier/power detector

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 111

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

RF Switch Control Lines

R7

RF_SW_CTRL_0

RF_SW_CTRL_1

RF_SW_CTRL_2

RF_SW_CTRL_3

RF_SW_CTRL_4

RF_SW_CTRL_5

RF_SW_CTRL_6

RF_SW_CTRL_7

RF_SW_CTRL_8

RF_SW_CTRL_9

RF_SW_CTRL_10

RF_SW_CTRL_11

RF_SW_CTRL_12

RF_SW_CTRL_13

RF_SW_CTRL_14

RF_SW_CTRL_15

O

Programmable RF switch control lines. The control

lines are programmable via the driver and NVRAM

file.

N8

P9

N7

N5

P7

P5

M8

K12

J11

M12

L9

J9

K10

M10

L8

WLAN PCI Express Interface

D5

PCIE_CLKREQ_L

OD PCIe clock request signal which indicates when the

REFCLK to the PCIe interface can be gated.

1 = the clock can be gated

0 = the clock is required

C4

PCIE_PERST_L

I (PU) PCIe System Reset. This input is the PCIe reset as

defined in the PCIe base specification version 1.1.

B1

C1

A5

A4

A3

A2

C5

PCIE_RDN0

I

Receiver differential pair (×1 lane)

PCIE_RDP0

PCIE_REFCLKN

PCIE_REFCLKP

PCIE_TDN0

I

PCIE Differential Clock inputs (negative and positive).

100 MHz differential.

I

O

Transmitter differential pair (×1 lane)

PCIE_TDP0

PCIE_PME_L

OD PCI power management event output. Used to

request a change in the device or system power state.

The assertion and deassertion of this signal is

asynchronous to the PCIe reference clock. This signal

has an open-drain output structure, as per the PCI

Bus Local Bus Specification, revision 2.3.

C3

C2

PCIE_TESTP

PCIE_TESTN

–

PCIe test pin

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 112

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

WLAN SDIO Bus Interface

Note: These signals can support alternate functionality depending on package and host interface mode. See

Table 26: “GPIO Alternative Signal Functions,” on page 120 for additional details.

A8

A9

B9

C9

B8

C8

SDIO_CLK

I

SDIO clock input

SDIO_CMD

I/O SDIO command line

I/O SDIO data line 0

I/O SDIO data line 1

I/O SDIO data line 2

I/O SDIO data line 3

SDIO_DATA_0

SDIO_DATA_1

SDIO_DATA_2

SDIO_DATA_3

WLAN HSIC Interface

A7

A6

D7

HSIC_STROBE

HSIC_DATA

RREFHSIC

I/O HSIC Strobe

I/O HSIC Data

I

HSIC reference resistor input. If HSIC is used,

connect this pin to ground via a 51-ohm 5% resistor.

On SDIO designs this pin should not be connected.

WLAN GPIO Interface

Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to support other functions.

See Table 23: “WLAN GPIO Functions and Strapping Options,” on page 119 and Table 26: “GPIO Alternative

Signal Functions,” on page 120 for additional details.

G11

F10

F11

G9

H9

F9

F8

E7

F7

E6

H12

–

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

GPIO_10

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

I/O Programmable GPIO pins

I/O

–

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 113

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

JTAG Interface

D9

JTAG_SEL

I/O JTAG select: pull high to select the JTAG interface. If

the JTAG interface is not used this pin may be left

floating or connected to ground.

Note: See Table 26: “GPIO Alternative Signal

Functions,” on page 120 for the JTAG signal pins.

Clocks

P12

N12

F6

WRF_XTAL_IN

WRF_XTAL_OUT

LPO_IN

I

XTAL oscillator input

O

I

XTAL oscillator output

External sleep clock input (32.768 kHz)

F4

CLK_REQ

O

Reference clock request (shared by BT and WLAN).

If not used, this can be no-connect.

Bluetooth/FM Transceiver

L1

–

BT_RF

O

I

Bluetooth PA output

SFLASH_CLK

BT_SF_CLK

BT_SF_CS_L

BT_SF_MISO

BT_SF_MOSI

FM_RFIN

–

I/O SFLASH_CSN

–

I/O SFLASH master input, slave output

I/O SFLASH master output, slave input

–

H1

–

I

FM radio antenna port

FM radio auxiliary antenna port

FM DAC output 1

FM_RFAUX

FM_AOUT1

FM_AOUT2

I

E1

F1

O

FM DAC output 2

Bluetooth PCM

M6

J4

BT_PCM_CLK

I/O PCM clock; can be master (output) or slave (input)

BT_PCM_IN

I

PCM data input

PCM data output

H4

K6

BT_PCM_OUT

BT_PCM_SYNC

O

I/O PCM sync; can be master (output) or slave (input).

Bluetooth USB Interface

E5

BT_USB_DN

I/O USB (Host) data negative. Negative terminal of the

USB transceiver.

F5

BT_USB_DP

I/O USB (Host) data positive. Positive terminal of the USB

transceiver.

Bluetooth UART

L5

K5

H5

BT_UART_CTS_L

I

O

I

UART clear-to-send. Active-low clear-to-send signal

for the HCI UART interface.

BT_UART_RTS_L

BT_UART_RXD

UART request-to-send. Active-low request-to-send

signal for the HCI UART interface. BT LED control pin.

UART serial input. Serial data input for the HCI UART

interface.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 114

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

BT_UART_TXD

J5

O

UART serial output. Serial data output for the HCI

UART interface.

Bluetooth/FM I²S

I²S clock, can be master (output) or slave (input).

I²S data output

J6

BT_I2S_CLK

I/O

G6

G5

L6

BT_I2S_DO

BT_I2S_DI

BT_I2S_WS

I²S data input

I²S WS; can be master (output) or slave (input).

Bluetooth GPIO

–

BT_GPIO_2

I/O Bluetooth general-purpose I/O

–

BT_GPIO_3

BT_GPIO_4

BT_GPIO_5

K4

–

Miscellaneous

A10

WL_REG_ON

I

Used by PMU to power up or power down the internal

BCM4354 regulators used by the WLAN section.

Also, when deasserted, this pin holds the WLAN

section in reset. This pin has an internal 200 kΩ pull-

down resistor that is enabled by default. It can be

disabled through programming.

D10

BT_REG_ON

I

Used by PMU to power up or power down the internal

BCM4354 regulators used by the Bluetooth/FM

section. Also, when deasserted, this pin holds the

Bluetooth/FM section in reset. This pin has an internal

200 kΩ pull-down resistor that is enabled by default. It

can be disabled through programming.

L4

J3

BT_DEV_WAKE

BT_HOST_WAKE

I/O Bluetooth DEV_WAKE

I/O Bluetooth HOST_WAKE

Integrated Voltage Regulators

B11

B12

A11

SR_VDDBATA5V

SR_VDDBATP5V

SR_VLX

I

Quiet VBAT

Power VBAT

O

CBuck switching regulator output. Refer to Table 43

on page 158 for details of the inductor and capacitor

required on this output.

C12

E12

P11

N10

D11

C11

D12

E11

LDO_VDD1P5

I

LNLDO input

LDO_VDDBAT5V

WRF_XTAL_VDD1P5

WRF_XTAL_VDD1P2

VOUT_LNLDO

I

LDO VBAT.

I

XTAL LDO input (1.35V)

XTAL LDO output (1.2V)

Output of LNLDO

Output of core LDO

Output of BT LDO

Output of 3.3V LDO

O

VOUT_CLDO

VOUT_BTLDO2P5

VOUT_LDO3P3_B

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 115

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

F12

–

VOUT_3P3

O

LDO 3.3V output

Voltage sense pin for LDO 3.3V output

VOUT_3P3_SENSE

Bluetooth Supplies

M1

K1

K3

K2

J1

BT_PAVDD2P5

PWR Bluetooth PA power supply

PWR Bluetooth LNA power supply

PWR Bluetooth IF block power supply

PWR Bluetooth RF PLL power supply

PWR Bluetooth RF power supply

PWR Core supply

BT_LNAVDD1P2

BT_IFVDD1P2

BT_PLLVDD1P2

BT_VCOVDD1P2

BT_VDDIO

K7

FM Transceiver Supplies

G1

–

FM_LNAVCOVDD1P2

PWR FM LNA and VCO 1.2V power supply

PWR FM LNA 1.2V power supply

PWR FM VCO 1.2V power supply

PWR FM PLL 1.2V power supply

PWR FM AUDIO power supply

FM_LNAVDD1P2

FM_VCOVDD1P2

FM_PLLVDD1P2

FM_AUDIOVDD1P2

–

F3

E2

WLAN Supplies

U4

R11

V6

WRF_BUCK_VDD1P5_CORE0

PWR Internal capacitor-less CORE0 LDO supply

PWR Internal capacitor-less CORE1 LDO supply

PWR Synth VDD 3.3V supply

WRF_BUCK_VDD1P5_CORE1

WRF_SYNTH_VBAT_VDD3P3

R3

WRF_PADRV_VBAT_VDD3P3_CO PWR CORE0 PA Driver VBAT supply

RE0

T9

WRF_PADRV_VBAT_VDD3P3_CO PWR CORE1 PA Driver VBAT supply

RE1

T1

WRF_PA5G_VBAT_VDD3P3_COR PWR 5 GHz CORE0 PA 3.3V VBAT supply

E0

V10

R1

V9

WRF_PA5G_VBAT_VDD3P3_COR PWR 5 GHz CORE1 PA 3.3V VBAT supply

E1

WRF_PA2G_VBAT_VDD3P3_COR PWR 2 GHz CORE0 PA 3.3V VBAT supply

E0

WRF_PA2G_VBAT_VDD3P3_COR PWR 2 GHz CORE1 PA 3.3V VBAT supply

E1

T5

T4

WRF_MMD_VDD1P2

WRF_PFD_VDD1P2

PWR 1.2V supply

Miscellaneous Supplies

OTP_VDD33

–

PWR OTP 3.3V supply

B7, D4, VDDC

E9, G10,

PWR 1.2V core supply for WLAN

J8, J12,

L10, M7

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 116

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

VDDIO

E10

PWR 1.8V–3.3V supply for WLAN. Must be directly

connected to PMU_VDDIO and BT_VDDIO on the

PCB.

E4, H3, BT_VDDC

M5

PWR 1.2V core supply for BT

–

VDDIO_PMU

PWR 1.8V–3.3V supply for PMU controls. Must be directly

connected to VDDIO and BT_VDDIO on the PCB.

E8

H11

C7

C6

H7

B3

B2

VDDIO_SD

PWR 1.8V–3.3V supply for SDIO pads

PWR IO supply for RF switch control pads (3.3V)

PWR 1.2V supply for HSIC PLL

VDDIO_RF

HSIC_AVDD12PLL

HSIC_DVDD12

AVDD_BBPLL

PWR 1.2V supply for HSIC digital

PWR Baseband PLL supply

PCIE_PLL_AVDD1P2

PCIE_RXTX_AVDD1P2

PWR 1.2V supply for PCIe PLL

PWR 1.2V supply for PCIE TX and RX

Ground

U6

P4

R8

V4

R12

N2

U7

V2

U12

P3

T8

WRF_VCO_GND1P2

GND VCO/LOGEN ground

WRF_AFE_GND1P2_CORE0

WRF_AFE_GND1P2_CORE1

WRF_BUCK_GND1P5_CORE0

WRF_BUCK_GND1P5_CORE1

WRF_LNA_2G_GND1P2_CORE0

WRF_LNA_2G_GND1P2_CORE1

WRF_LNA_5G_GND1P2_CORE0

WRF_LNA_5G_GND1P2_CORE1

WRF_TX_GND1P2_CORE0

WRF_TX_GND1P2_CORE1

GND CORE0 AFE ground

GND CORE1 AFE ground

GND Internal capacitor-less CORE0 LDO ground

GND Internal capacitor-less CORE1 LDO ground

GND 2 GHz internal CORE0 LNA ground

GND 2 GHz internal CORE1 LNA ground

GND 5 GHz internal CORE0 LNA ground

GND 5 GHz internal CORE1 LNA ground

GND TX CORE0 ground

GND TX CORE1 ground

T3

WRF_PADRV_VBAT_GND3P3_CO GND PAD CORE0 ground

RE0

T10

WRF_PADRV_VBAT_GND3P3_CO GND PAD CORE1 ground

RE1

N11

N3

WRF_XTAL_GND1P2

GND XTAL ground

WRF_RX2G_GND1P2_CORE0

WRF_RX2G_GND1P2_CORE1

WRF_RX5G_GND1P2_CORE0

WRF_RX5G_GND1P2_CORE1

WRF_LOGEN_GND1P2

GND RX 2GHz CORE0 ground

GND RX 2GHz CORE1 ground

GND RX 5GHz CORE0 ground

GND RX 5GHz CORE1 ground

GND LOGEN ground

T7

V3

T12

R6

R5

WRF_LOGENG_GND1P2

GND LOGEN ground

T2, U2

WRF_PA5G_VBAT_GND3P3_COR GND 5 GHz PA CORE0 ground

E0

U10, U11 WRF_PA5G_VBAT_GND3P3_COR GND 5 GHz PA CORE1 ground

E1

Broadcom^®

October 15, 2014 • 4354-DS109-R

BROADCOM CONFIDENTIAL

Page 117

BCM4354 Data Sheet

Signal Descriptions

Table 22: WLBGA Signal Descriptions

Type Description

Ball#

Signal Name

P2, R2

WRF_PA2G_VBAT_GND3P3_COR GND 2 GHz PA CORE0 ground

E0

U8, U9

WRF_PA2G_VBAT_GND3P3_COR GND 2 GHz PA CORE1 ground

E1

T6

V5

U5

WRF_MMD_GND1P2

WRF_CP_GND1P2

WRF_PFD_GND1P2

GND Ground

C10, D3, VSSC

D6, G4,

GND Core ground for WLAN and BT

G8, G12,

L7, L11,

M4

A12

B10

B6

L2

M3

L3

J2

SR_PVSS

GND Power ground

PMU_AVSS

GND Quiet ground

HSIC_AGND12PLL

BT_PAVSS

GND HSIC PLL ground

GND Bluetooth PA ground

GND Bluetooth IF block ground

GND Bluetooth PLL ground

GND Bluetooth VCO ground

GND FM VCO ground

GND FM LNA ground

GND FM PLL ground

GND FM AUDIO ground

GND Baseband PLL ground

GND PCIe ground

BT_IFVSS

BT_PLLVSS

BT_VCOVSS

FM_VCOVSS

FM_LNAVSS

FM_PLLVSS

FM_AUDIOVSS

AVSS_BBPLL

PCIE_AVSS

PCIE_RXTX_AVSS

PCIE_PLL_AVSS

RGND

G2

H2

G3

F2

G7

–

B4

B5

–

GND PCIe ground

GND Ground

–

BTRGND

GND Ground

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 118

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN/BT GPIO Signals and Strapping Options

The pins listed in Table 23 and Table 24 are sampled at power-on reset (POR) to determine the various

operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR.

After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.

Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default

mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kꢀ

resistor or less.

Note: Refer to the reference board schematics for more information.

Table 23: WLAN GPIO Functions and Strapping Options

Pin Name

Default Function Description

GPIO_4

0

1: SPROM is present

0: SPROM is absent (default). Applicable in PCIe Host mode.

Note: In SDIO Host mode, sdioPadVddio is 3.3V while set to 1, and 1.8V

while set to 0.

GPIO_5

0

0: sflash absent (default)

1: sflash present

GPIO_[10, 9, 8]

GPIO_12

[0,0,0]

1

Host interface selection: see Table 25.

1 = HTAvailable (default)

0 = ResourceModeInit is ALPAvailable. On PCBs, use a pull-down and tie

to ALP clock mode.

Table 24: BT GPIO Functions and Strapping Options

Default

Function Description

Pin Name

BT_GPIO4

0

1: BT Serial Flash is present.

0: BT Serial Flash is absent (default)

Table 25: GPIO_[10, 9, 8] Host Interface Selection

GPIO_[10, 9, 8]

Bit Setting

WLAN Host Interface Mode

Bluetooth Mode

000

010

011

SDIO

BTUART or BTUSB;

BT tPorts stand-alone.

HSIC_30D

PCIE

BTUART or BTUSB;

BT tPorts stand-alone

BTUART or BTUSB;

BT tPorts stand-alone

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 119

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

DC Characteristics

Section 14: DC Characteristics

Note: Values in this data sheet are design goals and are subject to change based on the results of

device characterization.

Absolute Maximum Ratings

Caution! The absolute maximum ratings in Table 29 indicate levels where permanent damage to the

device can occur, even if these limits are exceeded for only a brief duration. Functional operation is

not guaranteed under these conditions. Operation at absolute maximum conditions for extended

periods can adversely affect long-term reliability of the device.

Table 29: Absolute Maximum Ratings

Rating

Symbol

Value

Unit

DC supply for VBAT and PA driver supply^a

DC supply voltage for digital I/O

DC supply voltage for RF switch I/Os

DC input supply voltage for CLDO and LNLDO

DC supply voltage for RF analog

DC supply voltage for core

VBAT

–0.5 to +6.0

V

VDDIO

VDDIO_RF

–

–0.5 to 3.9

–0.5 to 1.575

–0.5 to 1.32

–0.5 to 3.63

–0.5

V

VDDRF

VDDC

–

WRF_TCXO_VDD

Maximum undershoot voltage for I/O^b

V_undershoot

Maximum overshoot voltage for I/O^b

Maximum junction temperature

V_overshoot

T_j

VDDIO + 0.5

125

V

°C

a. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V for up to 10 seconds, cumulative

duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V for up to 250 seconds,

cumulative duration over the lifetime of the device, are allowed.

b. Duration not to exceed 25% of the duty cycle.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 125

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Environmental Ratings

The environmental ratings are shown in Table 30.

Table 30: Environmental Ratings

Characteristic

Value

Units

Conditions/Comments

Functional operation^a

Ambient Temperature (T_A)

–30 to +85

°C

Storage Temperature

Relative Humidity

–40 to +125

Less than 60

Less than 85

°C

%

–

Storage

Operation

a. Functionality is guaranteed but specifications require derating at extreme temperatures; see the specification

tables for details.

Electrostatic Discharge Specifications

Proper use of wrist and heel grounding straps is required to discharge static electricity when handling the

BCM4354.

Caution! Electrostatic discharge (ESD) damage can occur if the BCM4354 is mishandled. Always

wear an ESD-preventive wrist or heel ground strap when handling the BCM4354. As with all electrical

devices of this type, take all necessary safety precautions to prevent damage to the equipment. When

not being used, always store the BCM4354 in antistatic packaging.

Table 31: Electrostatic Discharge Specifications

Pin Type Symbol

Condition

ESD Rating

Unit

ESD^a

ESD_HAND_HBM

Human body model contact discharge per

JEDEC EID/JESD22-A114.

WLBGA:

WLCSP:

WLBGA:

WLCSP:

1.k

V

1.5k

300

500

CDM

ESD_HAND_CDM Charged device model contact JEDEC EIA/

JESD22-C101.

V

a. Handling Reference: NQY00083, Section 3.4, Group D9, Table B.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 126

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Recommended Operating Conditions and DC Characteristics

Caution! Functional operation is not guaranteed outside of the limits shown in Table 32, and operation

outside these limits for extended periods can adversely affect long-term reliability of the device.

Table 32: Recommended Operating Conditions and DC Characteristics

Value

Parameter

Symbol

Minimum Typical Maximum Unit

3.0^a

1.14

5.25^b

1.26

1.98

DC supply voltage for VBAT

VBAT

–

V

DC supply voltage for core

VDD

1.2

1.8

V

DC supply voltage for RF blocks in chip

DC supply voltage for TCXO input buffer

VDDRF

WRF_TCXO_VD 1.62

D

DC supply voltage for digital I/O

VDDIO,

VDDIO_SD

1.62

–

3.63

V

DC supply voltage for RF switch I/Os

External TSSI input

VDDIO_RF

TSSI

3.13

0.15

0.4

3.3

–

3.46

0.95

0.7

V

Internal POR threshold

Vth_POR

–

SDIO Interface I/O Pins

For VDDIO_SD = 1.8V:

Input high voltage

VIH

VIL

1.27

–

V

Input low voltage

0.58

–

Output high voltage @ 2 mA

Output low voltage @ 2 mA

For VDDIO_SD = 3.3V:

Input high voltage

VOH

VOL

1.40

–

0.45

VIH

VIL

0.625 ×

VDDIO

–

V

Input low voltage

–

0.25 ×

VDDIO

Output high voltage @ 2 mA

Output low voltage @ 2 mA

VOH

VOL

0.75 ×

VDDIO

–

0.125 ×

VDDIO

Other Digital I/O Pins

For VDDIO = 1.8V:

Input high voltage

VIH

VIL

0.65 ×

VDDIO

–

V

Input low voltage

–

0.35 ×

VDDIO

Output high voltage @ 2 mA

VOH

VDDIO –

0.45

–

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 127

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Recommended Operating Conditions and DC Characteristics

Table 32: Recommended Operating Conditions and DC Characteristics (Cont.)

Value

Parameter

Output low voltage @ 2 mA

Symbol

Minimum Typical Maximum Unit

VOL

–

0.45

V

For VDDIO = 3.3V:

Input high voltage

VIH

VIL

2.00

–

V

Input low voltage

0.80

–

Output high voltage @ 2 mA

VOH

VDDIO –

0.4

Output low Voltage @ 2 mA

VOL

–

0.40

V

RF Switch Control Output Pins^c

For VDDIO_RF = 3.3V:

Output high voltage @ 2 mA

VOH

VDDIO –

0.4

–

V

Output low voltage @ 2 mA

Input capacitance

VOL

C_IN

–

0.40

5

V

pF

a. The BCM4354 is functional across this range of voltages. Optimal RF performance specified in the data sheet,

however, is guaranteed only for 3.13V < VBAT < 4.8V.

b. The maximum continuous voltage is 5.25V. Voltage transients up to 6.0V for up to 10 seconds, cumulative

duration over the lifetime of the device, are allowed. Voltage transients as high as 5.5V for up to 250 seconds,

cumulative duration over the lifetime of the device, are allowed.

c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 128

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth RF Specifications

Section 15: Bluetooth RF Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of

device characterization.

Unless otherwise stated, limit values apply for the conditions specified in Table 30: “Environmental Ratings,” on

page 126 and Table 32: “Recommended Operating Conditions and DC Characteristics,” on page 127. Typical

values apply for an ambient temperature of +25°C.

Figure 35: RF Port Location for Bluetooth Testing

BCM4354

RF Switch

(0.5 dB Insertion Loss)

WLAN Tx

BT Tx

Filter

WLAN/BT Rx

Antenna

Port

RF Port

Chip

Port

Note: All Bluetooth specifications are measured at the chip port unless otherwise specified.

Table 33: Bluetooth Receiver RF Specifications

Parameter

Conditions

Minimum Typical

Maximum Unit

Note: The specifications in this table are measured at the chip port output unless otherwise specified.

General

Frequency range

RX sensitivity

–

2402

–

2480

MHz

dBm

GFSK, 0.1% BER, 1 Mbps –

–93.5

–95.5

–

/4–DQPSK, 0.01% BER,

2 Mbps

–

8–DPSK, 0.01% BER,

3 Mbps

–89.5

–

dBm

Input IP3

–

–16

–

dBm

Maximum input at antenna

–20

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 129

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth RF Specifications

Table 33: Bluetooth Receiver RF Specifications (Cont.)

Parameter

Conditions

Minimum Typical

Maximum Unit

RX LO Leakage

2.4 GHz band

–

–90.0

–80.0

dBm

Interference Performance^a

C/I co-channel

GFSK, 0.1% BER

–

8

11

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

–7

0

–38

–56

–31

–46

–30

–40

–9

C/I  3 MHz adjacent channel GFSK, 0.1% BER

C/I image channel GFSK, 0.1% BER

C/I 1 MHz adjacent to image GFSK, 0.1% BER

channel

–20

C/I co-channel

/4–DQPSK, 0.1% BER

–

9

13

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

/4–DQPSK, 0.1% BER

–11

–39

–55

–23

–43

0

–30

–40

–7

C/I  3 MHz adjacent channel /4–DQPSK, 0.1% BER

C/I image channel /4–DQPSK, 0.1% BER

C/I 1 MHz adjacent to image /4–DQPSK, 0.1% BER

channel

–20

C/I co-channel

8–DPSK, 0.1% BER

–

17

21

5

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

–4

–37

–53

–16

–37

–25

–33

0

C/I  3 MHz adjacent channel 8–DPSK, 0.1% BER

C/I Image channel 8–DPSK, 0.1% BER

C/I 1 MHz adjacent to image 8–DPSK, 0.1% BER

channel

–13

Out-of-Band Blocking Performance (CW)

30–2000 MHz

0.1% BER

–

–10.0

–27

–

dBm

2000–2399 MHz

2498–3000 MHz

3000 MHz–12.75 GHz

–27

–10.0

Out-of-Band Blocking Performance, Modulated Interferer

GFSK (1 Mbps)^b

698–716 MHz

776–849 MHz

824–849 MHz

880–915 MHz

1710–1785 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–13.5

–13.8

–13.5

–14.3

–13.1

–18.1

–

dBm

WCDMA

GSM1800

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 130

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth RF Specifications

Table 33: Bluetooth Receiver RF Specifications (Cont.)

Parameter

Conditions

Minimum Typical

Maximum Unit

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD–SCDMA

WCDMA

Band 7

–

–17.4

–19.4

–18.8

–19.7

–19.6

–20.4

–30.5

–

dBm

2500–2570 MHz^c

2300–2400 MHz^d

2570–2620 MHz^e

2545–2575 MHz^f

Band 40

Band 38

XGP Band

–

–34.0

–30.8

–29.5

–

dBm

DPSK (2 Mbps)^b

π/4

698–716 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–9.8

–

dBm

776–794 MHz

–9.7

824–849 MHz

–10.7

–11.4

–10.4

–10.2

–15.8

–15.4

–16.6

–16.4

–17.9

–16.8

–18.6

–20.4

–31.9

824–849 MHz

880–915 MHz

WCDMA

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD-SCDMA

WCDMA

Band 7

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

2500–2570 MHz^c

2300–2400 MHz^d

2570–2620 MHz^e

2545–2575 MHz^f

Band 40

Band 38

XGP Band

–

–35.3

–31.8

–31.1

–

dBm

8DPSK (3 Mbps)^b

698–716 MHz

776–794 MHz

824–849 MHz

880–915 MHz

WCDMA

GSM850

WCDMA

E-GSM

–

–12.6

–12.7

–13.7

–12.8

–12.6

–

dBm

WCDMA

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 131

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth RF Specifications

Table 33: Bluetooth Receiver RF Specifications (Cont.)

Parameter

Conditions

Minimum Typical

Maximum Unit

1710–1785 MHz

1850–1910 MHz

1880–1920 MHz

1920–1980 MHz

2010–2025 MHz

2500–2570 MHz

GSM1800

WCDMA

GSM1900

WCDMA

TD-SCDMA

WCDMA

TD-SCDMA

WCDMA

Band 7

–

–18.1

–17.4

–19.1

–18.6

–19.3

–18.9

–20.4

–21.4

–31.0

–

dBm

2500–2570 MHz^c

2300–2400 MHz^d

2570–2620 MHz^e

2545–2575 MHz^f

Spurious Emissions

Band 40

Band 38

XGP Band

–

–34.5

–31.2

–30.0

–

dBm

30 MHz–1 GHz

1–12.75 GHz

–

–95

–62

–47

–

dBm

–70

dBm

851–894 MHz

925–960 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

–147

dBm/Hz

–

a. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined

in the version 4.1 specification.

b. Bluetooth reference level for the wanted signal at the Bluetooth Chip port = at 3 dB desense for each data rate.

c. Interferer: 2560 MHz, BW=10 MHz; measured at 2480 MHz.

d. Interferer: 2360 MHz, BW=10 MHz; measured at 2402 MHz.

e. Interferer: 2380 MHz, BW=10 MHz; measured at 2480 MHz.

f. Interferer: 2355 MHz, BW=10 MHz; measured at 2480 MHz.

Table 34: Bluetooth Transmitter RF Specifications

Parameter

Conditions

Minimum Typical Maximum Unit

Note: The specifications in this table are measured at the Chip port output unless otherwise specified.

General

Frequency range

2402

–

2480

MHz

dBm

dB

Basic rate (GFSK) TX power at Bluetooth

QPSK TX power at Bluetooth

8PSK TX power at Bluetooth

–

2

13.0

10.0

4

–

8

Power control step

–

Note: Output power is with TCA and TSSI enabled.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 132

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth RF Specifications

Table 34: Bluetooth Transmitter RF Specifications (Cont.)

Conditions Minimum Typical Maximum Unit

Parameter

GFSK In-Band Spurious Emissions

–20 dBc BW

–

0.93

1

MHz

EDR In-Band Spurious Emissions

1.0 MHz < |M – N| < 1.5 MHz

1.5 MHz < |M – N| < 2.5 MHz

M – N = the frequency range for –

–38

–31

–43

–26.0

–20.0

–40.0

dBc

which the spurious emission is

measured relative to the

–

dBm

|M – N|  2.5 MHz^a

–

transmit center frequency.

Out-of-Band Spurious Emissions

–36.0 ^b,c

30 MHz to 1 GHz

–

dBm

–30.0 ^b,d,e

–47.0

1 GHz to 12.75 GHz

–

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

–

dBm

–47.0

GPS Band Spurious Emissions

Spurious emissions

–

–103

–

dBm

Out-of-Band Noise Floor^f

65–108 MHz

FM RX

–

–147

–146

–145

–144

–141

–140

–

dBm/Hz

dBm

776–794 MHz

CDMA2000

cdmaOne, GSM850

E-GSM

869–960 MHz

925–960 MHz

1570–1580 MHz

1805–1880 MHz

1930–1990 MHz

2110–2170 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

GPS

GSM1800

GSM1900, cdmaOne, WCDMA –

WCDMA

Band 7

–

Band 40

Band 38

XGP Band

dBm

a. The typical number is measured at ± 3 MHz offset.

b. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification.

c. The spurious emissions during Idle mode are the same as specified in Table 34 on page 132.

d. Specified at the Bluetooth Antenna port.

e. Meets this specification using a front–end band–pass filter.

f. Transmitted power in cellular and FM bands at the Bluetooth Antenna port. See Figure 35 on page 129 for

location of the port.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 133

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth RF Specifications

Table 35: Local Oscillator Performance

Minimum Typical

Parameter

Maximum Unit

LO Performance

Lock time

–

72

–

s

Initial carrier frequency tolerance

±25

±75

kHz

Frequency Drift

DH1 packet

DH3 packet

DH5 packet

Drift rate

–

±8

5

±25

±40

20

kHz

kHz/50 µs

Frequency Deviation

00001111 sequence in payload^a

140

115

–

155

140

1

175

–

kHz

MHz

10101010 sequence in payload^b

Channel spacing

–

a. This pattern represents an average deviation in payload.

b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations.

Table 36: BLE RF Specifications

Parameter

Conditions

Minimum Typical

Maximum Unit

Frequency range

RX sense^a

–

2402

–

2480

–

MHz

dBm

GFSK, 0.1% BER, 1 Mbps

–95.5

TX power^b

–

8.5

–

dBm

Mod Char: delta F1 average –

225

255

–

275

–

kHz

%

Mod Char: delta F2 max.^c

–

99.9

Mod Char: ratio

–

0.8

0.95

–

%

a. Dirty TX is On.

b. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The

output is capped at 12 dBm out. The BLE TX power at the antenna port cannot exceed the 10 dBm specification

limit.

c. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 134

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

FM Receiver Specifications

Section 16: FM Receiver Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of

device characterization.

Unless otherwise stated, limit values apply for the conditions specified inTable 30: “Environmental Ratings,” on

page 126 and Table 32: “Recommended Operating Conditions and DC Characteristics,” on page 127. Typical

values apply for an ambient temperature +25°C.

Table 37: FM Receiver Specifications

Typica

Parameter

Conditions^a

Minimum l

Maximum Units

RF Parameters

Operating frequency^b

Sensitivity^c

Frequencies inclusive

65

–

108

–

MHz

FM only

SNR ≥ 26 dB

0

dBµV

EMF

–

1

–

µV EMF

dBuV

dB

–6

51

Receiver adjacent

channel selectivity^c,d

Measured for 30 dB SNR at the audio

output.

Wanted Signal: 23 dBµV EMF (14.1 µV

EMF), at ± 200 kHz.

At ± 400 kHz

–

62

53

–

dB

Intermediate signal plus Vin = 20 dBµV EMF (10 µV EMF)

noise-to-noise ratio (S+N)/

45

N, stereo^c

Intermodulation

performance^c,d

Blocker level increased until desired at

30 dB SNR

Wanted Signal: 33 dBµV EMF (45 µV

–

55

–

dBc

EMF)

Modulated Interferer: At f_Wanted

±400 kHz and ±4 MHz

CW Interferer: At f_Wanted± 800 kHz and

±8 MHz

AM suppression, mono^c

Vin = 23 dBµV EMF (14.1 µV EMF)

AM at 400 Hz with m = 0.3

No A-weighted or any other filtering

applied.

40

–

dB

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 135

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

FM Receiver Specifications

Table 37: FM Receiver Specifications (Cont.)

Typica

Minimum l Maximum Units

Parameter

RDS

Conditions^a

RDS sensitivity^e,f

RDS deviation = 1.2 kHz

RDS deviation = 2 kHz

–

16

–

dBµV

EMF

–

6.3

10

12

–

µV EMF

dBuV

dBµV

EMF

–

4

6

–

µV EMF

dBuV

RDS selectivity^f

Wanted Signal: 33 dBµV EMF (45 µV EMF), 2 kHz RDS deviation

Interferer: ꢁf = 40 kHz, fmod = 1 kHz

± 200 kHz

± 300 kHz

± 400 kHz

–

49

52

–

dB

kꢀ

pF

–

RF input impedance

1.5

2.5

–

Antenna tuning capacitor –

SNR > 26 dB

–

30

113

Maximum input level^c

–

dBµV

EMF

–

446

107

–55

mV EMF

dBuV

RF conducted emissions Local oscillator breakthrough measured –

dBm

(measured into a 50ꢀ

on the reference port

load)

869–894 MHz, 925–960 MHz,

1805–1880 MHz, 1930–1990 MHz.

GPS

–

–90

dBm

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 136

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

FM Receiver Specifications

Table 37: FM Receiver Specifications (Cont.)

Typica

Minimum l

Parameter

Conditions^a

Maximum Units

RF blocking levels at the GSM850, E-GSM (std), BW = 0.2 MHz,

FM antenna input 40 dB 824–849 MHz

–

7

–

dBm

SNR (assumes a 50ꢀ at 880–915 MHz

the radio input and

excludes spurs)

GSM850, E-GSM (edge),

BW = 0.2 MHz,

824–849 MHz

880–915 MHz

–

–1

–

dBm

GSM DCS 1800, PCS 1900 (std/edge),

BW = 0.2 MHz,

1710–1785 MHz

12

–

dBm

1850–1910 MHz

WCDMA: II(I), III(IV, X),

BW = 5 MHz,

1850–1980 MHz (1920–1980 MHz),

1710–1785 MHz (1710–1755 MHz,

1710–1770 MHz)

WCDMA: V(VI), VIII, XII, XIII, XIV,

BW = 5 MHz,

824–849 MHz (830–840 MHz),

–

5

0

–

dBm

880–915 MHz

CDMA2000, cdmaOne, BW = 1.25 MHz,

824–849 MHz,

887–925 MHz,

776–794 MHz

CDMA2000, cdmaOne, BW = 1.25 MHz,

1850–1910 MHz,

12

1750–1780 MHz,

1920–1980 MHz

Bluetooth, BW = 1 MHz,

2402–2480 MHz

–

11

6

–

dBm

IEEE 802.11g/b, BW = 20 MHz,

2400–2483.5 MHz

IEEE 802.11a, BW = 20 MHz,

4915–5825 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

Band 7

–

11

–

dBm

Band 40

Band 38

XGP Band

11

Tuning

Frequency step

Settling time

–

10

–

kHz

µs

Single-frequency switch in any direction –

to a frequency within the bands 88–

108 MHz or 76–90 MHz. Time measured

to within 5 kHz of the final frequency.

150

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 137

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

FM Receiver Specifications

Table 37: FM Receiver Specifications (Cont.)

Typica

Minimum l Maximum Units

Parameter

Conditions^a

Search time

Total time for an automatic search to

sweep from 88–108 MHz or 76–90 MHz

(and reverse direction) assuming no

channels are found.

–

8

sec

General Audio

Audio output level^g

Maximum audio output

level^h

–

–14.5

–

–12.5

0

dBFS

Audio DAC output level^g

Maximum DAC audio

output level^h

–

72

–

88

–

mV rms

333

Audio DAC output level

differenceⁱ

–

–1

–

1

dB

Left and right AC mute

FM input signal fully muted with DAC

enabled

60

80

–

dB

–

Left and right hard mute FM input signal fully muted with DAC

disabled

Soft mute attenuation and Muting is performed dynamically

start level

proportional to the FM wanted input

signal C/N. The muting characteristic is

fully programmable. Refer to “Audio

Features” on page 63 for further details.

Maximum signal plus

noise-to-noise ratio

–

69

64

–

dB

%

(S + N)/N, mono ⁱ

Maximum signal plus

noise-to-noise ratio

(S + N)/N, stereo^g

–

Total harmonic distortion, Vin = 66 dBµV EMF (2 mV EMF),

0.8

mono

∆f = 75 kHz, fmod = 400 Hz

∆f = 75 kHz, fmod = 1 kHz

∆f = 75 kHz, fmod = 3 kHz

∆f = 100 kHz, fmod = 1 kHz

–

0.8

1.0

1.5

%

Total harmonic distortion, Vin = 66 dBµV EMF (2 mV EMF)

stereo

∆f = 67.5 kHz, fmod = 1 kHz, ꢁf

Pilot = 7.5 kHz, L = R

Audio spurious productsⁱ

Range from 300 Hz to 15 kHz, with

respect to 1 kHz tone

–

–60

–

dBc

kHz

Hz

Audio bandwidth, upper (– Vin = 66 dBµV EMF (2 mV EMF)

15

–

3 dB point)

∆f = 8 kHz, for 50 µs

Audio bandwidth, lower (–

3 dB point)

20

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 138

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

FM Receiver Specifications

Table 37: FM Receiver Specifications (Cont.)

Typica

Minimum l Maximum Units

Parameter

Conditions^a

Audio in-band ripple

100 Hz to 13 kHz,

Vin = 66 dBµV EMF (2 mV EMF)

–0.5

–

0.5

dB

∆f = 8 kHz, for 50 µs

De-emphasis time

constant tolerance

With respect to 50 and 75 µs

–

3

–

±5

83

%

RSSI range

With 1 dB resolution and ± 5 dB

accuracy at room temp

dBµV

EMF

1.41

–3

–

14.1m

77

µV EMF

dBuV

Stereo Decoder

Stereo channel separation Forced Stereo mode

Vin = 66 dBµV EMF (2 mV EMF),

–

48

–

dB

∆f = 67.5 kHz, fmod = 1 kHz,

ꢁf Pilot = 6.75 kHz

R = 0, L = 1

Mono stereo blend and

switching

Blending and switching is dynamically proportional to the FM wanted input signal C/

N. The blending and switching characteristics are fully programmable. Refer to

“Audio Features” on page 63 for further details.

Pilot suppression

Vin = 66 dBµV EMF (2 mV EMF),

∆f = 75 kHz, fmod = 1 kHz

46

–

dB

Pause detection

Audio level at which a

pause is detected

Relative to 1 kHz tone, ∆f = 22.5 kHz

Four values in 3 dB steps

Four values

–

–21

20

–12

40

dB

ms

Audio pause duration

a. Following conditions are applied to all relevant tests unless otherwise indicated: Pre-emphasis and de-emphasis

of 50 us, R = L for mono, DAC Load ≥ 20 kꢀ, BAF = 300 Hz to 15 kHz, and A-weighted filtering applied.

b. Contact Broadcom regarding applications that operate between 65 and 76 MHz.

c. Wanted Signal: ∆f = 22.5 kHz, and fmod = 1 kHz.

d. Interferer: ꢁf = 22.5 kHz, and fmod = 1 kHz.

e. RDS sensitivity numbers are for 87.5–108 MHz only.

f. Vin = ꢁf = 32 kHz, fmod = 1 kHz, ꢁf Pilot = 7.5 kHz, and 95% of blocks decoded with no errors after correction.

g. Vin = 66 dBµV EMF (2 mV EMF), ∆f = 22.5 kHz, fmod = 1 kHz, and ꢁf Pilot = 6.75 kHz.

h. Vin = 66 dBµV EMF (2 mV EMF), ∆f = 100 kHz, fmod = 1 kHz, and ∆f Pilot = 6.75 kHz.

i. Vin = 66 dBµV EMF (2 mV EMF), ∆f = 22.5 kHz, and fmod = 1 kHz.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 139

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN RF Specifications

Section 17: WLAN RF Specifications

Introduction

The BCM4354 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the

5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radios.

Note: Values in this section of the data sheet are design goals and are subject to change based on the

results of device characterization.

Unless otherwise stated, limit values apply for the conditions specified inTable 30: “Environmental Ratings,” on

page 126 and Table 32: “Recommended Operating Conditions and DC Characteristics,” on page 127. Typical

values apply for an ambient temperature +25°C.

Figure 36: Port Locations (Applies to 2.4 GHz and 5 GHz)

BCM4354

RF Switch

(0.5 dB Insertion Loss)

WLAN Tx

BT Tx

Filter

WLAN/BT Rx

Antenna

Port

RF Port

Chip

Port

2.4 GHz Band General RF Specifications

Table 38: 2.4 GHz Band General RF Specifications

Item

Condition

Including TX ramp down –

Including TX ramp up

Minimum Typical

Maximum Unit

TX/RX switch time

RX/TX switch time

–

5

µs

–

2

Power-up and power-down ramp

time

DSSS/CCK modulations –

< 2

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 140

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Note: The values in Table 39 are specified at the RF port unless otherwise noted.

Table 39: WLAN 2.4 GHz Receiver Performance Specifications

Parameter

Condition/Notes

Min.

Typ. Max.

Unit

Frequency range

RX sensitivity IEEE

802.11b^a

–

2400

–

2500

–

MHz

1 Mbps DSSS

2 Mbps DSSS

5.5 Mbps DSSS

11 Mbps DSSS

–96.4

–94.5

–91.7

–89.4

–93.5

–92.1

–91.2

–88.6

–85.3

–82

dBm

–

dBm

–

dBm

–

dBm

SISO RX sensitivity IEEE 6 Mbps OFDM

802.11g

–

dBm

9 Mbps OFDM

–

dBm

(10% PER for 1024 octet

PSDU)^a

12 Mbps OFDM

–

dBm

18 Mbps OFDM

–

dBm

24 Mbps OFDM

36 Mbps OFDM

–

dBm

–

dBm

48 Mbps OFDM

–

–77.3

–75.8

–94.5

–94

–

dBm

54 Mbps OFDM

–

dBm

MIMO RX sensitivity IEEE 6 Mbps OFDM

–

dBm/core

802.11g

9 Mbps OFDM

–

(10% PER for 1024 octet

PSDU)^a

12 Mbps OFDM

–

–93.2

–91.6

–88.3

–85

–

18 Mbps OFDM

–

24 Mbps OFDM

–

36 Mbps OFDM

48 Mbps OFDM

–

–80.3

–78.8

–

54 Mbps OFDM

–

SISO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11n

MCS0

–

–93

–

dBm

(10% PER for 4096 octet

MCS1

–90.7

–88.2

–85.1

–81.5

–76.9

–75.3

–73.7

PSDU)^a,b

MCS2

Defined for default

parameters: GF, 800 ns GI,

and non–STBC.

MCS3

MCS4

MCS5

MCS6

MCS7

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 141

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 39: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ. Max.

Unit

MIMO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11n

MCS0

–

–94.5

–93.7

–91.2

–88.1

–84.5

–79.9

–78.3

–76.7

–93

–

dBm/core

(10% PER for 4096 octet

MCS1

PSDU)^a,b

MCS2

Defined for default

parameters: GF, 800 ns GI,

and non–STBC.

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS15

–73.7

SISO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11n

MCS0

–

–90.8

–87.9

–85.5

–82

–

dBm

(10% PER for 4096 octet

MCS1

PSDU)^a,b

MCS2

Defined for default

parameters: GF, 800 ns GI,

and non–STBC.

MCS3

MCS4

MCS5

MCS6

MCS7

–78.9

–74.2

–72.7

–71.3

MIMO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11n

MCS0

–

–92.3

–90.9

–88.5

–85

–

dBm/core

(10% PER for 4096 octet

MCS1

PSDU)^a,b

MCS2

Defined for default

parameters: GF, 800 ns GI,

and non–STBC.

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS15

–81.9

–77.2

–75.7

–74.3

–90.8

–71.3

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 142

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 39: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ. Max.

Unit

SISO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

–

–92.3

–89.9

–88.1

–84.9

–81.4

–76.9

–75.3

–73.6

–69.2

–

dBm

(10% PER for 4096 octet

MCS1, Nss 1

PSDU)^a,b

MCS2, Nss 1

Defined for default

MCS3, Nss 1

parameters: GF, 800 ns GI,

and non–STBC

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MIMO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

–

–93.8

–92.9

–91.1

–87.9

–84.4

–79.9

–78.3

–76.6

–72.2

–92

–

dBm/core

(10% PER for 4096 octet

MCS1, Nss 1

PSDU)^a,b

MCS2, Nss 1

Defined for default

MCS3, Nss 1

parameters: GF, 800 ns GI,

and non–STBC

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS0, Nss 2

MCS8, Nss 2

–68.1

SISO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

–

–89.5

–87

–

dBm

(10% PER for 4096 octet

MCS1, Nss 1

PSDU)^a,b

MCS2, Nss 1

Defined for default

–85.2

–82

MCS3, Nss 1

parameters: GF, 800 ns GI,

and non–STBC.

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

–78.8

–74.3

–72.7

–71.3

–66.9

–65.6

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 143

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 39: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ. Max.

Unit

MIMO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

–

–91

–

dBm/core

dBm

(10% PER for 4096 octet

MCS1, Nss 1

–90

PSDU)^a,b

MCS2, Nss 1

Defined for default

–88.2

–85

MCS3, Nss 1

parameters: GF, 800 ns GI,

and non–STBC.

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

MCS0, Nss 2

MCS9, Nss 2

–81.8

–77.3

–75.7

–74.3

–69.9

–68.6

–89

–64.2

–75.4

–72.7

–69.4

–72.8

–68.5

–67.3

SISO RX sensitivity IEEE MCS7, Nss 1

802.11ac 20/40/80 MHz

channel spacing with LDPC

20 MHz

40 MHz

MCS8, Nss 1

dBm

MCS9, Nss 1

dBm

(10% PER for 4096 octet

PSDU)^a,bat WLAN RF port.

Defined for default

parameters: GF, 800 ns GI,

LDPC coding, and non–

STBC.

MCS7, Nss 1

dBm

MCS8, Nss 1

MCS9, Nss 1

dBm

MIMO RX sensitivity IEEE MCS7, Nss 2

20 MHz

40 MHz

–

–74

–

dBm/core

802.11ac 20/40/80 MHz

channel spacing with LDPC

MCS8, Nss 2

–71.2

–68.0

–71.8

–67

MCS9, Nss 2

(10% PER for 4096 octet

PSDU)^a,bat WLAN RF port.

MCS7, Nss 2

MCS8, Nss 2

MCS9, Nss 2

Defined for default

parameters: GF, 800 ns GI,

LDPC coding, and non–

STBC.

–65.5

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 144

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 39: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ. Max.

Unit

Blocking level for 3dB RX 776–794 MHz

CDMA2000

cdmaOne

–8

–24

–25

–

dBm

sensitivity degradation

(without external filtering)^c

824–849 MHz^d

–24.5

824–849 MHz^d

880–915 MHz

GSM850

–16.5

–15

–

dBm

E–GSM

–2

–16

–18

–19

–26

–28.5

–45

–50

–45

–

dBm

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

2500–2570 MHz

2300–2400 MHz

2570-2620 MHz

2545-2575 MHz

GSM1800

cdmaOne

WCDMA

Band 7

–17

–21

–32

–29

–32

–45

–50

–45

–80

Band 40

Band 38

XGP band

In-band static CW jammer RX PER < 1%, 54 Mbps OFDM,

immunity

1000 octet PSDU for:

(fc – 8 MHz < fcw < + 8 MHz)

(RxSense + 23 dB < Rxlevel < max. input

level)

Input In–Band IP3

Maximum LNA gain

–

–15.5

–

dBm

MHz

Minimum LNA gain

–

–1.5

–

Maximum Receive Level

@ 2.4 GHz

@ 1, 2 Mbps (8% PER, 1024 octets)

–3.5

–

@ 5.5, 11 Mbps (8% PER, 1024 octets) –9.5

@ 6–54 Mbps (10% PER, 1024 octets) –9.5

–

@ MCS0–7 rates (10% PER, 4095 octets) –9.5

@ MCS8–9 rates (10% PER, 4095 octets) –11.5

–

LPF 3 dB Bandwidth

–

9

–

36

Adjacent channel rejection– Desired and interfering signal 30 MHz apart

DSSS

1 Mbps DSSS

2 Mbps DSSS

–74 dBm

35

–

dB

(Difference between

interfering and desired

signal at 8% PER for 1024

octet PSDU with desired

signal level as specified in

Condition/Notes)

Desired and interfering signal 25 MHz apart

5.5 Mbps DSSS

11 Mbps DSSS

–70 dBm

35

–

dB

Adjacent channel rejection– 6 Mbps OFDM

–79 dBm

–78 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

16

15

13

11

8

–

dB

OFDM

9 Mbps OFDM

(difference between

interfering and desired

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

signal (25 MHz apart) at

10% PER for 1024 octet

PSDU with desired signal

level as specified in

4

0

Condition/Notes)

–1

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 145

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Receiver Performance Specifications

Table 39: WLAN 2.4 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ. Max.

Unit

Adjacent channel rejection MCS0

–79 dBm

–76 dBm

–74 dBm

–71 dBm

–67 dBm

–63 dBm

–62 dBm

–61 dBm

–59 dBm

–57 dBm

–82 dBm

–80 dBm

–77 dBm

–74 dBm

–70 dBm

–66 dBm

–65 dBm

–64 dBm

–59 dBm

–57 dBm

–

16

13

11

8

–

5

8

13

–

dB

MCS0–9 (Difference

between interfering and

desired signal (25 MHz

MCS1

–

MCS2

–

apart) at 10% PER for 4096

octet PSDU with desired

signal level as specified in

Condition/Notes)

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS9

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS9

–

4

–

0

–

–1

–2

–4

–6

–

IEEE 802.11ac Adjacent

channel rejection MCS0–9

(Difference between

interfering and desired

signal at 10% PER for 4096

octet PSDU with desired

signal level as specified in

Condition/Notes)

–

Maximum receiver gain

Gain control step

–

95

3

–

RSSI accuracy^e

Range –90 dBm to –30 dBm

Range above –30 dBm

–5

–8

10

–

Return loss

Zo = 50ꢀ, across the dynamic range

At maximum gain

11.5

4

Receiver cascaded noise

figure

General spurs

1–18 GHz

–

–60

dBm/MHz

a. Derate by 1.5 dB for 55°C to 70°C.

b. Sensitivity degradations for alternate settings in MCS modes. MM: 0.5 dB drop, and SGI: 2 dB drop.

c. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band

for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country.

d. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic

signals (3 × 824 MHz) falling within band.)

e. The minimum and maximum values shown have a 95% confidence level.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 146

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Transmitter Performance Specifications

Note: The values in Table 40 are specified at the RF port unless otherwise noted.

Table 40: WLAN 2.4 GHz Transmitter Performance Specifications

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

Frequency range

–

2400

–

2500

MHz

Transmitted power in

cellular and FM bands at 18

dBm, 100% duty cycle, 1

Mbps CCK^a

76-108 MHz

776-794 MHz

869-960 MHz

FM RX

–

–149

–162

–

dBm/Hz

cdmaOne,

GSM850

925-960 MHz

E-GSM

GPS

–

–162

–152

-142

–143

–

dBm/Hz

1570-1580 MHz

1805-1880 MHz

1930-1990 MHz

GSM1800

GSM1900,

cdmaOne,

cdmaOne

2110-2170 MHz

2500-2570 MHz

2300-2400 MHz

2570-2620 MHz

2545-2575 MHz

WCDMA

Band 7

–

–128

–92

–

dBm/Hz

Band 40

Band 38

XGP Band

–95

–110

–18

2^ndharmonic

Harmonic level (at 18 dBm 4.8-5.0 GHz

with 100% duty cycle)

7.2-7.5 GHz

^rdharmonic

–

–20

–

dBm/Hz

3

–

General spurs (at 18 dBm 1–18 GHz

with 100% duty cycle)

–60

dBm/MHz

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 147

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 2.4 GHz Transmitter Performance Specifications

Table 40: WLAN 2.4 GHz Transmitter Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

–

EVM Does Not Exceed

TX power at RF port for

highest power level setting

at 25°C with spectral mask

and EVM compliance^b

802.11b

–9 dB

18

19.5

–

dBm

(DSSS/CCK)

OFDM, BPSK

OFDM, QPSK

–8 dB

18

19

18

17

–

dBm

–13 dB

18

OFDM, 16-QAM –19 dB

OFDM, 64-QAM –25 dB

(R = 3/4)

16.5

15.5

OFDM, 64-QAM –28 dB

(R = 5/6)

14.5

16

–

dBm

OFDM, 256-QAM –30 dB

(R = 3/4, VHT20)

13.5

12

15

13.5

0.45

–

dBm

OFDM, 256-QAM –32 dB

(R = 5/6, VHT20)

Phase noise

37.4 MHz Crystal, Integrated from –

10 kHz to 10 MHz

Degrees

dB

TX power control dynamic

range

–

10

Closed-loop TX power

Across full temperature and

–

±1.5

dB

variation at highest power voltage range. Applies across 10

level setting

dBm to 20 dBm output power

range.

Carrier suppression

Gain control step

–

15

–

dBc

dB

0.25

6

Return loss at chip port TX Zo = 50ꢀ

–

dB

a. The cellular standards listed only indicate the typical usages of that band in some countries: other standards

may also be used within those bands

b. Derate by 1.5 dB for temperatures higher than 55°C, or supply voltages lower than 3.0V. Derate by 3.0 dB for

supply voltages of lower than 2.7V, or supply voltages lower than 3.0V at temperatures higher than 55°C.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 148

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Note: The values in Table 41 on page 149 are specified at the RF port unless otherwise noted.

Table 41: WLAN 5 GHz Receiver Performance Specifications

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

Frequency range

–

4900

–

5845

–

MHz

SISO RX sensitivity IEEE 6 Mbps OFDM

802.11a

–92.5

–91.1

–90.2

–87.6

–84.3

–81

dBm

9 Mbps OFDM

–

dBm

(10% PER for 1000 octet

PSDU)^a

12 Mbps OFDM

–

dBm

18 Mbps OFDM

–

dBm

24 Mbps OFDM

36 Mbps OFDM

–

dBm

–

dBm

48 Mbps OFDM

–

–76.3

–74.8

–93.5

–93

–

dBm

54 Mbps OFDM

–

dBm

MIMO RX sensitivity IEEE 6 Mbps OFDM

–

dBm/core

802.11a

9 Mbps OFDM

–

(10% PER for 1024 octet

PSDU)^a,b

12 Mbps OFDM

–

–92.2

–90.6

–87.3

–84

–

18 Mbps OFDM

–

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

–

–79.3

–75.8

–

SISO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11n

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

–

–92

–

dBm

(10% PER for 4096 octet

PSDU)^a,b

–

–89.7

–87.2

–84.1

–80.5

–75.9

–74.3

–72.7

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 149

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 41: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

MIMO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11n

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS15

–

–93.5

–92.7

–90.2

–87.1

–83.5

–78.9

–77.3

–75.7

–92

–

dBm/core

(10% PER for 4096 octet

–

PSDU)^a,bDefined for

default parameters: GF,

800 ns GI, and non-STBC.

–72.7

SISO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11n

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

–

–89.8

–86.9

–84.5

–81

–

dBm

(10% PER for 4096 octet

PSDU)^a,b

–

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

–77.9

–73.2

–71.7

–70.3

MIMO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11n

MCS0

MCS1

MCS2

MCS3

MCS4

MCS5

MCS6

MCS7

MCS8

MCS15

–

–91.3

–89.9

–87.5

–84

–

dBm/core

(10% PER for 4096 octet

PSDU)^a,b

–

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

–80.9

–76.2

–74.7

–73.3

–89.8

–70.3

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 150

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 41: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

SISO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

MCS1, Nss 1

MCS2, Nss 1

MCS3, Nss 1

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

–

–91.3

–88.3

–86

–

dBm

(10% PER for 4096 octet

PSDU)^a,b

–

Defined for default

parameters: GF, 800 ns GI,

and non-STBC

–83

–79.4

–74.9

–73.3

–72.6

–68.2

MIMO RX sensitivity IEEE 20 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

MCS1, Nss 1

MCS2, Nss 1

MCS3, Nss 1

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS0, Nss 2

MCS8, Nss 2

–

–92.8

–91.3

–89

–

dBm/core

(10% PER for 4096 octet

PSDU)^a,b

–

Defined for default

parameters: GF, 800 ns GI,

and non-STBC

–86

–82.4

–77.9

–76.3

–75.6

–71.2

–91

–67.1

SISO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

MCS1, Nss 1

MCS2, Nss 1

MCS3, Nss 1

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

–

–88.5

–85.5

–83.7

–80.5

–77.5

–72.5

–71.7

–70.3

–65.9

–64.6

–

dBm

(10% PER for 4096 octet

PSDU)^a,b

–

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 151

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 41: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

MIMO RX sensitivity IEEE 40 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

MCS1, Nss 1

MCS2, Nss 1

MCS3, Nss 1

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

MCS0, Nss 2

MCS9, Nss 2

–

–90

–

dBm/core

(10% PER for 4096 octet

PSDU)^a,b

–

–88.5

–86.7

–83.5

–80.5

–75.5

–74.7

–73.3

–68.9

–67.6

–88

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

–63.2

SISO RX sensitivity IEEE 80 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

MCS1, Nss 1

MCS2, Nss 1

MCS3, Nss 1

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

–

–85

–

dBm

(10% PER for 4096 octet

PSDU)^a,b

–

–82

–80

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

–76.7

–73.7

–70.5

–68

–66.5

–62.3

–60.5

MIMO RX sensitivity IEEE 80 MHz channel spacing for all MCS rates

802.11ac

MCS0, Nss 1

MCS1, Nss 1

MCS2, Nss 1

MCS3, Nss 1

MCS4, Nss 1

MCS5, Nss 1

MCS6, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

MCS0, Nss 2

MCS9, Nss 2

–

–86.5

–85

–

dBm/core

(10% PER for 4096 octet

PSDU)^a,b

–

–83

Defined for default

parameters: GF, 800 ns GI,

and non-STBC.

–79.7

–76.7

–73.5

–71

–69.5

–65.3

–63.5

–84.3

–59.5

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 152

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 41: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

SISO RX sensitivity IEEE MCS7, Nss 1

802.11ac 20/40/80 MHz

channel spacing with

LDPC

20 MHz

–

–74.4

–

dBm

(10% PER for 4096 octet

PSDU)^a,bat WLAN RF

port. Defined for default

parameters: GF, 800 ns GI,

LDPC coding, and non-

STBC.

–

MCS8, Nss 1

MCS9, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

MCS7, Nss 1

MCS8, Nss 1

MCS9, Nss 1

20 MHz

40 MHz

80 MHz

20 MHz

–

–71.7

–71.4

–71.8

–67.5

–66.5

–68

–

dBm

–64.3

–62.5

–73

dBm

MIMO RX sensitivity IEEE MCS7, Nss 2

802.11ac 20/40/80 MHz

channel spacing with

LDPC

dBm/core

(10% PER for 4096 octet

PSDU)^a,bat WLAN RF

port. Defined for default

parameters: GF, 800 ns GI,

LDPC coding, and non-

STBC.

–

MCS8, Nss 2

MCS9, Nss 2

MCS7, Nss 2

MCS8, Nss 2

MCS9, Nss 2

MCS7, Nss 2

MCS8, Nss 2

MCS9, Nss 2

20 MHz

40 MHz

80 MHz

–

–70.2

–66.5

–70.8

–66

–

dBm/core

–64.7

–67

–62.8

–60.5

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 153

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 41: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

Alternate adjacent channel 776–794 MHz

CDMA2000

cdmaOne

–21

–20

–

dBm

rejection

824–849 MHz^d

Blocking level for 3 dB RX

sensitivity degradation^c

(without external filtering)

824–849 MHz^d

GSM850

–12

–

dBm

880–915 MHz

E-GSM

–12

–15

–20

–21

–

36

–

dBm

MHz

dB

1710–1785 MHz

1850–1910 MHz

1920–1980 MHz

2500–2570 MHz

2300–2400 MHz

2570–2620 MHz

2545–2575 MHz

Maximum LNA gain

Minimum LNA gain

@ 6, 9, 12 Mbps

GSM1800

cdmaOne

WCDMA

Band 7

–

Band 40

Band 38

XGP Band

–

Input In-Band IP3

–15.5

–1.5

–

Maximum receive level

@ 5.24 GHz

–9.5

–14.5

9

@ 18, 24, 36, 48, 54 Mbps

–

LPF 3 dB bandwidth

–

Adjacent channel rejection 6 Mbps OFDM

–79 dBm

16

15

13

11

–

(Difference between

interfering and desired

signal (20 MHz apart) at

10% PER for 1000 octet

PSDU with desired signal

level as specified in

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

65 Mbps OFDM

6 Mbps OFDM

9 Mbps OFDM

12 Mbps OFDM

18 Mbps OFDM

24 Mbps OFDM

36 Mbps OFDM

48 Mbps OFDM

54 Mbps OFDM

65 Mbps OFDM

–

–78 dBm

–

dB

–76 dBm

–

dB

–74 dBm

–

dB

–71 dBm

8

–

dB

–67 dBm

4

–

dB

Condition/Notes)

–63 dBm

0

–

dB

–62 dBm

–1

–2

32

31

29

27

24

20

16

15

14

–

dB

–61 dBm

–

dB

(Difference between

interfering and desired

signal (40 MHz apart) at

10% PER for 1000^eoctet

PSDU with desired signal

level as specified in

–78.5 dBm

–77.5 dBm

–75.5 dBm

–73.5 dBm

–70.5 dBm

–66.5 dBm

–62.5 dBm

–61.5 dBm

–60.5 dBm

–

dB

–

dB

–

dB

–

dB

–

dB

Condition/Notes)

–

dB

–

dB

–

dB

–

dB

Maximum receiver gain

Gain control step

95

3

dB

–

dB

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 154

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Receiver Performance Specifications

Table 41: WLAN 5 GHz Receiver Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

RSSI accuracy^f

Range –90 dBm to –30 dBm

Range above –30 dBm

–5

–8

10

–

5

dB

8

Return loss

Zo = 50ꢀ, across the dynamic range

13

–

Receiver cascaded noise At maximum gain

figure

General spurs

1–18 GHz

–

–65

dBm/MHz

a. Derate by 1.5 dB for 55°C to 70°C.

b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal

in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any

specific country.

c. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal

in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any

specific country.

d. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to

third harmonic signals (3 × 824 MHz) falling within band.)

e. For 65 Mbps, the size is 4096.

f. The minimum and maximum values shown have a 95% confidence level.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 155

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Transmitter Performance Specifications

Note: The values in Table 42 are specified at the RF port unless otherwise noted.

Table 42: WLAN 5 GHz Transmitter Performance Specifications

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

Frequency range

–

4900

–

5845

MHz

Transmitted power in

cellular and FM bands (at

18 dBm)^a

76-108 MHz

776-794 MHz

869-960 MHz

FMRX

–

–162

–168

–167

–

dBm/Hz

cdmaOne,

GSM850

1570-1580 MHz GPS

–

–170

–162

–169

–168

–

dBm/Hz

1592-1610 MHz GLONASS

1805-1880 MHz GSM1800

1850-1910 MHz GSM1900

1910-1930 MHz Band 37

1930-1990 MHz GSM1900,

cdmaOne,

WCDMA

2010-2075 MHz TDSCDMA

2110-2170 MHz WCDMA

2300-2370 MHz Band 40

2370-2400 MHz Band 40

2496-2530 MHz Band 41

2530-2560 MHz Band 41

2570-2690 MHz Band 41

–

–168

–160

–166

–162

–165

–158

–30

–

dBm/Hz

dBm/MHz

2^ndharmonic

Harmonic level

(at 17 dBm)

9.8-11.570 GHz

General spurs

1-18 GHz

–

–57

–

dBm/MHz

dBm

–

TX power at RF port for

highest power level setting

at 25°C with spectral mask

and EVM compliance^b

OFDM, QPSK

–13 dB

17.5

16

–

18.5

17.5

–

OFDM, 16-QAM –19 dB

OFDM, 64-QAM

–

(R = 3/4)

–25 dB

15

–

16.5

–

dBm

–

OFDM, 64-QAM

(R = 5/6)

–

–28 dB

14

13

15.5

14.5

–

dBm

OFDM, 256-QAM –30 dB

(R = 3/4, VHT)

–

OFDM, 256-QAM –32 dB

(R = 5/6, VHT)

11

12.5

–

dBm

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 156

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN 5 GHz Transmitter Performance Specifications

Table 42: WLAN 5 GHz Transmitter Performance Specifications (Cont.)

Parameter

Condition/Notes

Min.

Typ.

Max.

Unit

Phase noise

37.4 MHz Crystal, Integrated from 10 –

kHz to 10 MHz

0.5

–

Degrees

TX power control dynamic –

range

10

–

dB

Closed loop TX power

Across full-temperature and voltage

–

±2.0

variation at highest power range. Applies across 10 to 20 dBm

level setting

output power range.

Carrier suppression

Gain control step

Return loss

–

15

–

dBc

dB

–

0.25

6

Zo = 50ꢀ

–

dB

a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may

also be used within those bands.

b. Derate by 1.5 dB for temperatures higher than 55°C, or supply voltages lower than 3.0V. Derate by 3.0 dB for

supply voltages of lower than 2.7V, or supply voltages lower than 3.0V at temperatures higher than 55°C.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 157

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Internal Regulator Electrical Specifications

Section 18: Internal Regulator Electrical

Specifications

Note: Values in this data sheet are design goals and are subject to change based on the results of

device characterization.

Functional operation is not guaranteed outside of the specification limits provided in this section.

Core Buck Switching Regulator

Table 43: Core Buck Switching Regulator (CBUCK) Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

V

Input supply voltage (DC)

DC voltage range inclusive of

disturbances.

3.0

3.6

PWM mode switching frequency CCM, Load > 100 mA VBAT = 3.6V

2.8

–

4

5.2

600

–

MHz

mA

V

PWM output current

Output current limit

Output voltage range

–

1400

1.35

Programmable, 30 mV steps

Default = 1.35V

1.2

1.5

PWM output voltage

DC accuracy

Includes load and line regulation.

Forced PWM mode

–4

–

7

4

%

PWM ripple voltage, static

Measure with 20 MHz bandwidth limit.

20

mVpp

Static Load. Max. ripple based on

VBAT = 3.6V, Vout = 1.35V,

Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH,

Cap + Board total-ESR < 20 mꢀ,

C

_out> 1.9 μF, ESL<200pH

PWM mode peak efficiency

PFM mode efficiency

Peak Efficiency at 200 mA load

10 mA load current

78

70

–

86

81

–

%

µs

–

Start-up time from

power down

VIO already ON and steady.

Time from REG_ON rising edge to CLDO

reaching 1.2V

850

External inductor

0806 size, ± 30%, 0.11 ± 25% Ohms

–

2.2

4.7

–

µH

µF

2.0^b

10^c

External output capacitor

Ceramic, X5R, 0402,

ESR <30 mꢀ at 4 MHz, ± 20%, 6.3V

0.67^b

External input capacitor

For SR_VDDBATP5V pin,

ceramic, X5R, 0603,

4.7

–

µF

ESR < 30 mꢀ at 4 MHz, ± 20%, 6.3V,

4.7 µF

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 158

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

3.3V LDO (LDO3P3)

Table 43: Core Buck Switching Regulator (CBUCK) Specifications (Cont.)

Specification

Notes

Min.

Typ.

Max. Units

– µs

Input supply voltage ramp-up

time

0 to 4.3V

40

–

a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over

the lifetime of the device are allowed. Voltages as high as 5.5V for up to 250 seconds, cumulative duration, over

the lifetime of the device are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part–to–part

tolerance, DC–bias, temperature, and aging.

c. Total capacitance includes those connected at the far end of the active load.

3.3V LDO (LDO3P3)

Table 44: LDO3P3 Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

Input supply voltage, V_in

Min. = V_o+ 0.2V = 3.5V dropout voltage

2.3

3.6

V

requirement must be met under maximum

load for performance specifications.

Output current

–

0.2

–

600

–

mA

V

Nominal output voltage, V_o

Default = 3.3V

3.3

Dropout voltage

At max. load.

–

200

+5

120

6

mV

%

Output voltage DC accuracy

Quiescent current

Includes line/load regulation.

No load

–5

–

100

5.8

1.5

µA

mA

µA

Maximum load (600 mA)

–

Leakage current

Line regulation

Power-Down mode,

junction temperature = 85°C

–

5

V_infrom (V_o+ 0.2V) to 4.8V, max. load

load from 1 mA to 450 mA

–

3.5

mV/V

Load regulation

PSRR

–

0.25

–

mV/mA

dB

V_in≥ V_o+ 0.2V,

20

V_o= 3.3V, C_o= 4.7 µF,

Max. load, 100 Hz to 100 kHz

LDO turn-on time

Chip already powered up.

–

160

4.7

250

–

µs

1.0^b

External output capacitor, C_oCeramic, X5R, 0402,

(ESR: 5 mꢀ–240 mꢀ), ± 10%, 10V

µF

External input capacitor

For SR_VDDBATA5V pin (shared with

Bandgap) Ceramic, X5R, 0402,

(ESR: 30m-200 mꢀ), ± 10%, 10V.

Not needed if sharing VBAT capacitor 4.7 µF

with SR_VDDBATP5V.

–

4.7

–

µF

a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over

the lifetime of the device are allowed. Voltages as high as 5.5V for up to 250 seconds, cumulative duration, over

the lifetime of the device are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part

tolerance, DC-bias, temperature, and aging.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 159

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

3.3V LDO (LDO3P3_B)

Table 45: LDO3P3_B Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

V

Input supply voltage, V_in

Min. = V_o+ 0.2V = 3.5V dropout voltage

2.3

3.6

requirement must be met under maximum

load for performance specifications.

Output current

–

0.1

–

150

–

mA

V

Nominal output voltage, V_o

Default = 3.3V

3.3

Dropout voltage

At max. load.

–

200

+5

16

1.4

5

mV

%

Output voltage DC accuracy

Quiescent current

Includes line/load regulation.

–5

–

No load

–

10

1.38

1.5

µA

mA

µA

Maximum load (150 mA)

Leakage current

–

Power-Down mode,

–

junction temperature = 85°C

Line regulation

V_infrom (V_o+ 0.2V) to 4.8V, max. load

load from 1 mA to 450 mA

–

3.5

mV/V

Load regulation

PSRR

–

0.25

–

mV/mA

dB

V_in≥ V_o+ 0.2V,

20

V_o= 3.3V, C_o= 4.7 µF,

Max. load, 100 Hz to 100 kHz

LDO turn-on time

Chip already powered up.

–

150

–

µs

0.7^b

External output capacitor, C_oCeramic, X5R, 0402,

(ESR: 5 mꢀ–240 mꢀ), ± 10%, 10V

2.2

µF

External input capacitor

For SR_VDDBATA5V pin (shared with

Bandgap) Ceramic, X5R, 0402

–

4.7

–

µF

a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over

the lifetime of the device are allowed. Voltages as high as 5.5V for up to 250 seconds, cumulative duration, over

the lifetime of the device are allowed.

b. Minimum capacitor value refers to the residual capacitor value after taking into account the part–to–part

tolerance, DC–bias, temperature, and aging.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 160

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

2.5V LDO (BTLDO2P5)

Table 46: BTLDO2P5 Specifications

Specification

Notes

Min.

Typ.

Max. Units

5.25^a

V

Input supply voltage

Min. = 2.5V + 0.2V = 2.7V.

3.0

3.6

Dropout voltage requirement must be

met under maximum load for

performance specifications.

Nominal output voltage

Default = 2.5V.

Range

–

2.5

–

V

Output voltage programmability

2.2

–5

2.8

5

V

Accuracy at any step (including line/

load regulation), load > 0.1 mA.

%

Dropout voltage

Output current

At maximum load.

–

200

70

mV

mA

µA

0.1

–

Quiescent current

No load.

8

16

Maximum load at 70 mA.

Power-down mode.

–

660

1.5

–

700

5

µA

Leakage current

Line regulation

–

µA

V_infrom (V_o+ 0.2V) to 4.8V,

maximum load.

–

3.5

mV/V

Load regulation

PSRR

Load from 1 mA to 70 mA,

V_in= 3.6V.

–

0.3

–

mV/mA

dB

V_in≥ V_o+ 0.2V, V_o= 2.5V, C_o= 2.2 µF, 20

maximum load, 100 Hz to 100 kHz.

LDO turn-on time

In-rush current

Chip already powered up.

–

150

250

µs

V_in= V_o+ 0.15V to 4.8V, C_o= 2.2 µF,

No load.

mA

0.7^b

2.2

4.7

µF

External output capacitor, C_o

External input capacitor

Ceramic, X5R, 0402,

(ESR: 5–240 mꢀ), ±10%, 10V

2.64

–

For SR_VDDBATA5V pin (shared with –

Bandgap) ceramic, X5R, 0402,

(ESR: 30–200 mꢀ), ±10%, 10V.

Not needed if sharing VBAT 4.7 µF

capacitor with SR_VDDBATP5V.

a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over

the lifetime of the device are allowed. Voltages as high as 5.5V for up to 250 seconds, cumulative duration, over

the lifetime of the device are allowed.

b. The minimum value refers to the residual capacitor value after taking into account part–to–part tolerance, DC–

bias, temperature, and aging.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 161

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

CLDO

Table 47: CLDO Specifications

Notes

Specification

Min. Typ. Max. Units

1.35 1.5

Input supply voltage, V_in

Min. = 1.2 + 0.15V = 1.35V dropout voltage 1.3

requirement must be met under maximum

load.

V

Output current

–

0.2

1.1

–

300 mA

1.275 V

Output voltage, V_o

Programmable in 25 mV steps.

Default = 1.2.V

1.2

Dropout voltage

At max. load

–

150 mV

Output voltage DC accuracy

Quiescent current

Includes line/load regulation

No load

–4

–

+4

–

%

24

2.1

–

µA

mA

300 mA load

–

Line Regulation

V_infrom (V_o+ 0.15V) to 1.5V, maximum load –

5

mV/V

Load Regulation

Leakage Current

Load from 1 mA to 300 mA

Power down

–

0.02 0.05 mV/mA

–

1

–

20

3

µA

dB

Bypass mode

–

PSRR

@1 kHz, Vin ≥ 1.35V, C_o= 4.7 µF

20

–

Start-up Time of PMU

VIO up and steady. Time from the REG_ON –

rising edge to the CLDO reaching 1.2V.

–

700 µs

LDO Turn-on Time

LDO turn-on time when rest of the chip is up –

140 180 µs

1.32^a

External Output Capacitor, C_o

Total ESR: 5 mꢀ–240 mꢀ

4.7

1

–

µF

External Input Capacitor

Only use an external input capacitor at the

VDD_LDO pin if it is not supplied from

CBUCK output.

–

2.2

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part–to–part

tolerance, DC–bias, temperature, and aging.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 162

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

LNLDO

Table 48: LNLDO Specifications

Specification

Notes

Min.

Typ.

Max. Units

Input supply voltage, Vin

Min. = 1.2V_o+ 0.15V = 1.35V dropout

1.3

1.35

1.5

V

voltage requirement must be met under

maximum load.

Output Current

–

0.1

1.1

–

150

mA

V

Output Voltage, V_o

Programmable in 25 mV steps.

Default = 1.2V

1.2

1.275

Dropout Voltage

At maximum load

–

150

+4

–

mV

%

Output Voltage DC Accuracy Includes line/load regulation

–4

–

Quiescent current

No load

44

970

–

µA

Max. load

–

990

5

Line Regulation

V_infrom (V_o+ 0.1V) to 1.5V, max. load

–

mV/V

Load Regulation

Leakage Current

Output Noise

Load from 1 mA to 150 mA

Power-down

–

0.02

–

0.05

10

mV/mA

µA

@30 kHz, 60–150 mA load C_o= 2.2 µF

@100 kHz, 60–150 mA load C_o= 2.2 µF

–

60

35

nV/rt Hz

PSRR

@ 1kHz, Input > 1.35V, C_o= 2.2 µF, V_o=

1.2V

20

–

dB

LDO Turn-on Time

LDO turn-on time when rest of chip is up

–

140

2.2

180

4.7

µs

0.5^a

External Output Capacitor, Total ESR (trace/capacitor):

C_o

µF

5 mꢀ–240 mꢀ

External Input Capacitor

Only use an external input capacitor at the –

VDD_LDO pin if it is not supplied from

CBUCK output.

1

2.2

µF

Total ESR (trace/capacitor): 30 mꢀ–200 mꢀ

a. Minimum capacitor value refers to the residual capacitor value after taking into account the part–to–part

tolerance, DC–bias, temperature, and aging.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 163

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

System Power Consumption

Section 19: System Power Consumption

Note: Values in this data sheet are design goals and are subject to change based on the results of

device characterization.

Unless otherwise stated, these values apply for the conditions specified in Table 32: “Recommended

Operating Conditions and DC Characteristics,” on page 127.

WLAN Current Consumption

The WLAN current consumption measurements are shown in Table 49.

All values in Table 49 are with the Bluetooth core in reset (that is, Bluetooth and FM are OFF).

.

Table 49: Typical WLAN Power Consumption

Vio = 1.8V

uA^a

Bandwidth Band Vbat = 3.6V)

Mode

(MHz)

(GHz) mA

Sleep Modes

OFF^b

–

0.003

5.5

Sleep^c

–

0.005

1.2

0.4

1.2

0.4

1.5

0.5

2.0

0.7

260

IEEE power save, DTIM 1 1 RX core^d

20

40

80

2.4

5

IEEE power save, DTIM 3 1 RX core^d

IEEE power save, DTIM 1 1 RX core^d

IEEE power save, DTIM 3 1 RX core^d

IEEE power save, DTIM 1 1 RX core^d

IEEE power save, DTIM 3 1 RX core^d

IEEE power save, DTIM 1 1 RX core^d

IEEE power save, DTIM 3 1 RX core^d

5

Active Modes

Transmit

CCK 1 chain^e

20

40

2.4

5

350

270

540

310

620

315

60

MCS8, Nss 1, HT20, SGI^f,g,h

TMCS8, Nss 2, HT20, SGI^f,g,h

MCS7, SGI^{f, g,i}

MCS15, SGI^{f, g,i}

5

MCS7^f,g,i

5

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 164

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

WLAN Current Consumption

Table 49: Typical WLAN Power Consumption (Cont.)

Bandwidth Band Vbat = 3.6V)

Vio = 1.8V

uA^a

Mode

(MHz)

(GHz) mA

MCS9, Nss 1, SGI^f,g,j

40

5

295

590

305

610

60

MCS9, Nss 2, SGI^f,g,j

MCS9, Nss 1, SGI^f,g,j

MCS9, Nss 2, SGI^f,g,j

40

80

Receive

1 Mbps, 1 RX core

1 Mbps, 2 RX cores

20

2.4

59

75

62

60

MCS7, HT20 1 RX core^k

MCS7, HT20 2 RX cores^k

MCS15, HT20^k

20

40

80

2.4

5

81

60

86

CRS 1 RX core^l

57

CRS 2 RX cores^l

76

Receive MCS7, SGI 1 RX core^k

Receive MCS7, SGI 2 RX cores^k

Receiver MCS15, SGI^k

CRS 1 RX core^l

71

5

102

106

67

5

CRS 2 RX cores^l

5

96

Receive MCS 7, SGI 1 RX core^k

Receive MCS 7, SGI 2 RX cores^k

Receive MCS 15, SGI^k

CRS 1 RX core^l

5

91

5

135

141

80

5

CRS 2 RX cores^l

5

121

123

189

206

102

163

Receive MCS9, Nss 1, SGI^k

Receive MCS9, Nss 1, SGI 2 RX cores^k

Receive MCS9, Nss 2, SGI^k

CRS 1 RX core^l

5

CRS 2 RX cores^l

5

a. Specified with all pins idle (not switching) and not driving any loads.

b. WL_REG_ON, BT_REG_ON low, no VDDIO.

c. Idle, not associated, or inter-beacon.

d. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @1 Mbps. Average current over 3 DTIM intervals.

e. Output power per core at RF port = 21 dBm

f.

Duty cycle is 100%

g. Measured using packet engine test mode.

h. Output power per core at RF port = 17 dBm.

i.

j.

Output power per core at RF port = 17.5 dBm.

Output power per core at RF port = 14 dBm.

k.

l.

Duty cycle is 100%. Carrier sense (CS) detect/packet receive.

Carrier sense (CCA) when no carrier present.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 165

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Bluetooth and FM Current Consumption

The Bluetooth, BLE, and FM current consumption measurements are shown in Table 50.

Note:

•

The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 50.

For FM measurements, the Bluetooth core is in Sleep mode.

The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

Table 50: Bluetooth BLE and FM Current Consumption

VBAT (VBAT = 3.6V)

Operating Mode

Typical

VDDIO (VDDIO = 1.8V) Typical Units

Sleep

13

198

µA

mA

µA

Standard 1.28s Inquiry Scan

0.217

440

0.197

194

P and I Scan^b

500 ms Sniff Master

500 ms Sniff Slave

DM1/DH1 Master

DM3/DH3 Master

DM5/DH5 Master

3DH5 Master

0.168

0.124

25.3

30.6

31.4

29.2

11.45

11.7

0.195

0.190

0.024

0.035

0.037

0.094

0.089

0.090

mA

SCO HV3 Master

HV3 + Sniff + Scan^a

FMRX I²S Audio

8.0

–

mA

FMRX Analog Audio only

8.6

8.0

–

mA

FMRX I²S Audio + RDS

FMRX Analog Audio + RDS

8.6

–

mA

µA

BLE Scan^b

244

196

BLE Scan 10 ms

21.34

0.013

199

mA

µA

mA

µA

BLE Adv—Unconnectable 1.00 sec 67

BLE Adv—Unconnectable 1.28 sec 55

BLE Adv—Unconnectable 2.00 sec 58

199

BLE Connected 7.5 ms

BLE Connected 1 sec.

BLE Connected 1.28 sec.

3.95

0.013

198

57

52

197

a. At maximum class 1 TX power, 500 ms sniff, four attempts (slave), P = 1.28s, and I = 2.56s.

b. No devices present. A 1.28 second interval with a scan window of 11.25 ms.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 166

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Interface Timing and AC Characteristics

Section 20: Interface Timing and AC

Characteristics

SDIO Timing

SDIO Default Mode Timing

SDIO default mode timing is shown by the combination of Figure 37 and Table 51.

Figure 37: SDIO Bus Timing (Default Mode)

f_PP

t_WL

t_WH

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

(max)

(min)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 167

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

Table 51: SDIO Bus Timing^aParameters (Default Mode)

Symbol Minimum Typical

Parameter

Maximum Unit

SDIO CLK (All values are referred to minimum VIH and maximum VIL^b)

Frequency – Data Transfer mode

Frequency – Identification mode

Clock low time

fPP

0

–

25

400

–

MHz

kHz

ns

fOD

tWL

tWH

tTLH

tTHL

0

10

–

Clock high time

–

ns

Clock rise time

10

ns

Clock low time

–

ns

Inputs: CMD, DAT (referenced to CLK)

Input setup time

Input hold time

tISU

tIH

5

–

ns

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer mode

Output delay time – Identification mode

tODLY

0

–

14

50

ns

a. Timing is based on CL  40pF load on CMD and Data.

b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 168

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

SDIO High-Speed Mode Timing

SDIO high-speed mode timing is shown by the combination of Figure 38 and Table 52.

Figure 38: SDIO Bus Timing (High-Speed Mode)

f_PP

t_WL

t_WH

50% VDD

SDIO_CLK

t_THL

t_TLH

t_IH

t_ISU

Input

Output

t_ODLY

t_OH

Table 52: SDIO Bus Timing^aParameters (High-Speed Mode)

Parameter

Symbol

Minimum Typical

Maximum Unit

SDIO CLK (all values are referred to minimum VIH and maximum VIL^b)

Frequency – Data Transfer Mode

Frequency – Identification Mode

Clock low time

fPP

fOD

tWL

tWH

tTLH

tTHL

–

0

7

–

50

400

–

MHz

kHz

ns

Clock high time

–

ns

Clock rise time

3

ns

Clock low time

3

ns

–

Inputs: CMD, DAT (referenced to CLK)

Input setup Time

Input hold Time

tISU

tIH

–

6

2

–

ns

–

Outputs: CMD, DAT (referenced to CLK)

Output delay time – Data Transfer Mode

Output hold time

tODLY

tOH

–

14

–

ns

pF

2.5

–

Total system capacitance (each line)

CL

40

a. Timing is based on CL  40pF load on CMD and Data.

b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 169

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

SDIO Bus Timing Specifications in SDR Modes

Clock Timing

Figure 39: SDIO Clock Timing (SDR Modes)

t_CLK

SDIO_CLK

t_CR

t_CF

t_CR

Table 53: SDIO Bus Clock Timing Parameters (SDR Modes)

Parameter

Symbol

Minimum

Maximum

Unit

Comments

–

t_CLK

40

20

10

4.8

–

ns

SDR12 mode

SDR25 mode

SDR50 mode

SDR104 mode

–

t

_CR, t_CF

0.2 × t_CLK

t_CR, t_CF< 2.00 ns (max.) @100 MHz,

C_CARD= 10 pF

t_CR, t_CF< 0.96 ns (max.) @208 MHz,

C_CARD= 10 pF

Clock duty

–

30

70

%

–

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 170

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

Device Input Timing

Figure 40: SDIO Bus Input Timing (SDR Modes)

SDIO_CLK

t_IS

t_IH

CMD input

DAT[3:0] input

Table 54: SDIO Bus Input Timing Parameters (SDR Modes)

Symbol

Minimum

Maximum

Unit

Comments

SDR104 Mode

t_IS

t_IH

1.4

–

ns

C_CARD= 10 pF, VCT = 0.975V

C_CARD= 5 pF, VCT = 0.975V

0.80

SDR50 Mode

t_IS

t_IH

3.00

0.80

–

ns

C_CARD= 10 pF, VCT = 0.975V

C_CARD= 5 pF, VCT = 0.975V

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 171

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

Device Output Timing

Figure 41: SDIO Bus Output Timing (SDR Modes up to 100 MHz)

t_CLK

SDIO_CLK

t_ODLY

t_OH

CMD input

DAT[3:0] input

Table 55: SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)

Symbol

t_ODLY

t_OH

Minimum

Maximum

Unit

ns

Comments

–

7.5

14.0

–

t_CLK≥ 10 ns C_L= 30 pF using driver type B for SDR50

t_CLK≥ 20 ns C_L= 40 pF using for SDR12, SDR25

Hold time at the t_ODLY(min.) C_L= 15 pF

–

ns

1.5

ns

Figure 42: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)

t_CLK

SDIO_CLK

t_OP

t_ODW

CMD input

DAT[3:0] input

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 172

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

Table 56: SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz)

Symbol

t_OP

Minimum

0

Maximum

Unit

UI

Comments

2

Card output phase

∆t_OP

–350

0.60

+1550

–

ps

Delay variation due to temp change after tuning

t_ODW=2.88 ns @208 MHz

t_ODW

UI

•

∆t_OP= +1550 ps for junction temperature of ∆t_OP= 90 degrees during operation

∆t_OP= –350 ps for junction temperature of ∆t_OP= –20 degrees during operation

∆t_OP= +2600 ps for junction temperature of ∆t_OP= –20 to +125 degrees during operation

Figure 43: ∆t_OPConsideration for Variable Data Window (SDR 104 Mode)

Data valid window

Sampling point after tuning

ȴt_OP

1550 ps

=

Data valid window

ȴt_OP

350 ps

=

Sampling point after card junction heating

by +90°C from tuning temperature

Data valid window

Sampling point after card junction cooling

by 20°C from tuning temperature

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 173

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

SDIO Bus Timing Specifications in DDR50 Mode

Figure 44: SDIO Clock Timing (DDR50 Mode)

t_CLK

SDIO_CLK

t_CR

t_CF

t_CR

Table 57: SDIO Bus Clock Timing Parameters (DDR50 Mode)

Parameter

Symbol

Minimum

Maximum

–

Unit

ns

Comments

–

t_CLK

20

–

DDR50 mode

t

_CR,t_CF

0.2 × tCLK

ns

t_CR, t_CF< 4.00 ns (max.) @50 MHz,

C_CARD= 10 pF

Clock duty

–

45

55

%

–

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 174

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

SDIO Timing

Data Timing, DDR50 Mode

Figure 45: SDIO Data Timing (DDR50 Mode)

F_PP

SDIO_CLK

t_ISU2x

t_IH2x

t_ISU2x

t_IH2x

DAT[3:0]

input

Invalid

Data

Invalid

Data

Invalid

Data

Invalid

t_ODLY2x(max)

t_ODLY2x

(min)

t_ODLY2x

(min)

Available timing

window for card

output transition

DAT[3:0]

output

Data

In DDR50 mode, DAT[3:0] lines are sampled on both edges of

the clock (not applicable for CMD line)

Available timing

window for host to

sample data from card

Table 58: SDIO Bus Timing Parameters (DDR50 Mode)

Parameter

Input CMD

Symbol

Minimum

Maximum

Unit Comments

Input setup time

Input hold time

t_ISU

t_IH

6

–

ns

C_CARD< 10 pF (1 Card)

0.8

Output CMD

Output delay time

Output hold time

t_ODLY

t_OH

–

13.7

–

ns

C_CARD< 30 pF (1 Card)

C_CARD< 15 pF (1 Card)

1.5

Input DAT

Input setup time

Input hold time

t_ISU2x

t_IH2x

3

–

ns

C_CARD< 10 pF (1 Card)

0.8

Output DAT

Output delay time

Output hold time

t_ODLY2x

–

7.5

–

ns

C_CARD< 25 pF (1 Card)

C_CARD< 15 pF (1 Card)

1.5

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 175

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

HSIC Interface Specifications

Table 59: HSIC Interface Parameters

Parameter

Symbol Minimum

Typical

Maximum

1.3

Unit

Comments

HSIC signaling voltage

I/O voltage input low

I/O Voltage input high

I/O voltage output low

I/O voltage output high

I/O pad drive strength

V_DD

V_IL

1.1

1.2

–

V

ꢀ

–

–0.3

0.35 × V_DD

V_DD+ 0.3

0.25 × V_DD

–

V_IH

V_OL

V_OH

O_D

0.65 × V_DD

–

0.75 × V_DD

40

–

60

Controlled output

impedance driver

I/O weak keepers

I_L

20

100

3

–

70

–

mA

kꢀ

pF

ꢀ

–

I/O input impedance

Z_I

C_L

T_I

–

Total capacitive load^a

–

14

55

Characteristic trace

impedance

45

50

Circuit board trace length T_L

–

10

15

cm

ps

–

Circuit board trace

propagation skew^b

T_S

STROBE frequency^c

Slew rate (rise and fall)

STROBE and DATA^C

F_STROBE239.988

T_slew

240

240.012

1.2

MHz

V/ns

± 500 ppm

0.60 × V_DD1.0

Averaged from

30% ~ 70% points

Receiver data setup time T_s

(with respect to STROBE)^c

300

–

ps

Measured at the

50% point

Receiver data hold time

T_b

Measured at the

50% point

(with respect to STROBE)^c

a. Total Capacitive Load (C_L), includes device Input/Output capacitance, and capacitance of a 50ꢀ PCB trace with

a length of 10 cm.

b. Maximum propagation delay skew in STROBE or DATA with respect to each other. The trace delay should be

matched between STROBE and DATA to ensure that the signal timing is within specification limits at the

receiver.

c. Jitter and duty cycle are not separately specified parameters, they are incorporated into the values in the

Table 59.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 176

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCI Express Interface Parameters

Table 60: PCI Express Interface Parameters

Parameter

Symbol

Comments

Minimum Typical Maximum Unit

General

Baud rate

BPS

Vref

–

1

5

–

Gbaud

V

Reference clock

amplitude

LVPECL

Receiver

Differential termination ZRX-DIFF-DC

Differential termination 80

100

50

120

60

ꢀ

DC impedance

ZRX-DC

DC common-mode

impedance

40

Powered down

termination (POS)

ZRX-HIGH-IMP-DC- Power-down or RESET 100k

POS high impedance

–

ꢀ

Powered down

termination (NEG)

ZRX-HIGH-IMP-DC- Power-down or RESET 1k

ꢀ

NEG

high impedance

Input voltage

VRX-DIFFp-p

AC coupled, differential 175

p-p

mV

UI

Jitter tolerance

TRX-EYE

Minimum receiver eye 0.4

width

Differential return loss RLRX-DIFF

Differential return loss 10

–

dB

Common-mode return RLRX-CM

loss

Common-mode return

loss

6

Unexpected electrical TRX-IDEL-DET-

An unexpected

–

10

ms

idle enter detect

threshold integration

time

DIFF-ENTERTIME electrical idle must be

recognized no longer

than this time to signal

an unexpected idle

condition.

Signal detect threshold VRX-IDLE-DET-

DIFFp-p

Electrical idle detect

threshold

65

175

mV

Transmitter

Output voltage

VTX-DIFFp-p

VTX-RISE

Differential p-p,

programmable in 16

steps

0.8

–

1200

–

mV

UI

Output voltage rise

time

20% to 80%

0.125

(2.5 GT/s)

0.15

(5 GT/s)

Output voltage fall time VTX-FALL

80% to 20%

0.125

(2.5 GT/s)

–

UI

0.15

(5 GT/s)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 177

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

PCI Express Interface Parameters

Table 60: PCI Express Interface Parameters (Cont.)

Symbol Comments Minimum Typical Maximum Unit

Parameter

RX detection voltage VTX-RCV-DETECT The amount of voltage –

–

600

100

20

mV

swing

change allowed during

receiver detection.

TX AC peak common- VTX-CM-AC-PP

mode voltage

(5 GT/s)

TX AC common mode

voltage (5 GT/s)

–

0

TX AC peak common- VTX-CM-AC-P

mode voltage

(2.5 GT/s)

TX AC common mode

voltage (2.5 GT/s)

Absolute delta of DC VTX-CM-DC-

Absolute delta of DC

common-model voltage

during L0 and electrical

idle.

100

common-model

ACTIVE-IDLE-

voltage during L0 and DELTA

electrical idle

Absolute delta of DC VTX-CM-DC-LINE- DC offset between D+

0

–

25

mV

common-model

voltage between D+

and D-

DELTA

and D-

Electrical idle

differential peak output p

voltage

VTX-IDLE-DIFF-AC- Peak-to-peak voltage

0

–

20

mV

mA

ꢀ

TX short circuit

current

ITX-SHORT

Current limit when TX

output is shorted to

ground.

90

DC differential TX

termination

ZTX-DIFF-DC

RLTX-DIFF

Low impedance defined 80

during signaling

(parameter is captured

for 5.0 GHz by RLTX-

DIFF)

120

Differential

return loss

Differential

return loss

10 (min.)

for 0.05:

–

dB

1.25 GHz

Common-mode

return loss

RLTX-CM

TTX-EYE

Common-mode return

loss

6

–

dB

UI

TX eye width

Minimum TX

eye width

0.75

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 178

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

JTAG Timing

Signal Name

JTAG Timing

Table 61: JTAG Timing Characteristics

Output

Minimum

Period

Maximum

Setup

Hold

TCK

125 ns

–

TDI

–

20 ns

–

0 ns

–

TMS

–

TDO

–

100 ns

–

0 ns

–

JTAG_TRST

250 ns

–

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 179

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Power-Up Sequence and Timing

Section 21: Power-Up Sequence and

Timing

Sequencing of Reset and Regulator Control Signals

The BCM4354 has two signals that allow the host to control power consumption by enabling or disabling the

Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are

provided to indicate proper sequencing of the signals for various operational states (see Figure 46, Figure 47

on page 181, and Figure 48 and Figure 49 on page 182). The timing values indicated are minimum required

values; longer delays are also acceptable.

Description of Control Signals

•

WL_REG_ON: Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON

input to control the internal BCM4354 regulators. When this pin is high, the regulators are enabled and the

WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON

and WL_REG_ON pins are low, the regulators are disabled.

•

BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power up the internal BCM4354

regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this

pin is low and WL_REG_ON is high, the BT section is in reset.

Note:

•

For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay

between consecutive toggles (where both signals have been driven low). This is to allow time for

the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush

current on the order of 36 mA during the next PMU cold start.

•

The reset requirements for the Bluetooth core are also applicable for the FM core. In other words,

if FM is to be used, then the Bluetooth core must be enabled.

The BCM4354 has an internal power-on reset (POR) circuit. The device will be held in reset for a

maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least

150 ms after VDDC and VDDIO are available before initiating SDIO accesses.

•

VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the

same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 180

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Sequencing of Reset and Regulator Control Signals

Control Signal Timing Diagrams

Figure 46: WLAN = ON, Bluetooth = ON

32.678 kHz

Sleep Clock

90% of VH

VBAT*

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high

before VBAT is high.

Figure 47: WLAN = OFF, Bluetooth = OFF

32.678 kHz

Sleep Clock

VBAT*

VDDIO

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 181

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Sequencing of Reset and Regulator Control Signals

Figure 48: WLAN = ON, Bluetooth = OFF

32.678 kHz

Sleep Clock

90% of VH

VBAT*

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Figure 49: WLAN = OFF, Bluetooth = ON

32.678 kHz

Sleep Clock

90% of VH

VBAT*

VDDIO

~ 2 Sleep cycles

WL_REG_ON

BT_REG_ON

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO . VDDIO should NOT be present first or be held high before VBAT is high .

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 182

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Sequencing of Reset and Regulator Control Signals

Figure 50 shows the WLAN boot-up sequence from power-up to firmware download.

Figure 50: WLAN Boot-Up Sequence

VBAT*

VDDIO

WL_REG_ON

< 950 µs

VDDC

(from internal PMU)

< 104 ms

Internal POR

After a fixed delay following Internal POR and WL_REG_ON going high,

the device responds to host F0 (address 0x14) reads.

< 4 ms

Device requests for reference clock

8 ms

After 8 ms the reference clock is

assumed to be up. Access to PLL

registers is possible.

Host Interaction:

Host polls F0 (address 0x14) until it reads a

predefined pattern.

Host sets wake-up-wlan bit and

waits 8 ms, the maximum time for

reference clock availability.

After 8 ms, host programs PLL

registers to set crystal frequency

Chip active interrupt is asserted after the PLL locks

Host downloads

code.

*Notes:

1. VBAT should not rise 10%–90% faster than 40 microseconds.

2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high.

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 183

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Package Information

Section 22: Package Information

Package Thermal Characteristics

The information in Table 62 and Table 63 is based on the following conditions:

•

No heat sink, T_A= 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7

(101.6 mm × 101.6 mm × 1.6 mm) and P = 1.53W continuous dissipation.

Absolute junction temperature limits are maintained through active thermal monitoring and driver-based

techniques that may include duty-cycle limiting or turning off one of the TX chains, or both.

Table 62: WLCSP Package Thermal Characteristics

Characteristic

WLCSP

26.86

2.23

θ

_JA(°C/W) (value in still air)

_JB(°C/W)

_JC(°C/W)

1.09



_JT(°C/W)

_JB(°C/W)

2.48

11.61

125

Maximum Junction Temperature T_j(°C)

Maximum Power Dissipation (W)

1.53

Table 63: WLBGA Package Thermal Characteristics

Characteristic

WLBGA

26.80

1.66

θ

_JA(°C/W) (value in still air)

_JB(°C/W)

θ_JC(°C/W)

1.16



_JT(°C/W)

_JB(°C/W)

1.85

7.93

Maximum Junction Temperature T_j(°C)

Maximum Power Dissipation (W)

125

1.53

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 184

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Junction Temperature Estimation and PSI_JTVersus Theta_JC

The package thermal characterization parameter PSI_JT(_JT) yields a better estimation of actual junction

temperature (T_J) than using the junction-to-case thermal resistance parameter Theta_JC(θ_JC). The reason for

this is that θ_JCis based on the assumption that all the power is dissipated through the top surface of the package

case. In actual applications, however, some of the power is dissipated through the bottom and sides of the

package. _JTtakes into account the power dissipated through the top, bottom, and sides of the package. The

equation for calculating the device junction temperature is:

T_J= T_T+ P x _JT

Where:

•

T_J= Junction temperature at steady-state condition (°C)

T_T= Package case top center temperature at steady-state condition (°C)

P = Device power dissipation (Watts)



_JT= Package thermal characteristics; no airflow (°C/W)

Environmental Characteristics

For environmental characteristics data, see Table 30: “Environmental Ratings,” on page 126.

Broadcom^®

October 15, 2014 • 4354-DS109-R

BROADCOM CONFIDENTIAL

Page 185

BCM4354 Data Sheet

Mechanical Information

Section 23: Mechanical Information

Figure 51: 192-Ball WLBGA Package Mechanical Information

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 186

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Mechanical Information

Figure 52: WLBGA Keep-Out Areas for PCB Layout (Top View, Balls Facing Down)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 187

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Mechanical Information

Figure 53: 395-Bump WLCSP Package

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 188

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Mechanical Information

Figure 54: WLCSP Keep-Out Areas for PCB Layout (Top View, Balls Facing Down)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 189

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Ordering Information

Section 24: Ordering Information

Operating

Ambient

Temperature

Part Number

Package

Description

BCM4354XKUBG 192-ball WLBGA

(4.87 mm × 7.67 mm,

Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.0 –30°C to +85°C

+ FMRX (–22°F to 185°F)

0.4 mm pitch)

BCM4354XKWBG 395-bump WLCSP

(4.87 mm × 7.67 mm,

Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.0 –30°C to +85°C

+ FMRX

(–22°F to 185°F)

0.2 mm pitch)

BCM4354ZKUBG 192-ball WLBGA

(4.87 mm × 7.67 mm,

Dual-band 2.4 GHz and 5 GHz WLAN

–30°C to +85°C

(–22°F to 185°F)

0.4 mm pitch)

Broadcom^®

October 15, 2014 • 4354-DS109-R

Page 190

BROADCOM CONFIDENTIAL

BCM4354 Data Sheet

Broadcom^®Corporation reserves the right to make changes without further notice to any products or

data herein to improve reliability, function, or design.

Information furnished by Broadcom Corporation is believed to be accurate and reliable. However,

Broadcom Corporation does not assume any liability arising out of the application or use of this

information, nor the application or use of any product or circuit described herein, neither does it

convey any license under its patent rights nor the rights of others.

®

Broadcom Corporation

Phone: 949-926-5000

Fax: 949-926-5203

5300 California Avenue

E-mail: info@broadcom.com

Web: www.broadcom.com

Irvine, CA 92617

4354-DS109-R

October 15, 2014


型号：	BCM4354KKWBGT
厂家：	CYPRESS
描述：	Single-Chip 5G Wi-Fi IEEE 802.11ac 2Ã2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver
文件：	总192页 (文件大小：4575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BCM4354KKWBGT [CYPRESS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E