CY22393ZXC-XXXT [CYPRESS]
Three-PLL Serial-Programmable Flash-Programmable Clock Generator; 三锁相环串行可编程闪存的可编程时钟发生器
| 型号： | CY22393ZXC-XXXT |
| 厂家： | 
CYPRESS |
| 描述： | Three-PLL Serial-Programmable Flash-Programmable Clock Generator |
| 文件： | 总19页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22393
CY22394
CY22395
Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Benefits
Features
• Three integrated phase-locked loops (PLLs)
• Generates up to three unique frequencies on up to six
outputs from an external source.
• Ultra-wide divide counters (8-bit Q, 11-bit P, and 7-bit
post divide)
• Allows for 0-ppm frequency generation and frequency
conversion in the most demanding applications.
• Improved linear crystal load capacitors
• Flash programmability with external programmer
• Field-programmable
• Low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Configurable crystal drive strength
• Frequency select via three external LVTTL inputs
• 3.3V operation
• Improves frequency accuracy over temperature, age,
process, and initial ppm offset.
• Non-volatile programming enables easy customization,
ultra-fast turnaround, performance tweaking, design timing
margintesting,inventorycontrol,lowerpartcount,andmore
secure product supply. In addition, any part in the family can
be programmed multiple times, which reduces
programming errors and provides an easy upgrade path for
existing designs.
• In-house programming of samples and prototype quantities
are available using the CY3672 FTG Development Kit.
Production quantities are available through Cypress
Semiconductor’s value-added distribution partners or by
usingthird-partyprogrammersfromBPMicrosystems, HiLo
Systems, and others.
• Performance suitable for high-end multimedia, communica-
tions, industrial, A/D converters, and consumer applica-
tions.
• Supports numerous low-power application schemes and
reduces electromagnetic interference (EMI) by allowing
unused outputs to be turned off.
• 16-pin TSSOP package
• CyClocksRT™ support
Advanced Features
• Serial-programmable
• Configurable output buffer
• Digital VCXO
• High-frequency LVPECL output (CY22394 only)
• 3.3/2.5V outputs (CY22395 only)
• Adjust crystal drive strength for compatibility with virtually
all crystals.
• 3-bit external frequency select options for PLL1, CLKA, and
CLKB.
• Industry-standard supply voltage.
• Industry-standard packaging saves on board space.
• Easy to use software support for design entry.
• Allows in-system programming into volatile configuration
memory. All frequency settings can be changed providing
literally millions of frequency options.
• Adjust output buffer strength to lower EMI or improve timing
margin.
• Fine tune crystal oscillator frequency by changing load
capacitance.
• Differential output up to 400 MHz.
• Provides interfacing option for low-voltage parts.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07186 Rev. *B
Revised June 23, 2004
CY22393
CY22394
CY22395
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY22393FC
6 CMOS
8 MHz–30 MHz (external crystal) Up to 200 MHz
Commercial Temperature
Industrial Temperature
Commercial Temperature
Industrial Temperature
Commercial Temperature
Industrial Temperature
1 MHz–166 MHz (reference clock)
CY22393FI
CY22394FC
CY22394FI
CY22395FC
CY22395FI
6 CMOS
8 MHz–30 MHz (external crystal) Up to 166 MHz
1 MHz–150 MHz (reference clock)
1 PECL/
4 CMOS
8 MHz–30 MHz (external crystal) 100 MHz–400 MHz (PECL)
1 MHz–166 MHz (reference clock) Up to 200 MHz (CMOS)
1 PECL/
8 MHz–30 MHz (external crystal) 125 MHz–375 MHz (PECL)
1 MHz–150 MHz (reference clock) Up to 166 MHz (CMOS)
4 CMOS
4 LVCMOS/ 8 MHz–30 MHz (external crystal) Up to 200 MHz (3.3V)
1 CMOS 1 MHz–166 MHz (reference clock) Up to 133 MHz (2.5V)
4 LVCMOS/ 8 MHz–30 MHz (external crystal) Up to 166 MHz (3.3V)
1 CMOS 1 MHz–150 MHz (reference clock) Up to 133 MHz (2.5V)
Logic Block Diagram — CY22393
XTALIN
XBUF
CLKE
OSC.
XTALOUT
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
Divider
/2, /3, or /4
SHUTDOWN/OE
SCLK
PLL2
11-Bit P
8-Bit Q
Divider
7-Bit
CLKD
CLKC
4x4
SDAT
Crosspoint
Switch
S2/SUSPEND
Divider
7-Bit
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
CLKB
CLKA
Divider
7-Bit
Logic Block Diagram — CY22394
XTALIN
XBUF
OSC.
XTALOUT
CONFIGURATION
FLASH
0º
PLL1
11-Bit P
8-Bit Q
P+CLK
P-CLK
PECL
180º
OUTPUT
SHUTDOWN/OE
SCLK
PLL2
11-Bit P
8-Bit Q
Divider
7-Bit
4x4
CLKC
CLKB
CLKA
SDAT
Crosspoint
Switch
S2/SUSPEND
Divider
7-Bit
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
Document #: 38-07186 Rev. *B
Page 2 of 19
CY22393
CY22394
CY22395
Logic Block Diagram — CY22395
XTALIN
OSC.
XTALOUT
Divider
LCLKE
LCLKD
CLKC
/2, /3, or /4
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
Divider
7-Bit
SHUTDOWN/OE
SCLK
4x4
SDAT
Crosspoint
Switch
Divider
7-Bit
S2/SUSPEND
PLL2
11-Bit P
8-Bit Q
Divider
7-Bit
LCLKB
LCLKA
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD
Pin Configurations
CY22393
CY22395
CY22394
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
CLKC
SHUTDOWN/OE
S2/SUSPEND
AV
DD
SCLK (S1)
SDAT (S0)
GND
CLKC
SHUTDOWN/OE
S2/SUSPEND
AV
DD
SCLK (S1)
SDAT (S0)
GND/LGND
1
2
3
4
5
6
1
2
3
4
5
6
16
15
14
13
12
16
15
14
13
12
CLKC
SHUTDOWN/OE
S2/SUSPEND
AV
DD
SCLK (S1)
SDAT (S0)
GND
1
2
3
4
5
6
16
15
14
13
12
V
V
DD
V
DD
DD
AGND
AGND
AGND
XTALIN
XTALOUT
XBUF
XTALIN
XTALIN
XTALOUT
XBUF
XTALOUT
11
10
LV
DD
11
10
11
10
CLKD
CLKE
CLKA
CLKB
LCLKD
LCLKE
LCLKA
LCLKB
7
8
7
8
P–CLK
P+ CLK
CLKA
CLKB
7
8
9
9
9
Pin Definitions
PinNumber PinNumber PinNumber
Name
CLKC
VDD
CY22393
CY22394
CY22395
Description
Configurable clock output C
Power supply
1
2
1
2
1
2
AGND
3
3
3
Analog Ground
XTALIN
XTALOUT
XBUF
LVDD
CLKD or LCLKD
P–CLK
CLKE or LCLKE
P+ CLK
CLKB or LCLKB
4
5
6
N/A
7
N/A
8
N/A
9
4
5
6
N/A
N/A
7
N/A
8
4
5
N/A
6
7
N/A
8
N/A
9
Reference crystal input or external reference clock input
Reference crystal feedback
Buffered reference clock output
Low Voltage Clock Output Power Supply
Configurable clock output D; LCLKD referenced to LVDD
LV PECL Output[1]
Configurable clock output E; LCLKE referenced to LVDD
LV PECL Output[1]
9
Configurable clock output B; LCLKB referenced to LVDD
Note:
1. LVPECL outputs require an external termination network.
Document #: 38-07186 Rev. *B
Page 3 of 19
CY22393
CY22394
CY22395
Pin Definitions (continued)
PinNumber PinNumber PinNumber
Name
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AVDD
CY22393
CY22394
CY22395
Description
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
Configurable clock output A; LCLKA referenced to LVDD
Ground
Two Wire Serial Port Data. S0 value latched during start-up
Two Wire Serial Port Clock. S1 value latched during start-up
Analog Power Supply
S2/
General Purpose Input for Frequency Control; bit 2. Optionally
Suspend mode control input
SUSPEND
SHUTDOWN/
OE
16
16
16
Places outputs in three-state condition and shuts down chip
when LOW. Optionally, only places outputs in three-state
condition and does not shut down chip when LOW
CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Operation
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with
the reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Crystal Input
Configurable PLLs
The input crystal oscillator is an important feature of this family
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to two locations: the cross point switch and the PECL output
(CY22394). The output of PLL1 is also sent to a /2, /3, or /4
synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed via serial programming or
by external CMOS inputs, S0, S1, and S2. See the following
section on general-purpose Inputs for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the cross point switch. The frequency of PLL2 can be
changed via serial programming.
of parts because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, process, performance, and quality.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross point switch. The frequency of PLL3 can be
changed via serial programming.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.
General-Purpose Inputs
S2 is a general-purpose input that can be programmed to
allow for two different frequency settings. Options that may be
switched with this general-purpose input are as follows: the
frequency of PLL1, the output divider of CLKB, and the output
divider of CLKA.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start-up and used as the other two indexes
into this array.
Digital VCXO
The serial programming interface may be used to dynamically
change the capacitor load value on the crystal. A change in
crystal load capacitance corresponds with a change in the
reference frequency.
For special pullable crystals specified by Cypress, the capac-
itance pull range is +150 ppm to –150 ppm from midrange.
Document #: 38-07186 Rev. *B
Page 4 of 19
CY22393
CY22394
CY22395
Be aware that adjusting the frequency of the reference will
affect all frequencies on all PLLs in a similar manner since all
frequencies are derived from the single reference.
causing excess jitter. If one PLL is driving more than one
output, the negative phase of the PLL can be selected for one
of the outputs (CLKA–CLKD). This prevents the output edges
from aligning, allowing superior jitter performance.
Output Configuration
Power Supply Sequencing
Under normal operation there are four internal frequency
sources that may be routed via a programmable cross point
switch to any of the four programmable 7-bit output dividers.
The four sources are: reference, PLL1, PLL2, and PLL3. The
following is a description of each output.
For parts with multiple VDD pins, there are no power supply
sequencing requirements. The part will not be fully operational
until all VDD pins have been brought up to the voltages
specified in the “Operating Conditions” table.
CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. See the section on General-Purpose Inputs for more
information.
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of two programmable
registers. See the section on General-Purpose Inputs for more
information.
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register. For
the CY22394, CLKD is brought out as the complimentary
version of a LV PECL Clock referenced to CLKE, bypassing
both the cross point switch and 7-bit post divider.
All grounds should be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second-generation software application
that allows users to configure this family of devices. The
easy-to-use interface offers complete control of the many
features of this family including, but not limited to, input
frequency, PLL and output frequencies, and different
functional options. Data sheet frequency range limitations are
checked and performance tuning is automatically applied.
CyClocksRT also has a power estimation feature that allows
the user to see the power consumption of a specific configu-
ration. You can download a free copy of CyberClocks that
includes CyClocksRT for free on Cypress’s web site at
www.cypress.com
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency
rules which are not documented in this data sheet, but are
required for proper operation of the device. These rules can
be checked by using the latest version of CyClocksRT.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4. For the
CY22394, CLKE is brought out as an LV PECL Clock,
bypassing the post divider.
Junction Temperature Limitations
It is possible to program this family such that the maximum
Junction Temperature rating is exceeded. The package qJA is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum
ratings.
XBUF is simply the buffered reference.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While
driving multiple loads is possible with the proper termination it
is generally not recommended.
Dynamic Updates
The output divider registers are not synchronized with the
output clocks. Changing the divider value of an active output
will likely cause a glitch on that output.
Power-Saving Features
The SHUTDOWN/OE input three-states the outputs when
pulled LOW. If system shutdown is enabled, a LOW on this pin
also shuts off the PLLs, counters, reference oscillator, and all
other active components. The resulting current on the VDD
pins will be less than 5 mA (typical). After leaving shutdown
mode, the PLLs will have to relock.
The S2/SUSPEND input can be configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs can be shut off in nearly any combi-
nation. The only limitation is that if a PLL is shut off, all outputs
derived from it must also be shut off. Suspending a PLL shuts
off all associated logic, while suspending an output simply
forces a three-state condition.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL will likely cause the PLL try to
lock on an out-of-bounds condition. For this reason, it is
recommended that the PLL being programmed be turned off
during the update. This can be done by setting the PLL*_En
bit LOW.
PLL1, CLKA, and CLKB each have multiple registers
supplying data. Programming these resources can be accom-
plished safely by always programming an inactive register,
and then transitioning to that register. This allows these
resources to stay on during programming.
With the serial interface, each PLL and/or output can be
individually disabled. This provides total control over the power
savings.
The serial interface is active even with the SHUTDOWN/OE
pin LOW as the serial interface logic uses static components
and is completely self-timed. The part will not meet the IDDS
current limit with transitioning inputs.
Improving Jitter
Jitter Optimization Control is useful in mitigating problems
related to similar clocks switching at the same moment,
Document #: 38-07186 Rev. *B
Page 5 of 19
CY22393
CY22394
CY22395
Clk*_ACAdj[1:0]
Memory Bitmap Definitions
These bits modify the output predrivers, changing the duty
cycle through the pads. These are nominally set to 01, with a
higher value shifting the duty cycle higher. The performance of
the nominal setting is guaranteed.
Clk{A–D}_Div[6:0]
Each of the four main output clocks (CLKA–CLKD) features a
7-bit linear output divider. Any divider setting may be used
between 1 and 127 by programming the value of the desired
divider into this register. Odd divide values are automatically
duty-cycle corrected. Setting a divide value of zero powers
down the divider and forces the output to a three-state
condition.
CLKA and CLKB have two divider registers, selected by the
DivSel bit (which in turn is selected by S2, S1, and S0). This
allows dynamic changing of the output divider value. For the
CY22394 device, ClkD_Div = 000001.
Clk*_DCAdj[1:0]
These bits modify the DC drive of the outputs. The perfor-
mance of the nominal setting is guaranteed.
Clk*_DCAdj[1:0]
Output Drive Strength
–30% of nominal
Nominal
+15% of nominal
+50% of nominal
00
01
10
11
ClkE_Div[1:0]
CLKE has a simpler divider. For the CY22394, set
ClkE_Div = 01.
PLL*_Q[7:0]
ClkE_Div[1:0]
ClkE Output
Off
PLL1 0° Phase/4
PLL1 0° Phase/2
PLL1 0° Phase/3
PLL*_P[9:0]
PLL*_P0
00
01
10
11
These are the 8-bit Q value and 11-bit P values that determine
the PLL frequency. The formula is:
P
T
Q
FPLL = FREF × -------
T
Clk*_FS[2:0]
PT = (2 × (P + 3)) + PO
Qt = Q + 2
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1,
PLL2, and PLL3. Each PLL provides both positive and
negative phased outputs, for a total of seven clock sources.
Note that the phase is a relative measure of the PLL output
phases. No absolute phase relation exists at the outputs.
PLL*_LF[2:0]
These bits adjust the loop filter to optimize the stability of the
PLL. The following table can be used to guarantee stability.
However, CyClocksRT uses a more complicated algorithm to
set the loop filter for enhanced jitter performance. It is recom-
mended to use the Print Preview function in CyClocksRT to
determine the charge pump settings for optimal jitter perfor-
mance.
Clk*_FS[2:0]
000
Clock Source
Reference Clock
001
Reserved
010
011
100
101
110
111
PLL1 0° Phase
PLL1 180° Phase
PLL2 0° Phase
PLL2 180° Phase
PLL3 0° Phase
PLL3 180° Phase
PLL*_LF[2:0]
PT Min
16
232
627
835
PT Max
231
626
834
1043
1600
000
001
010
011
100
1044
Xbuf_OE
PLL*_En
This bit enables the XBUF output when HIGH. For the
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must
have a divider setting of zero (off). Since the PLL1_En bit is
dynamic, internal logic automatically turns off dependent
outputs when PLL1_En goes LOW.
CY22395, Xbuf_OE = 0.
PdnEn
This bit selects the function of the SHUTDOWN/OE pin. When
this bit is HIGH, the pin is an active LOW shutdown control.
When this bit is LOW, this pin is an active HIGH output enable
control.
DivSel
This bit controls which register is used for the CLKA and CLKB
dividers.
Document #: 38-07186 Rev. *B
Page 6 of 19
CY22393
CY22394
CY22395
OscCap[5:0]
OscCap
00H–20H
20H–30H
30H–40H
This controls the internal capacitive load of the oscillator. The
Crystal Freq\ R 30Ω 60Ω 30Ω 60Ω 30Ω 60Ω
approximate effective crystal load capacitance is:
8–15 MHz
15–20 MHz
20–25 MHz
25–30 MHz
00
01
01
10
01
10
10
10
01
01
10
10
10
10
10
11
01
10
10
11
10
10
11
CLOAD = 6pF + (OscCap × 0.375pF)
Set to zero for external reference clock.
NA
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These
should always be set according to the following table. The
parameters are the Crystal Frequency, Internal Crystal
Parasitic Resistance (available from the manufacturer), and
the OscCap setting during crystal start-up (which occurs when
power is applied, or after shutdown is released). If in doubt,
use the next higher setting.
For external reference, the following table must be used.
External Freq (MHz) 1–25 25–50 50–90 90–166
OscDrv[1:0]
00
01
10
11
Reserved
These bits must be programmed LOW for proper operation of
the device.
Serial Programming Bitmaps — Summary Tables
Addr DivSel
b7
b6
b5
b4
b3
b2
b1
b0
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
ClkD_FS[2:1]
Clk{C,X}_ACAdj[1:0]
ClkX_DCAdj[1]
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkC_FS[2:1]
Clk{A,B,D,E}_ACAdj[1:0]
Clk{D,E}_DCAdj[1]
ClkB_FS[2:1]
PdnEn
ClkA_FS[2:1]
ClkE_Div[1:0]
Clk{A,B}_DCAdj[1]
Xbuf_OE
ClkC_DCAdj[1]
PLL2_Q[7:0]
PLL2_P[7:0]
PLL2_LF[2:0]
Reserved
Reserved
PLL2_En
PLL3_En
PLL2_PO
PLL3_PO
PLL2_P[9:8]
PLL3_Q[7:0]
PLL3_P[7:0]
PLL3_LF[2:0]
Osc_Cap[5:0]
PLL3_P[9:8]
Osc_Drv[1:0]
S2
Addr
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
(1,0)
b7
b6
b5
b4
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b3
b2
b1
b0
000
001
010
011
DivSel
DivSel
DivSel
DivSel
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
Document #: 38-07186 Rev. *B
Page 7 of 19
CY22393
CY22394
CY22395
S2
Addr
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
(1,0)
b7
b6
b5
b4
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b3
b2
b1
b0
100
101
110
111
DivSel
DivSel
DivSel
DivSel
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
Data Frame
Serial Programming Interface (SPI) Protocol
and Timing
The CY22393,CY22394 and CY22395 utilizes a 2-serial-wire
interface SDAT and SCLK that operates up to 400 kbits/sec in
Read or Write mode. The basic Write serial format is as
follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is
illustrated in Figure 2.
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 4.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W
bit, followed by register address (eight bits) and register data
(eight bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Default Startup Condition for the CY22393/94/95
Acknowledge Pulse
The default (programmed) condition of each device is
During Write Mode the CY22393,CY22394 and CY22395 will
respond with an Acknowledge pulse after every eight bits. This
is accomplished by pulling the SDAT line LOW during the N*9th
clock cycle as illustrated in Figure 5. (N = the number of bytes
transmitted). During Read Mode the acknowledge pulse after
the data packet is sent is generated by the master.
generally set by the distributor, who will program the device
using
a customer-specified JEDEC file produced by
CyClocksRT, Cypress’s proprietary development software.
Parts shipped by the factory are blank and unprogrammed. In
this condition, all bits are set to 0, all outputs are three-stated,
and the crystal oscillator circuit is active.
While users can develop their own subroutine to program any
or all of the individual registers as described in the following
pages, it may be easier to simply use CyClocksRT to produce
the required register setting file.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is
followed by an acknowledge bit from the slave (ack = 0/LOW).
The next eight bits must contain the data word intended for
storage. After the data word is received, the slave responds
with another acknowledge bit (ack = 0/LOW), and the master
must end the write sequence with a STOP condition.
Device Address
The device address is a 7-bit value that is configured during
Field Programming. By programming different device
addresses, two or more parts can be connected to the serial
interface and be independently controlled. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.
Writing Multiple Bytes
The default serial interface address is 69H, but should there
be a conflict with any other devices in your system, this can
also be changed using CyClocksRT.
In order to write more than one byte at a time, the master does
not end the write sequence with a stop condition. Instead, the
master can send multiple contiguous bytes of data to be
stored. After each byte, the slave responds with an
acknowledge bit, just like after the first byte, and will accept
data until the acknowledge bit is responded to by the STOP
condition. When receiving multiple bytes, the CY22393,
CY22394, and CY22395 internally increments the register
address.
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is LOW as illustrated in Figure 3.
Document #: 38-07186 Rev. *B
Page 8 of 19
CY22393
CY22394
CY22395
master generates
a
START condition following the
Read Operations
acknowledge. This terminates the write operation before any
data is stored in the address, but not before the internal
address pointer is set. Next the master reissues the control
byte with the R/W byte set to ‘1’. The CY22393,CY22394 and
CY22395 then issues an acknowledge and transmits the 8-bit
word. The master device does not acknowledge the transfer,
but does generate a STOP condition which causes the
CY22393,CY22394 and CY22395 to stop transmission.
Read operations are initiated the same way as Write opera-
tions except that the R/W bit of the slave address is set to ‘1’
(HIGH). There are three basic read operations: current
address read, random read, and sequential read.
Current Address Read
The CY22393,CY22394 and CY22395 has an onboard
address counter that retains 1 more than the address of the
last word access. If the last word written or read was word ‘n’,
then a current address read operation would return the value
stored in location ‘n+1’. When the CY22393,CY22394 and
CY22395 receives the slave address with the R/W bit set to a
‘1’, the CY22393,CY22394 and CY22395 issues an
acknowledge and transmits the 8-bit word. The master device
does not acknowledge the transfer, but does generate a STOP
condition, which causes the CY22393,CY22394 and CY22395
to stop transmission.
Sequential Read
Sequential read operations follow the same process as
random reads except that the master issues an acknowledge
instead of a STOP condition after transmission of the first 8-bit
data word. This action results in an incrementing of the internal
address pointer, and subsequently output of the next 8-bit data
word. By continuing to issue acknowledges instead of STOP
conditions, the master may serially read the entire contents of
the slave device memory. Note that register addresses outside
of 08H to 1BH and 40H to 57H can be read from but are not
real registers and do not contain configuration information.
When the internal address pointer points to the FFH register,
after the next increment, the pointer will point to the 00H
register.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first
the word address must be set. This is accomplished by
sending the address to the CY22393,CY22394 and CY22395
as part of a write operation. After the word address is sent, the
SCL
SDAT
STOP
Address or
Acknowledge
Valid
Data may
Condition
START
Condition
be changed
Figure 1. Data Transfer Sequence on the Serial Bus
Document #: 38-07186 Rev. *B
Page 9 of 19
CY22393
CY22394
CY22395
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
1 Bit
Slave
ACK
1 Bit
Slave
ACK
SDAT Write
R/W = 0
Multiple
7-bit
8-bit
8-bit
8-bit
8-bit
8-bit
8-bit
Contiguous
Registers
Device
Register Register Register
Register
Register
Data
Register
Data
Address
Address Data
Data
(XXH+1)
Data
(XXH)
(XXH)
(XXH+2)
(FFH)
(00H)
Stop Signal
Start Signal
1 Bit
1 Bit
1 Bit
1 Bit
R/W = 1
Slave
ACK
Slave
ACK
Master
ACK
SDAT Read
7-bit
Current
Address
Read
8-bit
Device
Register
Data
Address
Stop Signal
Start Signal
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
1 Bit
R/W = 0
Slave
ACK
Master
ACK
Master
ACK
Master
ACK
Master
ACK
Master
ACK
Slave
ACK
Master
ACK
SDAT Read
Multiple
7-bit
8-bit
7-bit
8-bit
8-bit
8-bit
8-bit
Contiguous
Registers
Device
Address
Register Device
Register
Register
Register
Data
Register
Data
Address
(XXH)
Data
(XXH)
Data
(FFH)
Address
+R/W=1
(XXH+1)
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Figure 2. Data Frame Architecture
Transition
to next Bit
Data Valid
SDAT
tDH
tSU
CLKHIGH
VIH
VIL
SCLK
CLKLOW
Figure 3. Data Valid and Data Transition Periods
Serial Programming Interface Timing
SDAT
SCLK
Transition
to next Bit
START
STOP
Figure 4. Start and Stop Frame
Document #: 38-07186 Rev. *B
Page 10 of 19
CY22393
CY22394
CY22395
SDAT
+
+
+
+
START
D7
D6
D1
D0
DA6
DA5 DA0
R/W
ACK
RA7
RA6 RA1
RA0
ACK
ACK
STOP
+
+
SCLK
Figure 5. Frame Format (Device Address, R/W, Register Address, Register Data)
Serial Programming Interface Timing Specifications
Parameter
Description
Min.
Max.
Unit
fSCLK
Frequency of SCLK
Start mode time from SDA LOW to SCL LOW
SCLK LOW period
400
kHz
µs
µs
µs
ns
ns
ns
ns
µs
µs
0.6
1.3
0.6
100
0
CLKLOW
CLKHIGH
tSU
SCLK HIGH period
Data transition to SCLK HIGH
Data hold (SCLK LOW to data transition)
Rise time of SCLK and SDAT
Fall time of SCLK and SDAT
Stop mode time from SCLK HIGH to SDAT HIGH
Stop mode to Start mode
tDH
300
300
0.6
1.3
Document #: 38-07186 Rev. *B
Page 11 of 19
CY22393
CY22394
CY22395
Junction Temperature.................................................. 125°C
Data Retention @ Tj=125×C .................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage............................................... –0.5V to +7.0V
DC Input Voltage............................–0.5V to + (AVDD + 0.5V)
Storage Temperature ..................................–65°C to +125°C
(per MIL-STD-883, Method 3015) ........................... > 2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Operating Conditions[2]
Parameter
VDD/AVDD/LVDD
LVDD
Description
Part Numbers
All
22395
Commercial Operating Temperature, Ambient All
Min.
3.135
2.375
0
Typ
3.3
2.5
Max.
3.465
2.625
+70
+85
15
30
166
150
Unit
V
V
°C
°C
Supply Voltage
2.5V Output Supply Voltage
TA
Industrial Operating Temperature, Ambient
Max. Load Capacitance
All
All
All
All
All
–40
CLOAD_OUT
fREF
pF
External Reference Crystal
8
1
1
MHz
MHz
MHz
External Reference Clock,[3] Commercial
External Reference Clock,[3] Industrial
3.3V Electrical Characteristics
Parameter
IOH
IOL
CXTAL_MIN
Description
Output High Current[4]
Output Low Current[4]
Conditions
VOH = (L)VDD – 0.5, (L)VDD = 3.3V
VOL = 0.5, (L)VDD = 3.3V
Min.
12
12
Typ.
Max.
Unit
mA
mA
pF
pF
pF
AVDD
AVDD
µA
24
24
6
30
7
Crystal Load Capacitance[4] Capload at minimum setting
CXTAL_MAX Crystal Load Capacitance[3] Capload at maximum setting
CIN
VIH
VIL
IIH
Input Pin Capacitance[4]
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current
Except crystal pins
CMOS levels,% of AVDD
CMOS levels,% of AVDD
VIN = AVDD – 0.3 V
VIN = +0.3 V
70%
30%
10
10
<1
<1
IIL
Input LOW Current
µA
IOZ
IDD
Output Leakage Current
Total Power Supply Current 3.3V Power Supply;
Three-state outputs
10
µA
mA
50
100
5
2 outputs @ 20 MHz; 4 outputs @ 40 MHz
3.3V Power Supply;
mA
2 outputs @ 166 MHz; 4 outputs @ 83 MHz
IDDS
Total Power Supply Current in Shutdown active
20
µA
Shutdown Mode
2.5V Electrical Characteristics (CY22395 only)[5]
Parameter
IOH_2.5
IOL_2.5
Description
Output High Current[4]
Output Low Current[4]
Conditions
VOH = LVDD – 0.5, LVDD = 2.5 V
VOL = 0.5, LVDD = 2.5 V
Min.
8
8
Typ.
16
16
Max.
Unit
mA
mA
Notes:
2. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
3. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.
DD
4. Guaranteed by design, not 100% tested.
5. V
is only specified and characterized at 3.3V ± 5% and 2.5V ± 5%. V
may be powered at any value between 3.465 and 2.375.
DDL
DDL
Document #: 38-07186 Rev. *B
Page 12 of 19
CY22393
CY22394
CY22395
3.3V Switching Characteristics
Parameter
1/t1
Description
Conditions
Min.
Typ.
Max.
200
166
400
Unit
MHz
MHz
MHz
Output Frequency[4, 6] Clock output limit, CMOS, Commercial
Clock output limit, CMOS, Industrial
Clock output limit, PECL, Commercial (CY22394
100
125
only)
Clock output limit, PECL, Industrial (CY22394
only)
375
MHz
t2
Output Duty Cycle[4, 7] Duty cycle for outputs, defined as t2 ³ t1,
Fout<100 MHz, divider>=2,
45%
50%
50%
55%
measured at VDD/2
Duty cycle for outputs, defined as t2 ³ t1,
Fout>100 MHz or divider = 1,
measured at VDD/2
40%
60%
t3
t4
t5
t6
v7
t8
t9
Rising Edge Slew
Rate[4]
Output clock rise time, 20% to 80% of VDD
0.75
0.75
1.4
1.4
150
400
0
V/ns
V/ns
ns
Falling Edge Slew
Output clock fall time, 20% to 80% of VDD
Rate[4]
Output three-state
Timing[4]
Time for output to enter or leave three-state
mode after SHUTDOWN/OE switches
300
0.2
3
Clock Jitter[4, 8]
Peak-to-peak period jitter, CLK outputs
ps
measured at VDD/2
P+/P– Crossing Point[4] Crossing point referenced to Vdd/2, balanced
resistor network (CY22394 only)
–0.2
V
P+/P– Jitter[4, 8]
Peak-to-peak period jitter, P+/P– outputs
200
1.0
ps
measured at crossing point (CY22394 only)
Lock Time[4]
PLL Lock Time from Power-up
ms
2.5V Switching Characteristics (CY22395 only)[5]
Parameter
1/t1_2.5
t2_2.5
Description
Conditions
Clock output limit, LVCMOS
Min.
Typ.
Max.
133
60%
Unit
MHz
Output Frequency[4, 6]
Output Duty Cycle[4, 7]
Duty cycle for outputs, defined as t2 ÷ t1
40%
50%
measured at LVDD/2
t3_2.5
t4_2.5
Rising Edge Slew Rate[4] Output clock rise time, 20% to 80% of LVDD
Falling Edge Slew Rate[4] Output clock fall time, 20% to 80% of LVDD
0.5
0.5
1.0
1.0
V/ns
V/ns
Switching Waveforms
All Outputs, Duty Cycle and Rise/Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Notes:
6. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
7. Reference Output duty cycle depends on XTALIN duty cycle.
8. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07186 Rev. *B
Page 13 of 19
CY22393
CY22394
CY22395
Output Three State Timing
OE
t
5
t
5
ALL
THREE-STATE
OUTPUTS
CLK Output Jitter
t
6
CLK
OUTPUT
P+/P– Crossing Point and Jitter
t
8
P-
v
7
V
/2
DD
P+
CPU Frequency Change
SELECT
OLD SELECT
NEW SELECT STABLE
t
9
F
new
F
old
CPU
Test Circuit
AVDD
CLK out
CLOAD
VDD
0.1
µF
P+/P- out
(L)VDD
0.1
µF
GND
Ordering Information
Ordering Code
CY22393ZC-XXX
CY22393ZC-XXXT
CY22393ZI-XXX
CY22393ZI-XXXT
CY22393FC
Package Type
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
Product Flow
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Document #: 38-07186 Rev. *B
Page 14 of 19
CY22393
CY22394
CY22395
Ordering Information
Ordering Code
CY22393FCT
CY22393FI
CY22393FIT
CY22394ZC-XXX
CY22394ZC-XXXT
CY22394ZI-XXX
CY22394ZI-XXXT
CY22394FC
CY22394FCT
CY22394FI
CY22394FIT
CY22395ZC-XXX
CY22395ZC-XXXT
CY22395ZI-XXX
CY22395ZI-XXXT
CY22395FC
Package Type
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
Product Flow
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
CY22395FCT
CY22395FI
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
Lead Free Devices
CY22393ZXC-XXX
CY22393ZXC-XXXT
CY22393ZXI-XXX
CY22393ZXI-XXXT
CY22393FXC
CY22393FXCT
CY22393FXI
CY22393FXIT
CY22394ZXC-XXX
CY22394ZXC-XXXT
CY22394ZXI-XXX
CY22394ZXI-XXXT
CY22394FXC
CY22394FXCT
CY22394FXI
CY22394FXIT
CY22395ZXC-XXX
CY22395ZXC-XXXT
CY22395ZXI-XXX
CY22395ZXI-XXXT
CY22395FXC
CY22395FXCT
CY22395FXI
CY22395FXIT
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
16-Pin TSSOP - Tape and Reel
Document #: 38-07186 Rev. *B
Page 15 of 19
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY22393
CY22394
CY22395
Package Diagram
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05 gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
Document #: 38-07186 Rev. *B
Page 16 of 19
CY22393
CY22394
CY22395
Ordering Information
Ordering Code
CY22393ZC-XXX
CY22393ZC-XXXT
CY22393ZI-XXX
CY22393ZI-XXXT
CY22393FC
CY22393FCT
CY22393FI
CY22393FIT
CY22394ZC-XXX
CY22394ZC-XXXT
CY22394ZI-XXX
CY22394ZI-XXXT
CY22394FC
CY22394FCT
CY22394FI
CY22394FIT
Package Type
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
Product Flow
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
CY22395ZC-XXX
CY22395ZC-XXXT
CY22395ZI-XXX
CY22395ZI-XXXT
CY22395FC
CY22395FCT
CY22395FI
Lead Free Devices
CY22393ZXC-XXX
CY22393ZXC-XXXT
CY22393ZXI-XXX
CY22393ZXI-XXXT
CY22393FXC
CY22393FXCT
CY22393FXI
CY22393FXIT
CY22394ZXC-XXX
CY22394ZXC-XXXT
CY22394ZXI-XXX
CY22394ZXI-XXXT
CY22394FXC
CY22394FXCT
CY22394FXI
CY22394FXIT
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP- Tape and Reel
16-Pin TSSOP
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
16-Pin TSSOP - Tape and Reel
16-Pin TSSOP
16-Pin TSSOP
16-Pin TSSOP
16-Pin TSSOP
CY22395ZXC-XXX
CY22395ZXI-XXX
CY22395FXC
CY22395FX I
Document #: 38-07186 Rev. *B
Page 17 of 19
CY22393
CY22394
CY22395
CyClocksRT is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07186 Rev. *B
Page 18 of 19
CY22393
CY22394
CY22395
Document History Page
Document Title: CY22393/CY22394/CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Document Number: 38-07186
Issue
Date
12/09/01
10/13/03
See ECN
Orig. of
Change
DSG
RGL
RGL
REV.
**
*A
ECN NO.
111984
129388
237755
Description of Change
Change from Spec number: 38-01144 to 38-07186
Added timing information
*B
Added Lead Free Devices
Document #: 38-07186 Rev. *B
Page 19 of 19
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