CY22393ZXE-XXX [CYPRESS]
Clock Generator, 166MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16;
| 型号： | CY22393ZXE-XXX |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 166MHz, CMOS, PDSO16, 4.40 MM, LEAD FREE, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总19页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22393
Automotive Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Automotive Three-PLL Serial-Programmable Flash-Programmable Clock Generator
■ CyClocksRT™ software support
■ AEC-Q100 Qualified
Features
■ Three integrated phase-locked loops (PLLs)
■ Available in A and E grade
■ Ultra-wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
Advanced Features
■ Improved linear crystal load capacitors
■ Flash programmability with external programmer
■ Field-programmable
■ Two-wire serial interface for in-system configurability
■ Configurable output buffer
■ Digital VCXO
■ Low-jitter, high-accuracy outputs
Functional Description
■ Power management options (Shutdown, OE, Suspend)
■ Configurable crystal drive strength
■ Frequency select through three external LVTTL inputs
■ 3.3-V operation
The CY22393 has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
■ 16-pin TSSOP package
Logic Block Diagram – CY22393
XTALIN
XBUF
OSC.
XTALOUT
CONFIGURATION
PLL1
FLASH
Divider
/2, /3, or /4
CLKE
11-Bit P
8-Bit Q
SHUTDOWN/OE
PLL2
Divider
7-Bit
SCLK
CLKD
11-Bit P
8-Bit Q
4x4
Crosspoint
Switch
SDAT
S2/SUSPEND
Divider
CLKC
7-Bit
PLL3
11-Bit P
8-Bit Q
Divider
CLKB
7-Bit
Divider
CLKA
7-Bit
Cypress Semiconductor Corporation
Document Number: 001-73555 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 23, 2014
CY22393
Contents
lPin Configuration............................................................. 3
Configurable PLLs....................................................... 3
General-Purpose Inputs .............................................. 4
Crystal Input ................................................................ 4
Crystal Drive Level and Power.................................... 4
Digital VCXO ............................................................... 4
Output Configuration ................................................... 4
Power-Saving Features............................................... 4
Improving Jitter............................................................ 5
Power Supply Sequencing .......................................... 5
CyClocksRT Software ...................................................... 5
Device Programming........................................................ 5
Junction Temperature Limitations ............................... 5
Dynamic Updates........................................................ 5
Memory Bitmap Definitions............................................. 5
Clk{A–D}_Div[6:0]........................................................ 5
ClkE_Div[1:0]............................................................... 5
Clk*_FS[2:0] ................................................................ 5
Xbuf_OE...................................................................... 6
PdnEn.......................................................................... 6
Clk*_ACAdj[1:0]........................................................... 6
Clk*_DCAdj[1:0] .......................................................... 6
PLL*_Q[7:0]................................................................. 6
PLL*_P[9:0] ................................................................. 6
PLL*_P0 ...................................................................... 6
PLL*_LF[2:0] ............................................................... 6
PLL*_En ...................................................................... 6
DivSel.......................................................................... 6
OscCap[5:0] ................................................................ 6
OscDrv[1:0] ................................................................. 6
Reserved..................................................................... 6
Serial Programming Bitmaps – Summary Tables ......... 7
Serial Bus Programming Protocol and Timing.............. 8
Default Startup Condition for the CY22393................. 8
Device Address ........................................................... 8
Data Valid.................................................................... 8
Data Frame ................................................................. 8
Acknowledge Pulse..................................................... 8
Write Operations............................................................... 8
Writing Individual Bytes............................................... 8
Writing Multiple Bytes.................................................. 8
Read Operations............................................................... 8
Current Address Read................................................. 8
Random Read ............................................................. 8
Sequential Read.......................................................... 8
Serial Programming Interface Timing........................... 10
Serial Programming Interface Timing Specifications . 10
Electrical Specifications ................................................ 11
Absolute Maximum Conditions.................................. 11
Operating Conditions................................................. 11
Recommended Crystal Specifications....................... 11
3.3 V Electrical Characteristics.................................. 11
3.3 V Switching Characteristics................................. 12
Switching Waveforms .................................................... 13
Test Circuit...................................................................... 14
Ordering Information...................................................... 15
Possible Configurations............................................. 15
Package Diagram............................................................ 16
Acronyms........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support....................... 19
Products.................................................................... 19
PSoC Solutions......................................................... 19
Document Number: 001-73555 Rev. *B
Page 2 of 19
CY22393
Pin Configuration
Figure 1. Pin Diagram - 16-Pin TSSOP CY22393
Pin Definitions
Name
CLKC
Pin Number
Description
1
2
Configurable clock output C
VDD
Power supply
AGND
XTALIN
XTALOUT
XBUF
3
Analog ground
4
Reference crystal input or external reference clock input
Reference crystal feedback
Buffered reference clock output
Configurable clock output D
Configurable clock output E
Configurable clock output B
Configurable clock output A
Ground
5
6
CLKD
7
CLKE
8
CLKB
9
CLKA
10
11
12
13
14
15
GND
SDAT (S0)
SCLK (S1)
AVDD
Serial port data. S0 value latched during start-up
Serial port clock. S1 value latched during start-up
Analog power supply
S2/
General-purpose input for frequency control; bit 2. Optionally, Suspend mode control input
SUSPEND
SHUTDOWN/
OE
16
Places outputs in tristate condition and shuts down chip when LOW. Optionally, only places outputs
in tristate condition and does not shut down chip when LOW
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
cross point switch. The frequency of PLL2 is changed using
serial programming.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to the
cross point switch. The output of PLL1 is also sent to a /2, /3, or
/4 synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming or
by external CMOS inputs, S0, S1, and S2. See General-Purpose
Inputs on page 4 for more detail.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross point switch. The frequency of PLL3 is changed using
serial programming.
Document Number: 001-73555 Rev. *B
Page 3 of 19
CY22393
General-Purpose Inputs
Digital VCXO
S2 is a general-purpose input that is programmed to enable two
frequency settings. The options that switch with this
general-purpose input are as follows: the frequency of PLL1, the
output divider of CLKB, and the output divider of CLKA.
The serial programming interface is used to dynamically change
the capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start-up and used as the other two indices into
this array.
For special pullable crystals specified by Cypress, the
capacitance pull range is +150 ppm to –150 ppm from midrange.
Be aware that adjusting the frequency of the reference affects all
frequencies on all PLLs in a similar manner because all
frequencies are derived from the single reference.
CLKA and CLKB have seven-bit dividers that point to one of the
two programmable settings (register 0 or register 1). Both clocks
share a single register control and both must be set to register 0,
or both must be set to register 1.
Output Configuration
Under normal operation there are four internal frequency
sources that are routed through a programmable cross point
switch to any of the four programmable 7-bit output dividers. The
four sources are: reference, PLL1, PLL2, and PLL3. The
following is a description of each output.
For example, the part may be programmed to use S0, S1, and
S2 (0, 0, 0 to 1, 1, 1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be
glitch-free.
■ CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section General-Purpose Inputs for more
information.
Crystal Input
The input crystal oscillator is an important feature of CY24293
because of its flexibility and performance features.
■ CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one of the two programmable
registers. See the section General-Purpose Inputs for more
information.
The oscillator inverter has programmable drive strength. This
enables maximum compatibility with crystals from various
manufacturers. Parallel resonant, fundamental mode crystals
should be used.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when nonlinear load
capacitance interacts with load, bias, supply, and temperature
changes. Nonlinear (FET gate) crystal load capacitors must not
be used for MPEG, communications, or other applications that
are sensitive to absolute frequency requirements.
■ CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
■ CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post
divider derives its value from one programmable register.
■ CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375 pF for a total crystal load range of 6 pF to
30 pF. Typical crystals have a CL specification in the range of
12 pF to 18 pF.
■ XBUF is the buffered reference.
The clock outputs are designed to drive a single-point load with
a total lumped load capacitance of 15 pF. While driving multiple
loads is possible with the proper termination, it is generally not
recommended.
For driven clock inputs, the input load capacitors can be
bypassed. This allows the clock chip to accept driven frequency
inputs up to 166 MHz. If the application requires a driven input,
leave XTALOUT floating.
Power-Saving Features
The SHUTDOWN/OE input tristates the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, reference oscillator, and all other
active components. The resulting current on the VDD pins is less
than 5 mA (typical). Relock the PLLs after leaving the shutdown
mode.
Crystal Drive Level and Power
Crystals are specified to accept a maximum drive level.
Generally, larger crystals can accept more power. For a specific
voltage swing, power dissipation in the crystal is proportional to
ESR and proportional to the square of the crystal frequency.
(Note that the actual ESR is sometimes much less than the value
specified by the crystal manufacturer.) Power is also almost
proportional to the square of CL.
The S2/SUSPEND input is configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs are shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
associated logic, while suspending an output simply forces a
tristate condition.
Power can be reduced to less than the DL specified in Recom-
mended Crystal Specifications on page 11 by selecting a
reduced frequency crystal with low CL and low R1 (ESR).
Document Number: 001-73555 Rev. *B
Page 4 of 19
CY22393
With the serial interface, each PLL and/or output is individually
disabled. This provides total control over the power savings.
Dynamic Updates
The output divider registers are not synchronized with the output
clocks. Changing the divider value of an active output is likely
cause a glitch on that output.
Improving Jitter
Jitter Optimization Control is useful for mitigating problems
related to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs
(CLKA–CLKD). This prevents the output edges from aligning and
allows superior jitter performance.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL can cause the PLL to try to lock
an out-of-bounds condition. Therefore, you must turn off the PLL
being programmed during the update. Do this by setting the
PLL*_En bit LOW.
Power Supply Sequencing
PLL1, CLKA, and CLKB each have multiple registers supplying
data. To program these resources safely, always program an
inactive register, and then transition to that register. This allows
these resources to stay active during programming.
There are no power supply sequencing requirements. The part
is not fully operational until all VDD pins are brought up to the
voltages specified in the Operating Conditions on page 11.
The serial interface is active even with the SHUTDOWN/OE pin
LOW as the serial interface logic uses static components and is
completely self-timed. The part does not meet the IDDS current
limit with transitioning inputs.
All grounds must be connected to the same ground plane.
CyClocksRT Software
CyClocksRT is our second-generation software application that
allows users to configure this device. The easy-to-use interface
offers complete control of the many features of this device
including, but not limited to, input frequency, PLL and output
frequencies, and different functional options. It checks the data
sheet frequency range limitations and automatically applies
performance tuning. CyClocksRT also has a power estimation
feature that allows you to see the power consumption of a
specific configuration. You can download a free copy of
CyberClocks that includes CyClocksRT on Cypress’s web site,
www.cypress.com.
Memory Bitmap Definitions
Clk{A–D}_Div[6:0]
Each of the four main output clocks (CLKA–CLKD) features a
7-bit linear output divider. Any divider setting between 1 and 127
may be used by programming the value of the desired divider
into this register. Odd divide values are automatically duty-cycle
corrected. Setting a divide value of zero powers down the divider
and forces the output to a tristate condition.
CLKA and CLKB have two divider registers, selected by the
DivSel bit (which, in turn, is selected by S2, S1, and S0). This
allows the output divider value to change dynamically.
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency rules
that are not documented in this datasheet, but are required for
proper operation of the device. Check these rules by using the
latest version of CyClocksRT.
ClkE_Div[1:0]
CLKE has a simpler divider (see Table 1).
Device Programming
Table 1. ClkE Divider
ClkE_Div[1:0]
ClkE Output
Part numbers starting with CY22392F are ‘field programmable’
devices. Field programmable devices are shipped
unprogrammed and must be programmed prior to installation on
a PCB. After a programming file (.jed) is created using the
CyberClocks software, devices can be programmed in small
quantities using the CY3672 programmer and CY3698[1]
adapter. Programming of the clock device should be done at
temperatures < 75 °C. Volume programming is available through
Cypress Semiconductor’s value-added distribution partners or
by using third-party programmers from BP Microsystems, HiLo
Systems, and others. For sufficiently large volumes, Cypress can
supply pre-programmed devices with a part number extension
that is configuration-specific.
00
01
10
11
Off
PLL1 0 ° Phase/4
PLL1 0 ° Phase/2
PLL1 0 ° Phase/3
Clk*_FS[2:0]
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1, PLL2,
and PLL3. Each PLL provides both positive and negative phased
outputs, for a total of seven clock sources (see Table 2). Note
that the phase is a relative measure of the PLL output phases.
No absolute phase relation exists at the outputs.
Junction Temperature Limitations
It is possible to program this family such that the maximum
junction temperature rating is exceeded. The package θJA is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the junction
temperature and package power dissipation maximum ratings.
Note
1. CY3698 only supports programming of only the 16-pin TSSOP package.
Document Number: 001-73555 Rev. *B
Page 5 of 19
CY22393
Table 2. Clock Source
Table 4. Loop Filter Settings
Clk*_FS[2:0]
000
Clock Source
Reference Clock
PLL*_LF[2:0]
PT Min
PT Max
231
000
001
010
011
100
16
232
627
835
1044
001
Reserved
626
010
PLL1 0 ° Phase
PLL1 180 ° Phase
PLL2 0 ° Phase
PLL2 180 ° Phase
PLL3 0 ° Phase
PLL3 180 ° Phase
834
011
1043
1600
100
101
110
PLL*_En
111
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must have
a divider setting of zero (off). Because the PLL1_En bit is
dynamic, internal logic automatically turns off dependent outputs
when PLL1_En goes LOW.
Xbuf_OE
This bit enables the XBUF output when HIGH.
PdnEn
DivSel
This bit selects the function of the SHUTDOWN/OE pin. When
this bit is HIGH, the pin is an active LOW shutdown control. When
this bit is LOW, this pin is an active HIGH output enable control.
This bit controls which register is used for the CLKA and CLKB
dividers.
Clk*_ACAdj[1:0]
OscCap[5:0]
These bits modify the output predrivers, changing the duty cycle
through the pads. These are nominally set to 01, with a higher
value shifting the duty cycle higher. The performance of the
nominal setting is guaranteed.
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
Equation 2
CLOAD = 6pF + (OscCap × 0.375pF)
Clk*_DCAdj[1:0]
Set to zero for external reference clock.
These bits modify the DC drive of the outputs. The performance
of the nominal setting is guaranteed.
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These must
always be set according to Table 5. The parameters are the
Crystal Frequency, Internal Crystal Parasitic Resistance
(equivalent series resistance), and the OscCap setting during
crystal start-up, which occurs when power is applied, or after
shutdown is released. If in doubt, use the next higher setting.
Table 3. Output Drive Strength
Clk*_DCAdj[1:0]
Output Drive Strength
–30% of nominal
Nominal
00
01
10
11
+15% of nominal
+50% of nominal
Table 5. Crystal Oscillator Gain Settings
OscCap
00H–20H
20H–30H
30H–40H
PLL*_Q[7:0]
Crystal Freq\ R 30 Ω 60 Ω 30 Ω 60 Ω 30 Ω 60 Ω
PLL*_P[9:0]
PLL*_P0
8–15 MHz
15–20 MHz
20–25 MHz
25–30 MHz
00
01
01
10
01
10
10
10
01
01
10
10
10
10
10
11
01
10
10
11
10
10
11
These are the 8-bit Q value and 11-bit P values that determine
the PLL frequency. The formula is:
NA
PT
⎛
⎝
⎞
⎠
-------
For external reference, the use Table 6.
Table 6. Osc Drv for External Reference
FPLL = FREF
×
QT
Equation 1
PT = (2 × (P + 3)) + PO
QT = Q + 2
External Freq (MHz) 1–25
OscDrv[1:0] 00
25–50
50–90 90–166
10 11
01
PLL*_LF[2:0]
Reserved
These bits adjust the loop filter to optimize the stability of the PLL.
Table 4 can be used to guarantee stability. However,
CyClocksRT uses a more complicated algorithm to set the loop
filter for enhanced jitter performance. Use the Print Preview
function in CyClocksRT to determine the charge pump settings
for optimal jitter performance.
These bits must be programmed LOW for proper operation of the
device.
Document Number: 001-73555 Rev. *B
Page 6 of 19
CY22393
Serial Programming Bitmaps – Summary Tables
Addr
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
DivSel
b7
b6
b5
b4
b3
b2
b1
b0
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkD_FS[2:1]
ClkC_FS[2:1]
ClkB_FS[2:1]
ClkA_FS[2:1]
Clk{C,X}_ACAdj[1:0]
ClkX_DCAdj[1]
Clk{A,B,D,E}_ACAdj[1:0]
Clk{D,E}_DCAdj[1]
PdnEn
Xbuf_OE
ClkE_Div[1:0]
ClkC_DCAdj[1]
Clk{A,B}_DCAdj[1]
PLL2_Q[7:0]
PLL2_P[7:0]
PLL2_LF[2:0]
Reserved
Reserved
PLL2_En
PLL3_En
PLL2_PO
PLL3_PO
PLL2_P[9:8]
PLL3_Q[7:0]
PLL3_P[7:0]
PLL3_LF[2:0]
Osc_Cap[5:0]
PLL3_P[9:8]
Osc_Drv[1:0]
Addr
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
S2 (1,0)
b7
b6
b5
b4
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b3
b2
b1
b0
000
DivSel
DivSel
DivSel
DivSel
DivSel
DivSel
DivSel
DivSel
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_P[9:8]
001
010
011
100
101
110
111
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
Document Number: 001-73555 Rev. *B
Page 7 of 19
CY22393
During Read Mode, the master generates the acknowledge
pulse after the data packet is read.
SerialBusProgrammingProtocolandTiming
The CY22393 has a 2-wire serial interface for in-system
programming. They use the SDAT and SCLK pins, and operate
up to 400 kbit/s in Read or Write mode. Except for the data hold
time, it is compliant with the I2C bus standard. The basic Write
serial format is as follows:
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit.
The basic serial format is illustrated in Figure 3 on page 9.
Default Startup Condition for the CY22393
Writing Multiple Bytes
The default (programmed) condition of CY24293 is set by the
distributor, who programs the device using a customer-specified
JEDEC file produced by CyClocksRT, Cypress’s proprietary
development software. Parts shipped by the factory are blank
and unprogrammed. In this condition, all bits are set to 0, all
outputs are tristated, and the crystal oscillator circuit is active.
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition. Instead, the master
sends multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, the same as
after the first byte, and accepts data until the STOP condition
responds to the acknowledge bit. When receiving multiple bytes,
the CY22393 internally increment the register address.
While users can develop their own subroutine to program any or
all of the individual registers as described in the following pages,
it may be easier to simply use CyClocksRT to produce the
required register setting file.
Read Operations
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Device Address
The device address is a 7-bit value that is configured during Field
Programming. By programming different device addresses, two
or more parts are connected to the serial interface and can be
independently controlled. The device address is combined with
a read/write bit as the LSB and is sent after each start bit.
Current Address Read
The CY22393 have an onboard address counter that retains “1”
more than the address of the last word access. If the last word
written or read was word ‘n’, then a current address read
operation returns the value stored in location ‘n+1’. When the
CY22393 receives the slave address with the R/W bit set to a ‘1’,
it issues an acknowledge and transmit the 8-bit word. The master
device does not acknowledge the transfer, but generates a
STOP condition, which causes the CY22393 to stop
transmission.
The default serial interface address is 69H, but there must not
be a conflict with any other devices in your system. This can also
be changed using CyClocksRT.
Data Valid
Data is valid when the clock is HIGH, and can only be
transitioned when the clock is LOW as illustrated in Figure 4 on
page 9.
Random Read
Data Frame
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. Do this by sending the address to the
CY22393 as part of a write operation. After the word address is
sent, the master generates a START condition following the
acknowledge. This terminates the write operation before any
data is stored in the address, but not before setting the internal
address pointer. Next, the master reissues the control byte with
the R/W byte set to ‘1’. The CY22393, then, issues an
acknowledge and transmits the 8-bit word. The master device
does not acknowledge the transfer, but generates a STOP
condition which causes CY22393 to stop transmission.
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 5 on page 10.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by the register address (eight bits) and register data
(eight bits).
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
Sequential Read
Acknowledge Pulse
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmitting the first 8-bit data word. This
action increments the internal address pointer, and subsequently
outputs the next 8-bit data word. By continuing to issue
During Write Mode, the CY22393 responds with an
Acknowledge pulse after every eight bits. To do this, it pulls the
SDAT line LOW during the N*9th clock cycle, as illustrated in
Figure 6 on page 10. (N = the number of bytes transmitted).
Document Number: 001-73555 Rev. *B
Page 8 of 19
CY22393
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. Note that
register addresses outside of 08H to 1BH and 40H to 57H can
be read from but are not real registers and do not contain
configuration information. When the internal address pointer
points to the FFH register, after the next increment, the pointer
points to the 00H register.
Figure 2. Data Transfer Sequence on the Serial Bus
SCLK
SDAT
STOP
Address or
Acknowledge
Valid
Data may
be changed
Condition
START
Condition
Figure 3. Data Frame Architecture
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
R/W = 0
SDAT Write
Multiple
Contiguous
Registers
7-bit
Device
Address
8-bit
8-bit
8-bit
8-bit
Register
Data
8-bit
Register
Data
8-bit
Register
Data
Register Register Register
Address Data
(XXH)
Data
(XXH+1)
(XXH)
(XXH+2)
(FFH)
(00H)
Stop Signal
Start Signal
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
R/W = 1
SDAT Read
7-bit
Device
Address
Current
Address
Read
8-bit
Register
Data
Stop Signal
Start Signal
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
R/W = 0
SDAT Read
Multiple
Contiguous
Registers
7-bit
Device
Address
8-bit
7-bit
8-bit
Register
Data
8-bit
Register
Data
8-bit
Register
Data
8-bit
Register
Data
Register Device
Address
(XXH)
Address
+R/W=1
(XXH)
(XXH+1)
(FFH)
(00H)
Stop Signal
Start Signal
Repeated
Start bit
Figure 4. Data Valid and Data Transition Periods
Transition
to next Bit
Data Valid
SDAT
tDH
tSU
CLKHIGH
VIH
VIL
SCLK
CLKLOW
Document Number: 001-73555 Rev. *B
Page 9 of 19
CY22393
Serial Programming Interface Timing
Figure 5. Start and Stop Frame
SDAT
SCLK
Transition
to next Bit
START
STOP
Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data)
SDAT
+
+
+
+
START
D7
D6
D1
D0
DA6
DA5 DA0
R/W
ACK
RA7
RA6 RA1
RA0
ACK
ACK
STOP
+
+
SCLK
Serial Programming Interface Timing Specifications
Parameter
fSCLK
Description
Min
Max
400
–
Unit
kHz
μs
Frequency of SCLK
–
Start mode time from SDA LOW to SCL LOW
SCLK LOW period
0.6
1.3
0.6
100
100
–
CLKLOW
CLKHIGH
tSU
–
μs
SCLK HIGH period
–
μs
Data transition to SCLK HIGH
Data hold (SCLK LOW to data transition)
Rise time of SCLK and SDAT
Fall time of SCLK and SDAT
–
ns
tDH
–
ns
300
300
–
ns
–
ns
Stop mode time from SCLK HIGH to SDAT HIGH
Stop mode to Start mode
0.6
1.3
μs
–
μs
Document Number: 001-73555 Rev. *B
Page 10 of 19
CY22393
Maximum programming cycles ........................................100
Package power dissipation (A-Grade) ..................... 350 mW
Package power dissipation (E-Grade) ..................... 217 mW
Electrical Specifications
Absolute Maximum Conditions
Supply voltage .............................................–0.5 V to +7.0 V
DC input voltage ......................... –0.5 V to + (AVDD + 0.5 V)
Storage temperature ................................ –65 °C to +125 °C
Junction temperature
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2000 V
Latch-up (per JEDEC 17) ................................... > ±200 mA
Stresses exceeding absolute maximum conditions may cause
permanent damage to the device. These conditions are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in the operation
sections of this datasheet is not implied. Extended exposure to
absolute maximum conditions may affect reliability.
A Grade................................................................. 125 °C
E Grade.................................................................150 °C
Data retention at TJ = 125 °C ...............................> 10 years
Data retention at TJ = 150 °C .................................> 2 years
Operating Conditions
Parameter
/AV
Description
Min
3.135
–40
-40
–
Typ
3.3
–
Max
3.465
85
Unit
V
V
T
Supply voltage
DD
DD
Automotive A-Grade operating temperature, Ambient
Automotive E-Grade operating temperature, Ambient
Maximum load capacitance
°C
A
T
125
15
°C
A
C
–
–
–
pF
LOAD_OUT
f
External reference crystal
8
30
MHz
MHz
REF
[2]
External reference clock , Automotive
1
150
Recommended Crystal Specifications
Parameter
Description
Nominal crystal frequency
Description
Min
Typ
Max Unit
F
Parallel resonance, fundamental mode
8
8
–
–
–
–
30
20
50
2
MHz
pF
NOM
C
R
Nominal load capacitance
Equivalent series resistance (ESR)
Crystal drive level
LNOM
1
Fundamental mode
–
Ω
DL
No external series resistor assumed
0.5
mW
3.3 V Electrical Characteristics
[3]
Parameter
Description
Conditions
Min
12
12
–
Typ
24
24
6
Max Unit
[4, 5]
I
I
Output high current
V
V
= V – 0.5 V, V = 3.3 V
–
–
–
–
–
–
mA
mA
pF
OH
OL
OH
DD
DD
[4, 5]
Output low current
= 0.5 V, V = 3.3 V
DD
OL
[4]
C
C
C
Crystal load capacitance
Crystal load capacitance
Capload at minimum setting
Capload at maximum setting
Except crystal pins
XTAL_MIN
[3]
–
30
7
pF
XTAL_MAX
[4]
Input pin capacitance
–
pF
IN
IH
IL
V
V
I
High-level input voltage
Low-level input voltage
Input high current
CMOS levels,% of AV
CMOS levels,% of AV
70%
–
–
AV
DD
DD
DD
DD
30% AV
V
V
= AV – 0.3 V
–
<1
<1
10
10
10
μA
μA
μA
IH
IN
IN
DD
I
I
Input low current
= +0.3 V
–
IL
OZ
Output leakage current
Three-state outputs (OE = Low)
–
Notes
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.
DD
3. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
4. Guaranteed by design, not 100% tested.
5. Profile configuration through CyberClocks (JEDEC file) should be so generated such that Drive strength should be at ‘Mid Low’ or above.
Document Number: 001-73555 Rev. *B
Page 11 of 19
CY22393
3.3 V Electrical Characteristics (continued)
[3]
Parameter
Description
Conditions
Min
Typ
Max Unit
I
Total power supply current
3.3-V power supply; 2 outputs at 20 MHz;
–
50
–
mA
mA
μA
DD
[6,7]
4 outputs at 40 MHz
3.3-V power supply; 2 outputs at 166 MHz;
–
–
100
5
–
[6,7]
4 outputs at 83 MHz
I
Total power supply current in shutdown mode Shutdown active
20
DDS
3.3 V Switching Characteristics
Parameter Description
1/t1
Conditions
Min
Typ
Max
166
Unit
Output frequency [8, 9]
Output duty cycle [8, 10]
Clock output limit, CMOS, Automotive
–
–
MHz
t2
Duty cycle for outputs, defined as t2 ÷ t1, 45%
Fout < 100 MHz, divider > 2, measured at
50%
55%
VDD/2
Duty cycle for outputs, defined as t2 ÷ t1, 40%
Fout > 100 MHz or divider = 1, measured at
50%
60%
VDD/2
t3
t4
t5
Rising edge slew rate [8]
Falling edge slew rate [8]
Output three-state timing [8]
Output clock rise time, 20% to 80% of VDD 0.75
1.4
1.4
150
–
–
V/ns
V/ns
ns
Output clock fall time, 20% to 80% of VDD
0.75
–
Time for output to enter or leave three-state
mode after SHUTDOWN/OE switches
300
t6
t7
Clock jitter [8, 9]
Lock time [8]
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–
–
400
1.0
–
3
ps
PLL lock time from power-up
ms
Notes
6. Profile configuration through CyberClocks (JEDEC file) should be so generated such that for E-Grade, I max < 56 mA (considering T max = 125 °C).
DD
A
7. Profile configuration through CyberClocks (JEDEC file) should be so generated such that for A - Grade, I max < 90 mA (considering T max = 85 °C).
DD
A
8. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
9. Reference output duty cycle depends on XTALIN duty cycle.
10. Jitter varies significantly with configuration. Reference output jitter depends on XTALIN jitter and edge rate.
Document Number: 001-73555 Rev. *B
Page 12 of 19
CY22393
Switching Waveforms
Figure 7. All Outputs, Duty Cycle and Rise and Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 8. Output Tristate Timing
OE
t
5
t
5
ALL
TRISTATE
OUTPUTS
Figure 9. CLK Output Jitter
t6
CLK
OUTPUT
Figure 10. CPU Frequency Change
SELECT
CPU
OLD SELECT
NEW SELECT STABLE
t
7
F
new
F
old
Document Number: 001-73555 Rev. *B
Page 13 of 19
CY22393
Test Circuit
Figure 11. Test Circuit
Document Number: 001-73555 Rev. *B
Page 14 of 19
CY22393
Ordering Information
Ordering Code
Pb-free
Package Type
16-pin TSSOP
Product Flow
CY22393FXA
CY22393FXAT
CY22393FXE
CY22393FXET
Programmer
CY3672-USB
CY3698
Automotive A-Grade, –40 °C to 85 °C
Automotive A-Grade, –40 °C to 85 °C
Automotive E-Grade, –40 °C to 125 °C
Automotive E-Grade, –40 °C to 125 °C
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
Programmer
CY22393F Adapter for CY3672-USB
Possible Configurations
Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information
Ordering Code
Package Type
Product Flow
Pb-Free
CY22393ZXA-xxx
CY22393ZXA-xxxT
CY22393ZXE-xxx
CY22393ZXE-xxxT
16-pin TSSOP
Automotive A-Grade, –40 °C to 85 °C
Automotive A-Grade, –40 °C to 85 °C
Automotive E-Grade, –40 °C to 125 °C
Automotive E-Grade, –40 °C to 125 °C
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
Ordering Code Definitions
CY 22393
F
X -xxx
T
X
X
T = tape and reel, blank = tube
Configuration specific identifier (factory programmed)
Temperature Range: X = A or E
A = Automotive-A Grade = –40 °C to 85 °C,
E = Automotive-E Grade = –40 °C to 125 °C
Pb-free
Package: X = blank or Z
blank = 16-pin TSSOP (field programmable)
Z = 16-pin TSSOP (factory programmed)
X = F or blank
F = field programmable; blank = factory programmed
Part Identifier:
22393: 3.3 V CMOS clock generator
Company ID: CY = Cypress
Document Number: 001-73555 Rev. *B
Page 15 of 19
CY22393
Package Diagram
Figure 12. 16-pin TSSOP 4.40 mm Body Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *D
Document Number: 001-73555 Rev. *B
Page 16 of 19
CY22393
Acronyms
Document Conventions
Table 7. Acronyms Used in this Document
Units of Measure
Acronym
CMOS
ESR
Description
complementary metal oxide semiconductor
equivalent series resistance
field application engineer
Table 8. Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
kilohertz
FAE
kHz
MHz
μA
μF
FET
field effect transistor
megahertz
microampere
microfarad
microsecond
milliampere
millimeter
millisecond
milliwatt
JEDEC
LSB
joint electron devices engineering council
least significant bit
LVTTL
MPEG
OE
low voltage transistor-transistor logic
motion picture experts group
output enable
μs
mA
mm
ms
mW
ns
PLL
phase-locked loop
TSSOP
VCXO
thin shrink small outline package
voltage-controlled crystal oscillator
nanosecond
ohm
Ω
%
percent
pF
picofarad
ppm
ps
parts per million
picosecond
volt
V
Document Number: 001-73555 Rev. *B
Page 17 of 19
CY22393
Document History Page
Document Title: CY22393, Automotive Three-PLL Serial-Programmable Flash-Programmable Clock Generator
Document Number: 001-73555
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
3416122
3693908
4337034
PURU
PURU
CINM
11/14/2011 New data sheet
*A
*B
07/26/2012 Added CY22393 Automotive E-Grade Device
04/23/2014 Added A and E grade compatibility in Features
Added Device Programming section
Added footnotes 1, 5, 6, and 7.
Added junction temperature for A and E grade.
Added data retention at TJ = 150 °C and updated package power dissipation
for A and E grade.
Changed datasheet status to Final
Document Number: 001-73555 Rev. *B
Page 18 of 19
CY22393
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Lighting & Power Control
Community | Forums | Blogs | Video | Training
Technical Support
Memory
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2011-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-73555 Rev. *B
Revised April 23, 2014
Page 19 of 19
CyClocksRT is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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