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CY2273A-4 [CYPRESS]

Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs; Pentium㈢ / II ， 6X86 ， K6时钟合成器/驱动器，用于台式电脑采用英特尔82430TX ， 82440LX或ALI IV / IV + ， AGP和3个DIMM内存模块
CY2273A-4
型号： CY2273A-4
厂家： CYPRESS    CYPRESS
描述：

Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs
Pentium㈢ / II ， 6X86 ， K6时钟合成器/驱动器，用于台式电脑采用英特尔82430TX ， 82440LX或ALI IV / IV + ， AGP和3个DIMM内存模块

驱动器 电脑 PC 时钟
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CY2273A  
Pentium®/II, 6x86,K6ClockSynthesizer/DriverforDesktopPCs  
with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs  
The CY2273A possesses power-down, CPU stop, and PCI  
Features  
stop pins for power management control. These inputs are  
multiplexed with SDRAM clock outputs, and are selected when  
the MODE pin is driven low. Additionally, the signals are syn-  
chronized on-chip, and ensure glitch-free transitions on the  
outputs. When the CPU_STOP input is asserted, the CPU  
clock outputs are driven LOW. When the PCI_STOP input is  
asserted, the PCI clock outputs (except the free-running PCI  
clock) are driven LOW. When the PWR_DWN pin is asserted,  
the reference oscillator and PLLs are shut down, and all out-  
puts are driven LOW.  
• Mixed 2.5V and 3.3V operation  
• Complete clock solution for Pentium®, Pentium® II,  
Cyrix, and AMD processor-based motherboards  
— Four CPU clocks at 2.5V or 3.3V  
— Up to twelve 3.3V SDRAM clocks  
— Seven synchronous PCI clocks, one free-running  
— One 3.3V 48 MHz USB clock  
— One 2.5V IOAPIC clock (-3 option only)  
— Two AGP clocks at 60 or 66.6MHz (-2 option only)  
— One 3.3V Ref. clock at 14.318 MHz  
The CY2273A outputs are designed for low EMI emissions.  
Controlled rise and fall times, unique output driver circuits and  
factory-EPROM programmable output drive and slew-rate en-  
able optimal configurations for EMI control.  
2
• I C™ Serial Configuration Interface  
• Factory-EPROM programmable output drive and slew  
rate for EMI customization  
• Factory-EPROM programmable CPU clock frequencies  
for custom configurations  
• Power-down, CPU stop and PCI stop pins  
• Available in space-saving 48-pin SSOP package  
CY2273A Selector Guide  
Clocks Outputs  
-1  
-2  
-3  
-4  
CPU (60, 66.6, 75,  
83.3 MHz)  
4
4
--  
4
Functional Description  
The CY2273A is a clock synthesizer/driver for a Pentium, Pen-  
tium II, Cyrix, or AMD processor-based PC using Intel’s  
82430TX, 82440LX, ALI Aladdin IV or Aladdin IV+ chipsets.  
CPU (60, 66.6 MHz)  
SDRAM  
--  
--  
4
--  
9/12  
9/12  
9/12  
9/12  
[1]  
[1]  
[1]  
[1]  
PCI (30, 33.3MHz)  
USB/IR (48MHz)  
AGP (60 or 66MHz)  
IOAPIC (14.318MHz)  
Ref (14.318MHz)  
CPU-PCI delay  
7
5
7
7
The CY2273A-1 outputs four CPU clocks at 2.5V or 3.3V with  
up to 83.3MHz operation. There are seven PCI clocks, running  
at 30 and 33.3MHz. One of the PCI clocks is free-running.  
Additionally, the part outputs up to twelve 3.3V SDRAM clocks,  
one 3.3V USB clock at 48 MHz, and one 3.3V reference clock  
at 14.318 MHz. The CY2273A-2 is similar, except that  
PCICLK4 and PCICLK5 are now AGP clocks. The CY2273A-3  
is more suited to Pentium II systems, as it outputs one 2.5V  
IOAPIC clock. Finally, the CY2273A-4 is similar to the  
CY2273A-1 except that is supports 0-ns CPU-PCI delay.  
1
--  
--  
1
1
2
--  
1
1
--  
1
1
1
--  
--  
1
1–5.5 ns 1–5.5 ns 0 ns  
0 ns  
Note:  
1. One free-running PCI clock.  
CY2273A-3 only  
Logic Block Diagram  
IOAPIC  
VDDQ2  
REF0 (14.318 MHz)  
XTALIN  
14.318  
MHz  
OSC.  
STOP  
LOGIC  
CPU  
PLL  
XTALOUT  
CPUCLK [0-3]  
VDDCPU  
SEL0  
SEL1  
CY2273A-1,-2,-4 only  
SDRAM5/PWR_DWN  
SDRAM [0-4],[8-11]  
EPROM  
SDRAM6/CPU_STOP  
MODE  
Delay (-1,-2 option)  
SDRAM7/PCI_STOP  
SYS PLL  
/1 or /1.25  
/1 or /2  
CY2273A-2 only  
AGP [0,1]  
STOP  
LOGIC  
PCI [0-5], PCI [0-3]  
PCICLK_F  
SERIAL  
INTERFACE  
CONTROL  
LOGIC  
SCLK  
USBCLK (48 MHz)  
SDATA  
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
October 12, 1998  
CY2273A  
Pin Configurations  
CY2273A-2  
SSOP  
CY2273A-3  
SSOP  
Top View  
CY2273A-1,-4  
SSOP  
Top View  
Top View  
AV  
USBCLK  
REF0  
AV  
V
V
DDQ2  
V
DD  
1
2
3
4
48  
47  
46  
45  
44  
43  
42  
41  
1
2
3
4
48  
47  
46  
45  
44  
43  
42  
41  
DD  
1
2
3
4
48  
47  
46  
45  
44  
43  
42  
41  
DDQ3  
DDQ3  
REF0  
REF0  
USBCLK  
SEL1  
IOAPIC  
SEL0  
USBCLK  
SEL1  
V
V
V
SS  
SS  
SS  
XTALIN  
XTALIN  
XTALIN  
V
V
V
SS  
SS  
SS  
5
6
5
6
XTALOUT  
CPUCLK0  
CPUCLK1  
XTALOUT  
CPUCLK0  
CPUCLK1  
5
6
7
XTALOUT  
CPUCLK0  
CPUCLK1  
V
DDQ3  
V
V
DDQ3  
DDQ3  
PCICLK_F  
PCICLK0  
PCICLK_F  
PCICLK0  
PCICLK_F  
PCICLK0  
V
V
V
7
7
DDCPU  
DDCPU  
DDCPU  
CPUCLK2  
CPUCLK3  
CPUCLK2  
CPUCLK3  
8
8
CPUCLK2  
CPUCLK3  
8
V
V
V
SS  
SS  
SS  
9
9
9
40  
39  
38  
40  
39  
38  
40  
39  
38  
10  
11  
12  
10  
11  
12  
10  
11  
12  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK1  
PCICLK2  
PCICLK3  
PCICLK1  
PCICLK2  
PCICLK3  
V
V
V
SS  
SS  
SS  
SDRAM0  
SDRAM1  
SDRAM0  
SDRAM1  
SDRAM0  
SDRAM1  
37  
36  
35  
34  
37  
36  
35  
34  
37  
36  
35  
34  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
13  
14  
15  
16  
17  
18  
AGP0  
PCICLK4  
PCICLK4  
V
V
V
DDQ3  
DDQ3  
DDQ3  
V
V
DDQ3  
V
DDQ3  
DDQ3  
SDRAM2  
SDRAM3  
SDRAM2  
SDRAM3  
SDRAM2  
SDRAM3  
AGP1  
V
PCICLK5  
PCICLK5  
V
V
33  
32  
31  
30  
29  
28  
27  
26  
25  
33  
32  
31  
30  
29  
28  
27  
26  
25  
33  
32  
31  
SS  
V
SS  
V
SS  
V
SS  
SS  
SS  
SDRAM11  
SDRAM10  
SDRAM11  
SDRAM10  
SDRAM11  
SDRAM10  
SDRAM4  
SDRAM4  
SDRAM4  
SDRAM5/PWR_DWN  
SDRAM5/PWR_DWN  
SDRAM5/PWR_DWN  
V
DDQ3  
V
V
19  
20  
21  
22  
23  
24  
30  
29  
28  
27  
26  
25  
DDQ3  
DDQ3  
V
V
V
DDQ3  
DDQ3  
DDQ3  
SDRAM9  
SDRAM9  
SDRAM9  
SDRAM6/CPU_STOP  
SDRAM7/PCI_STOP  
SDRAM6/CPU_STOP  
SDRAM7/PCI_STOP  
SDRAM6/CPU_STOP  
SDRAM7/PCI_STOP  
SDRAM8  
SDRAM8  
SDRAM8  
V
V
V
SS  
SS  
SS  
V
SEL0  
V
SEL0  
V
SS  
SS  
SS  
SDATA  
SCLK  
AV  
SDATA  
SCLK  
MODE  
SCLK  
DD  
MODE  
MODE  
SDATA  
2
CY2273A  
Pin Summary  
Name  
Pins (-1, -4)  
Pins (-2)  
Pins (-3)  
Description  
V
6, 14, 19, 30, 36, 6, 14, 19, 30, 36, 6, 14, 19, 30, 36 3.3V Digital voltage supply  
DDQ3  
48  
N/A  
42  
1
48  
N/A  
42  
1
V
V
48  
42  
23  
IOAPIC Digital voltage supply, 2.5V  
DDQ2  
CPU Digital voltage supply, 2.5V or 3.3V  
Analog voltage supply, 3.3V  
DDCPU  
AV  
DD  
V
3, 9, 16, 22, 27, 3, 9, 16, 22, 27, 3, 9, 16, 22, 27, Ground  
SS  
33, 39, 45  
33, 39, 45  
33, 39, 45  
[2]  
XTALIN  
4
4
4
Reference crystal input  
[2]  
XTALOUT  
5
5
5
Reference crystal feedback  
SDRAM7/  
PCI_STOP  
28  
28  
28  
SDRAM clock output. Also, active low control input  
to stop PCI clocks, enabled when MODE is LOW.  
SDRAM6/  
CPU_STOP  
29  
29  
29  
SDRAM clock output. Also, active low control input  
to stop CPU clocks, enabled when MODE is LOW.  
SDRAM5/  
PWR_DWN  
31  
31  
31  
SDRAM clock output. Also, active low control input  
to power down device, enabled when MODE is LOW.  
SDRAM[0:4],  
[8:11]  
38, 37, 35, 34,  
32, 21, 20, 18, 17 32, 21, 20, 18, 17 32, 21, 20, 18, 17  
38, 37, 35, 34,  
38, 37, 35, 34,  
SDRAM clock outputs  
SEL0  
26  
26  
46  
CPU frequency select input, bit 0 (See table below.)  
CPU frequency select input, bit 0 (See table below.)  
CPU clock outputs  
SEL1  
46  
46  
N/A  
CPUCLK[0:3]  
44, 43, 41, 40  
44, 43, 41, 40  
44, 43, 41, 40  
PCICLK[0:5]or 8, 10, 11, 12, 13, 8, 10, 11, 12  
8, 10, 11, 12, 13, PCI clock outputs, at 30 or 33.33 MHz  
15  
PCICLK[0:3]  
PCICLK_F  
AGPCLK[0:1]  
IOAPIC  
15  
7
7
7
Free-running PCI clock output  
N/A  
N/A  
2
13, 15  
N/A  
2
N/A  
47  
2
AGP clock outputs at 60 or 66.66 MHz  
IOAPIC clock output  
REF0  
3.3V Reference clock output  
USBCLK  
SDATA  
47  
23  
24  
25  
47  
1
USB Clock output at 48 MHz  
23  
24  
25  
26  
Serial data input for serial configuration port  
Serial clock input for serial configuration port  
SCLK  
24  
MODE  
25  
Mode Select pin for enabling power management  
features  
Note:  
2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.  
Function Table (-1, -2 and -4)  
CPU/PCI  
Ratio  
CPUCLK[0:3]  
SDRAM[0:11]  
PCICLK[0:5]  
PCICLK_F  
AGP  
REF0  
SEL1 SEL0  
(-2 Only)  
IOAPIC  
USBCLK  
48 MHz  
0
0
1
1
0
1
0
1
2
2
60.0 MHz  
30.0 MHz  
60.0 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
66.67 MHz  
75.0 MHz  
83.33 MHz  
33.33 MHz  
30.0 MHz  
33.33 MHz  
66.66 MHz  
60.0 MHz  
66.66 MHz  
48 MHz  
48 MHz  
48 MHz  
2.5  
2.5  
Function Table (-3)  
SEL0 CPU/PCI Ratio  
CPUCLK[0:3]/SDRAM[0:11]  
60.0 MHz  
PCICLK[0:5],PCICLK_F  
30.0 MHz  
REF0/IOAPIC  
14.318 MHz  
USBCLK  
48 MHz  
48 MHz  
0
1
2
2
66.67 MHz  
33.33 MHz  
14.318 MHz  
3
CY2273A  
Actual Clock Frequency Values  
Target  
Frequency  
(MHz)  
Actual  
Frequency  
(MHz)  
Clock Output  
CPUCLK  
CPUCLK  
CPUCLK  
CPUCLK  
USBCLK  
PPM  
–195  
66.67  
60.0  
66.654  
60.0  
0
75.0  
75.0  
0
83.33  
48.0  
83.138  
48.008  
–1947  
167  
• Output impedance: 25Ω (typical) measured at 1.5V  
Power Management Logic[3] - Active when MODE pin is held ‘LOW’  
Other  
PCICLK_F Clocks  
CPU_STOP PCI_STOP PWR_DWN  
CPUCLK  
PCICLK  
Osc.  
Stopped Off  
PLLs  
Off  
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low  
Low  
Low  
Low  
Low  
Stopped  
Running  
Running  
Running  
Running Running Running  
Running Running Running  
Running Running Running  
Running Running Running  
33/30 MHz  
60/66/75/83 MHz Low  
60/66/75/83 MHz 30/33/30/33 MHz Running  
Serial Configuration Map  
Byte 0: Functional and Frequency Select Clock  
Register (1 = Enable, 0 = Disable)  
• The Serialbits will be read by the clock driver in the following  
order:  
Bit Pin #  
Bit 7 --  
Bit 6 --  
Bit 5 --  
Bit 4 --  
Bit 3 --  
Bit 2 --  
Description  
(Reserved) drive to ‘0’  
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
Bit 1 Bit 0  
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0  
• Reserved and unused bits should be programmed to “0”.  
2
• I C Address for the CY2273 is:  
Bit 1 --  
Bit 0  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
R/W  
1
1
0
0
1 - Three-State  
0 - N/A  
1
1
0
1
0
0
1
----  
1 - Testmode  
0 - Normal Operation  
Select Functions  
Outputs  
SDRAM  
-2 only  
AGP  
Functional Description  
CPU  
PCI, PCI_F  
Hi-Z  
TCLK/4  
Ref  
IOAPIC  
Hi-Z  
TCLK  
USBCLK  
Hi-Z  
TCLK/2  
Three-State  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
TCLK/2  
[5]  
[4]  
Test Mode  
TCLK/2  
TCLK/2  
TCLK  
Notes:  
3. AGP clocks are driven on PCICLK5 and PCICLK4 on -2 option. These clocks behave similar to the PCICLK_F output, in that they are free-running and stop  
only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.  
4. TCLK supplied on the XTALIN pin in Test Mode.  
5. Valid only for SEL1=0.  
4
CY2273A  
Byte 1: CPU Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Byte 2: PCI Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Bit  
Pin #  
Description  
Bit  
Bit 7  
Bit 6  
Bit 5  
Pin #  
Description  
(Reserved) drive to ‘0’  
Bit 7  
47 (-1,-2, and -4) USBCLK  
1 (-3 only)  
--  
7
PCICLK_F (Active/Inactive)  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
N/A  
N/A  
N/A  
40  
(Reserved) drive to ‘0’  
15  
PCICLK5 (Active/Inactive) (-1,-3 and -4)  
AGP1 (Active/Inactive) (-2 only)  
(Reserved) drive to ‘0’  
Not used - drive to ‘0’  
Bit 4  
13  
PCICLK4 (Active/Inactive) (-1,-3 and -4)  
AGP0 (Active/Inactive) (-2 only)  
CPUCLK3 (Active/Inactive)  
CPUCLK2 (Active/Inactive)  
CPUCLK1 (Active/Inactive)  
CPUCLK0 (Active/Inactive)  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
12  
11  
10  
8
PCICLK3 (Active/Inactive)  
PCICLK2 (Active/Inactive)  
PCICLK1 (Active/Inactive)  
PCICLK0 (Active/Inactive)  
41  
43  
44  
Byte 3: SDRAM Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Byte 4: SDRAM Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Bit Pin #  
Bit 7 28  
Bit 6 29  
Bit 5 31  
Bit 4 32  
Bit 3 34  
Bit 2 35  
Bit 1 37  
Bit 0 38  
Description  
SDRAM7 (Active/Inactive)  
SDRAM6 (Active/Inactive)  
SDRAM5 (Active/Inactive)  
SDRAM4 (Active/Inactive)  
SDRAM3 (Active/Inactive)  
SDRAM2 (Active/Inactive)  
SDRAM1 (Active/Inactive)  
SDRAM0 (Active/Inactive)  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin #  
N/A  
Description  
Not used - drive to ‘0’  
N/A  
N/A  
N/A  
17  
Not used - drive to ‘0’  
Not used - drive to ‘0’  
Not used - drive to ‘0’  
SDRAM11  
18  
SDRAM10  
20  
SDRAM9  
21  
SDRAM8  
Byte 5: Peripheral Active/Inactive Register  
(1 = Active, 0 = Inactive), Default = Active  
Byte 6: Reserved, for future use  
Bit  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Pin #  
N/A  
Description  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
IOAPIC (Active/Inactive) (-3 only)  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
(Reserved) drive to ‘0’  
REF0 (Active/Inactive)  
N/A  
N/A  
47  
N/A  
N/A  
N/A  
2
5
CY2273A  
Storage Temperature (Non-Condensing) ... –65°C to +150°C  
Max. Soldering Temperature (10 sec) ...................... +260°C  
Junction Temperature............................................... +150°C  
Package Power Dissipation .............................................. 1W  
Static Discharge Voltage ........................................... >2000V  
Maximum Ratings  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Supply Voltage..................................................–0.5 to +7.0V  
Input Voltage.............................................. –0.5V to V +0.5  
DD  
(per MIL-STD-883, Method 3015, like V pins tied together)  
DD  
Operating Conditions[6]  
Parameter  
AV , V  
Description  
Analog and Digital Supply Voltage  
Min.  
Max.  
Unit  
V
3.135  
3.465  
DD DDQ3  
V
CPU Supply Voltage  
2.375  
3.135  
2.9  
3.465  
V
DDCPU  
V
IOAPIC Supply Voltage  
2.375  
0
2.9  
70  
V
DDQ2  
T
Operating Temperature, Ambient  
°C  
pF  
A
C
Max. Capacitive Load on  
CPUCLK, USBCLK, IOAPIC  
PCICLK, AGP(-2 only), SDRAM  
REF0  
L
10  
30, 20  
20  
20  
30  
45  
f
Reference Frequency, Oscillator Nominal Value  
14.318  
14.318  
MHz  
(REF)  
Electrical Characteristics Over the Operating Range  
Parameter  
Description  
Test Conditions  
Min. Max. Unit  
V
High-level Input Voltage  
Low-level Input Voltage  
Low-level Input Voltage  
High-level Output Voltage  
Except Crystal Inputs  
Except Crystal Inputs  
2.0  
V
V
V
V
IH  
V
V
V
0.8  
0.7  
IL  
2
I C inputs only  
ILiic  
OH  
V
V
V
= V  
= V  
= 2.375V  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
= 16 mA CPUCLK 2.0  
= 18 mA IOAPIC  
= 27 mA CPUCLK  
= 29 mA IOAPIC  
= 16 mA CPUCLK 2.4  
= 36 mA SDRAM  
= 32 mA PCICLK  
= 26 mA USBCLK  
= 36 mA REF0  
DDCPU  
DDCPU  
DDQ2  
DDQ2  
OH  
OH  
OL  
OL  
OH  
OH  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
V
V
Low-level Output Voltage  
High-level Output Voltage  
= 2.375V  
0.4  
V
V
OL  
, AV , V = 3.135V  
DD DDCPU  
OH  
DDQ3  
DDQ3  
V
Low-level Output Voltage  
V
, AV , V  
= 3.135V  
= 27 mA CPUCLK  
= 29 mA SDRAM  
= 26 mA PCICLK  
= 21 mA USBCLK  
= 29 mA REF0  
0.4V  
V
OL  
DD DDCPU  
I
I
I
I
I
I
Input High Current  
Input Low Current  
V
V
= V  
DD  
–10 +10 µA  
10 µA  
IH  
IH  
IL  
= 0V  
IL  
Output Leakage Current  
Three-state  
–10 +10 µA  
= 3.465V, V = 0 or V , Loaded Outputs, CPU = 66.67 MHz 300 mA  
IN DD  
OZ  
DD  
DD  
DDS  
[7]  
Power Supply Current  
V
V
DD  
DD  
[7]  
Power Supply Current  
= 3.465V, V = 0 or V , Unloaded Outputs  
120 mA  
IN  
DD  
Power-down Current  
Current draw in power-down state  
500 µA  
Notes:  
6. Electrical parameters are guaranteed with these operating conditions.  
7. Power supply current will vary with number of outputs which are running.  
6
CY2273A  
Switching Characteristics for CY2273A-1, CY2273A-2[8]Over the Operating Range  
Parameter  
Output  
Description  
Test Conditions  
Min. Typ.  
Max. Unit  
[9, 10]  
t
All  
Output Duty Cycle  
t = t ÷ t  
1B  
45  
50  
55  
%
1
2
1
1A  
t
CPUCLK  
CPU Clock Rising and Between 0.4V and 2.0V, V  
= 2.5V 0.75  
= 3.3V  
4.0  
V/ns  
DDCPU  
DDCPU  
[10]  
Falling Edge Rate  
Between 0.4V and 2.4V, V  
t
SDRAM, PCI, SDRAM, PCI, REF0  
Between 0.4V and 2.4V  
0.85  
4.0  
4.0  
V/ns  
2
REF0, USB  
Clock Rising and Fall-  
ing Edge Rate  
[10]  
t
t
t
t
t
t
t
t
t
t
t
AGP (-2 only) AGP Rising and Falling Between 0.4V and 2.4V  
Edge Rate  
0.85  
V/ns  
ns  
2
CPUCLK  
CPUCLK  
CPUCLK  
CPU Clock Rise Time Between 0.4V and 2.0V, V  
Between 0.4V and 2.4V, V  
= 2.5V 0.4  
= 3.3V 0.5  
2.13  
2.67  
3
DDCPU  
DDCPU  
CPU Clock Fall Time  
Between 2.0V and 0.4V, V  
Between 2.4V and 0.4V, V  
= 2.5V 0.4  
= 3.3V 0.5  
2.13  
2.67  
ns  
4
DDCPU  
DDCPU  
CPU-CPU Clock Skew Measured at 1.25V, V  
= 2.5V  
DDCPU  
DDCPU  
100  
3.0  
250  
5.5  
650  
500  
500  
250  
500  
3
ps  
5
Measured at 1.5V, V  
= 3.3V  
CPUCLK,  
PCICLK  
CPU-PCI Clock Skew Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
1.0  
ns  
6
CPUCLK,  
SDRAM  
CPU-SDRAM Clock  
Skew  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
ps  
7
[10]  
PCICLK,  
PCICLK  
PCI-PCI Clock Skew  
Measured at 1.5V  
ps  
8
PCICLK,  
PCICLK-AGP Clock  
Measured at 1.5V  
ps  
9
AGP (-2 only) Skew (-2 only)  
CPUCLK,  
SDRAM  
Cycle-Cycle Clock  
Jitter  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
ps  
10  
10  
11  
[10]  
PCICLK,  
AGP (-2 only) Jitter  
Cycle-Cycle Clock  
Measured at 1.5V  
ps  
[10]  
CPUCLK,  
PCICLK,  
Power-up Time  
CPU, PCI, AGP, and SDRAM clock sta-  
bilization from power-up  
ms  
AGP (-2 only),  
SDRAM  
Notes:  
8. All parameters specified with loaded outputs.  
9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.  
10. Measured at CPU=66.6 MHz, SDRAM=66.6 MHz, PCI=33.3 MHz, AGP=66.6 MHz.  
7
CY2273A  
Switching Characteristics for CY2273A-3[8]Over the Operating Range  
Parameter  
Output  
All  
CPUCLK, CPU and IOAPIC Clock  
Description  
Test Conditions  
Min. Typ. Max.  
Unit  
%
[9]  
t
Output Duty Cycle  
t = t ÷ t  
1B  
45  
50  
55  
1
2
1
1A  
t
Between 0.4V and 2.0V, V  
Between 0.4V and 2.4V, V  
= 2.5V 0.75  
= 3.3V  
1.0  
4.0  
V/ns  
DDCPU  
DDCPU  
IOAPIC  
Rising and Falling Edge  
Rate  
t
t
REF0  
USBCLK  
REF0 and USBCLK Ris- Between 0.4V and 2.4V  
ing and Falling Edge Rate  
1.0  
4.0  
4.0  
V/ns  
V/ns  
2
SDRAM  
PCI  
SDRAM and PCI Clock  
Rising and Falling Edge  
Rate  
Between 0.4V and 2.4V  
0.85  
1.0  
2
t
t
t
t
t
t
t
CPUCLK  
CPUCLK  
CPUCLK  
CPU Clock Rise Time  
CPU Clock Fall Time  
CPU-CPU Clock Skew  
Between 0.4V and 2.0V, V  
Between 0.4V and 2.4V, V  
= 2.5V 0.4  
= 3.3V 0.5  
2.13  
2.67  
ns  
ns  
ps  
ps  
ps  
ps  
ps  
3
DDCPU  
DDCPU  
Between 2.0V and 0.4V, V  
Between 2.4V and 0.4V, V  
= 2.5V 0.4  
= 3.3V 0.5  
2.13  
2.67  
4
DDCPU  
DDCPU  
Measured at 1.25V, V  
= 2.5V  
= 3.3V  
100  
300  
900  
600  
500  
750  
5
DDCPU  
Measured at 1.5V, V  
DDCPU  
CPUCLK, CPU-PCI Clock Skew  
PCICLK  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
6
CPUCLK, CPU-SDRAM Clock  
SDRAM  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
7
Skew  
PCICLK,  
PCICLK  
PCI-PCI Clock Skew  
Measured at 1.5V  
8
CPUCLK, Cycle-Cycle Clock Jitter Measured at 1.25V for 2.5V clocks, and  
10  
SDRAM  
at 1.5V for 3.3V clocks  
t
t
PCICLK  
Cycle-Cycle Clock Jitter Measured at 1.5V  
500  
3
ps  
10  
CPUCLK, Power-up Time  
PCICLK,  
CPU, PCI, AGP, and SDRAM clock sta-  
bilization from power-up  
ms  
11  
SDRAM  
8
CY2273A  
Switching Characteristics for CY2273A-4[8]Over the Operating Range  
Parameter  
Output  
All  
Description  
Test Conditions  
Min. Typ. Max. Unit  
[9]  
t
Output Duty Cycle  
t = t ÷ t  
1B  
45  
50  
55  
%
1
2
1
1A  
t
t
CPUCLK  
CPU Clock Rising and  
Falling Edge Rate  
Between 0.4V and 2.0V, V  
= 2.5V 0.75 1.0  
4.0  
V/ns  
DDCPU  
SDRAM  
SDRAM, PCI, REF0,  
Between 0.4V and 2.4V  
0.85  
1.0  
4.0  
V/ns  
2
PCI, REF0, USB Clock Rising and  
USB  
Falling Edge Rate  
t
t
t
t
CPUCLK  
CPUCLK  
CPUCLK  
CPU Clock Rise Time  
CPU Clock Fall Time  
CPU-CPU Clock Skew  
CPU-PCI Clock Skew  
Between 0.4V and 2.0V, V  
Between 2.0V and 0.4V, V  
Measured at 1.25V  
= 2.5V 0.4  
= 2.5V 0.4  
2.13  
2.13  
250  
ns  
ns  
ps  
ps  
3
4
5
6
DDCPU  
DDCPU  
100  
CPUCLK,  
PCICLK  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
1200  
t
t
CPUCLK,  
SDRAM  
CPU-SDRAM Clock  
Skew  
Measured at 1.25V for 2.5V clocks, and  
at 1.5V for 3.3V clocks  
650  
500  
ps  
ps  
7
8
PCICLK,  
PCICLK  
PCI-PCI Clock Skew  
Measured at 1.5V  
t
t
t
t
CPUCLK,  
SDRAM  
PCICLK  
Cycle-Cycle Clock Jitter  
Cycle-Cycle Clock Jitter  
Cycle-Cycle Clock Jitter  
Power-up Time  
Measured at 1.25V, V  
Measured at 1.5V  
Measured at 1.5V  
= 2.5V  
DDCPU  
650  
650  
1200  
3
ps  
ps  
10  
10  
10  
11  
ps  
CPUCLK,  
PCICLK,  
SDRAM  
CPU, PCI, AGP, and SDRAM clock sta-  
bilization from power-up  
ms  
2
Timing Requirement for the I C Bus  
Parameter  
Description  
Min.  
Max.  
Unit  
kHz  
µs  
t
t
t
t
t
t
t
SCLK Clock Frequency  
0
4.7  
4
100  
12  
13  
14  
15  
16  
17  
18  
Time the bus must be free before a new transmission can start  
Hold time start condition. After this period the first clock pulse is generated.  
The Low period of the clock.  
µs  
4.7  
4
µs  
The High period of the clock.  
µs  
Set-up time for start condition. (Only relevant for a repeated start condition.)  
4.7  
µs  
Hold time DATA  
µs  
for CBUS compatible masters.  
for I C devices  
5
0
2
t
t
t
t
DATA input set-up time  
250  
ns  
µs  
ns  
µs  
19  
20  
21  
22  
Rise time of both SDATA and SCLK inputs  
Fall time of both SDATA and SCLK inputs  
Se-up time for stop condition  
1
300  
4.0  
Switching Waveforms  
Duty Cycle Timing  
t
1B  
t
1A  
9
CY2273A  
Switching Waveforms (continued)  
All Outputs Rise/Fall Time  
VDD  
0V  
OUTPUT  
t
2
t
3
t
2
t
4
CPU-CPU Clock Skew  
CPUCLK  
CPUCLK  
t
5
CPU-SDRAM Clock Skew  
CPUCLK  
SDRAM  
t
7
CPU-PCI Clock Skew  
CPUCLK  
PCICLK  
t6  
PCI-PCI Clock Skew  
PCICLK  
PCICLK  
t
8
AGP-PCI Clock Skew (-2 only)  
AGPCLK  
PCICLK  
t9  
10  
CY2273A  
Switching Waveforms (continued)  
[11, 12]  
CPU_STOP  
CPUCLK  
(Internal)  
PCICLK  
(Internal)  
PCICLK  
(Free-Running)  
CPU_STOP  
CPUCLK  
(External)  
[13, 14]  
PCI_STOP  
CPUCLK  
(Internal)  
PCICLK  
(Internal)  
PCICLK  
(Free-Running)  
PCI_STOP  
PCICLK  
(External)  
PWR_DOWN  
CPUCLK  
(Internal)  
PCICLK  
(Internal)  
PWR_DWN  
CPUCLK  
(External)  
PCICLK  
(External)  
VCO  
Crystal  
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.  
2
Timing Requirements for the I C Bus  
SDA  
t
t
t
21  
13  
t
14  
20  
SCL  
t
14  
t
t
17  
22  
t
t
t
19  
t
16  
15  
18  
Notes:  
11. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.  
12. CPU_STOP may be applied asynchronously. It is synchronized internally.  
13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.  
14. PCI_STOP may be applied asynchronously. It is synchronized internally.  
11  
CY2273A  
Application Information  
Clock traces must be terminated with either series or parallel termination, as they are normally done.  
Application Circuit  
Summary  
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C  
of  
LOAD  
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different  
is used. Footprints must be laid out for flexibility.  
C
LOAD  
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 µF.  
In some cases, smaller value capacitors may be required.  
• The value ofthe series terminating resistor satisfies the following equation, where R  
is the loaded characteristic impedance  
trace  
ofthe trace, R is theoutputimpedanceofthe clockgenerator(specified in the datasheet), and R  
is theseries terminating  
out  
series  
resistor.  
R
> R  
– R  
trace out  
series  
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor  
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.  
• A Ferrite Bead may be used to isolate the Board V from the clock generator V island. Ensure that the Ferrite Bead offers  
DD  
DD  
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout  
and Termination Techniques for Cypress Clock Generators” for more details.  
• If a Ferrite Bead is used, a 10 µF– 22 µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor  
prevents power supply droop during current surges.  
12  
CY2273A  
Test Circuit  
V
DDQ3  
V
DDQ3  
V
V
DDQ2  
1
23  
48  
48  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
3
6
3
6
45  
42  
45  
42  
V
DDCPU  
DDCPU  
9
9
39  
36  
39  
36  
14  
14  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
0.1 µF  
16  
19  
33  
30  
33  
30  
16  
19  
0.1 µF  
0.1 µF  
22  
22  
27  
27  
OUTPUTS  
OUTPUTS  
C
LOAD  
C
LOAD  
Note: All Capacitors must be placed as close to the pins as is possible  
Ordering Information  
Package  
Operating  
Range  
Ordering Code  
CY2273APVC–1  
CY2273APVC–2  
CY2273APVC–3  
CY2273APVC–4  
Name  
O48  
O48  
O48  
O48  
Package Type  
48-Pin SSOP  
Commercial  
Commercial  
Commercial  
Commercial  
48-Pin SSOP  
48-Pin SSOP  
48-Pin SSOP  
Document #: 38–00615–D  
13  
CY2273A  
Package Diagram  
48-Lead Shrunk Small Outline Package O48  
51-85061-B  
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  

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