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CY23S08SI-2 [CYPRESS]

3.3V Zero Delay Buffer; 3.3V零延迟缓冲器
CY23S08SI-2
型号： CY23S08SI-2
厂家： CYPRESS    CYPRESS
描述：

3.3V Zero Delay Buffer
3.3V零延迟缓冲器

时钟驱动器 逻辑集成电路 光电二极管
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CY23S08  
3.3V Zero Delay Buffer  
The CY23S08 has two banks of four outputs each, which can be  
controlled by the Select inputs as shown in Table 2 on page 3. If  
all output clocks are not required, Bank B can be three-stated.  
The select inputs also allow the input clock to be directly applied  
to the output for chip and system testing purposes.  
Features  
■ Zero input-output propagation delay, adjustable by capacitive  
load on FBK input  
■ Multiple configurations, see Table 3 on page 3  
The CY23S08 PLL enters a power down state when there are no  
rising edges on the REF input. In this mode, all outputs are  
three-stated and the PLL is turned off, resulting in less than  
50 μA of current draw. The PLL shuts down in two additional  
cases as shown in Table 2 on page 3.  
■ Multiple low-skew outputs  
❐ 45 ps typical output-output skew(–1)  
❐ Two banks of four outputs, three-stateable by two select in-  
puts  
Multiple CY23S08 devices can accept the same input clock and  
distribute it in a system. In this case, the skew between the  
outputs of two devices is guaranteed to be less than 700 ps.  
■ 10 MHz to 133 MHz operating range  
■ 65 ps typical cycle-cycle jitter (–1, –1H)  
■ Advanced 0.65μ CMOS technology  
■ Space saving 16-pin 150-mil SOIC/TSSOP packages  
■ 3.3V operation  
The CY23S08 is available in five different configurations, as  
shown in Table 3 on page 3. The CY23S08–1 is the base part,  
where the output frequencies equal the reference if there is no  
counter in the feedback path. The CY23S08–1H is the high-drive  
version of the –1, and rise and fall times on this device are much  
faster.  
■ Spread Aware™  
The CY23S08–2 enables the user to obtain 2X and 1X  
frequencies on each output bank. The exact configuration and  
output frequencies depends on which output drives the feedback  
pin. The CY23S08–2H is the high-drive version of the –2, and  
rise and fall times on this device are much faster.  
Functional Description  
The CY23S08 is a 3.3V zero delay buffer designed to distribute  
high speed clocks in PC, workstation, datacom, telecom, and  
other high performance applications.  
The CY23S08–3 enables the user to obtain 4X and 2X  
frequencies on the outputs.  
The part has an on-chip PLL which locks to an input clock  
presented on the REF pin. The PLL feedback must be driven into  
the FBK pin, and can be obtained from one of the outputs. The  
input-to-output propagation delay is guaranteed to be less than  
350 ps, and output-to-output skew is guaranteed to be less than  
250 ps.  
The CY23S08–4 enables the user to obtain 2X clocks on all  
outputs. Thus, the part is extremely versatile, and can be used  
in a variety of applications.  
Logic Block Diagram  
/2  
FBK  
PLL  
REF  
MUX  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
Extra Divider (–3, –4)  
S2  
Select Input  
Decoding  
S1  
/2  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
Extra Divider (–2, –2H, –3)  
Cypress Semiconductor Corporation  
Document #: 38-07265 Rev. *G  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 05, 2007  
[+] Feedback  
CY23S08  
Pinouts  
Figure 1. Pin Diagram - 16 Pin SOIC Package  
Top View  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
REF  
FBK  
CLKA1  
CLKA4  
CLKA3  
VDD  
CLKA2  
VDD  
SOIC  
GND  
GND  
CLKB4  
CLKB3  
S1  
CLKB1  
CLKB2  
S2  
Table 1. Pin Definition - 16 Pin SOIC Package  
Pin  
Signal  
Description  
1
REF[2]  
CLKA1[3]  
CLKA2[3]  
VDD  
Input reference frequency, 5V tolerant input  
Clock output, Bank A  
Clock output, Bank A  
3.3V supply  
2
3
4
5
GND  
Ground  
6
CLKB1[3]  
CLKB2[3]  
S2[4]  
Clock output, Bank B  
Clock output, Bank B  
Select input, bit 2  
Select input, bit 1  
Clock output, Bank B  
Clock output, Bank B  
Ground  
7
8
9
S1[4]  
10  
11  
12  
13  
14  
15  
16  
CLKB3[3]  
CLKB4[3]  
GND  
VDD  
3.3V supply  
CLKA3[3]  
CLKA4[3]  
FBK  
Clock output, Bank A  
Clock output, Bank A  
PLL feedback input  
Notes  
1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.  
2. Weak pull down.  
3. Weak pull down on all outputs.  
4. Weak pull ups on these inputs.  
Document #: 38-07265 Rev. *G  
Page 2 of 10  
[+] Feedback  
CY23S08  
Table 2. Select Input Decoding  
S2  
0
S1  
0
CLOCK A1–A4  
Three-State  
Driven  
CLOCK B1–B4  
Three-State  
Three-State  
Driven  
Output Source  
PLL  
PLL Shutdown  
Y
N
Y
N
0
1
PLL  
1
0
Driven  
Reference  
PLL  
1
1
Driven  
Driven  
Table 3. Available CY23S08 Configurations  
Device  
CY23S08–1  
CY23S08–1H  
CY23S08–2  
CY23S08–2H  
CY23S08–2  
CY23S08–2H  
CY23S08–3  
CY23S08–3  
CY23S08–4  
Feedback From  
Bank A or Bank B  
Bank A or Bank B  
Bank A  
Bank A Frequency  
Bank B Frequency  
Reference  
Reference  
Reference  
Reference  
Reference  
Reference/2  
Reference/2  
Reference  
Bank A  
Reference  
Bank B  
2 X Reference  
2 X Reference  
2 X Reference  
4 X Reference  
2 X Reference  
Bank B  
Reference  
Bank A  
Reference or Reference[1]  
2 X Reference  
2 X Reference  
Bank B  
Bank A or Bank B  
Spread Aware  
Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been  
one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the  
Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant  
amount of tracking skew which may cause problems in systems requiring synchronization.  
For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with  
Spread Spectrum Frequency Timing Generator (SSFTG) ICs.  
Document #: 38-07265 Rev. *G  
Page 3 of 10  
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CY23S08  
Maximum Ratings  
Supply Voltage to Ground Potential................–0.5V to +7.0V  
DC Input Voltage (Except Ref) ..............–0.5V to VDD + 0.5V  
DC Input Voltage REF ...........................................–0.5 to 7V  
Storage Temperature ................................. –65°C to +150°C  
Max. Soldering Temperature (10 sec.) ....................... 260°C  
Junction Temperature................................................. 150°C  
Static Discharge Voltage  
(per MIL-STD-883, Method 3015) .............................>2000V  
Operating Conditions for CY23S08SC-XX Commercial Temperature Devices  
Parameter[5]  
Description  
Min  
3.0  
0
Max  
3.6  
70  
30  
15  
7
Unit  
V
VDD  
Supply Voltage  
TA  
CL  
Operating Temperature (Ambient Temperature)  
Load Capacitance, below 100 MHz  
Load Capacitance, from 100 MHz to 133 MHz  
Input Capacitance[6]  
°C  
pF  
pF  
pF  
—
—
CIN  
—
Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices  
Parameter  
Description  
Input LOW Voltage  
Input HIGH Voltage  
Input LOW Current  
Input HIGH Current  
Output LOW Voltage[7]  
Test Conditions  
Min  
—
Max  
0.8  
Unit  
V
VIL  
VIH  
IIL  
2.0  
—
—
V
VIN = 0V  
50.0  
100.0  
0.4  
μA  
μA  
V
IIH  
VIN = VDD  
—
VOL  
IOL = 8 mA (–1, –2, –3, –4)  
IOL = 12 mA (-1H, -2H)  
—
VOH  
Output HIGH Voltage[7]  
IOH = –8 mA (–1, –2, –3, –4)  
IOH = –12 mA (–1H, –2H)  
2.4  
—
V
IDD (PD mode)  
IDD  
Power down Supply Current REF = 0 MHz  
—
—
—
12.0  
45.0  
μA  
mA  
mA  
Supply Current Unloaded outputs, 100-MHz REF,  
Select inputs at VDD or GND  
70.0  
(–1H, –2H)  
Unloaded outputs, 66-MHz REF  
(–1,–2,–3,–4)  
—
—
32.0  
18.0  
mA  
mA  
Unloaded outputs, 33-MHz REF  
(–1,–2,–3,–4)  
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices  
Parameter[8]  
Name  
Output Frequency  
Output Frequency  
Output Frequency  
Output Frequency  
Output Frequency  
Test Conditions  
30-pF load, –1, –1H, –2, –3 devices  
30-pF load, –4 devices  
Min  
10  
Typ.  
—
Max  
100  
Unit  
t1  
MHz  
MHz  
MHz  
MHz  
MHz  
%
t1  
t1  
t1  
t1  
15  
—
100  
20-pF load, –1H device  
10  
—
133.3  
140.0  
140.0  
60.0  
15-pF load, –1, –2, –3, devices  
15-pF load, –4 devices  
10  
—
15  
—
Duty Cycle[7] = t2 ÷ t1  
(–1,–2,–3,–4,–1H, -2H)  
Measured at VDD/2, FOUT = 66.66 MHz  
30-pF load  
40.0  
50.0  
Duty Cycle[7] = t2 ÷ t1  
(–1,–2,–3,–4,–1H, -2H)  
Measured at VDD/2, FOUT <66.66 MHz  
15-pF load  
45.0  
50.0  
55.0  
%
Notes  
5. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.  
6. Applies to both Ref Clock and FBK.  
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.  
8. All parameters are specified with loaded outputs.  
Document #: 38-07265 Rev. *G  
Page 4 of 10  
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CY23S08  
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)  
Parameter[8]  
Name  
Test Conditions  
Min  
Typ.  
Max  
Unit  
t3  
Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF  
load  
—
—
2.20  
ns  
t3  
t3  
t4  
t4  
t4  
t5  
Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF  
load  
—
—
—
—
—
—
—
1.50  
1.50  
2.20  
1.50  
1.25  
200  
ns  
ns  
ns  
ns  
ns  
ps  
ps  
Rise Time[7] (–1H, -2H)  
Measured between 0.8V and 2.0V, 30-pF  
load  
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF  
load  
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF  
load  
—
—
Fall Time[7] (–1H, 2H)  
Measured between 0.8V and 2.0V, 30-pF  
load  
—
Output to Output Skew on All outputs equally loaded  
same Bank (–1)[7]  
45  
105  
Output to Output Skew on All outputs equally loaded  
—
150  
same Bank  
(–1H,–2,–2H,–3)[7]  
Output to Output Skew on All outputs equally loaded  
same Bank (–4)[7]  
—
—
70  
—
—
—
—
—
—
—
65  
85  
—
—
—
100  
200  
300  
215  
250  
+275  
700  
ps  
ps  
Output to Output Skew  
(–1H, -2H)  
All outputs equally loaded  
All outputs equally loaded  
All outputs equally loaded  
All outputs equally loaded  
Output Bank A to Output  
Bank B Skew (–1,–2, –3)  
—
ps  
Output Bank A to Output  
Bank B Skew (–4)  
—
ps  
Output Bank A to Output  
Bank B Skew (–1H)  
—
ps  
t6  
t7  
t8  
tJ  
Delay, REF Rising Edge to Measured at VDD/2  
FBK Rising Edge[7]  
Device to Device Skew[7] Measured at VDD/2 on the FBK pins of  
devices  
–250  
—
ps  
ps  
Output Slew Rate[7]  
Measured between 0.8V and 2.0V on –1H,  
–2H device using Test Circuit #2  
1
V/ns  
ps  
Cycle to Cycle Jitter[7]  
(–1, –1H)  
Measured at 66.67 MHz, loaded outputs, 15,  
30-pF loads: 133 MHz, 15-pF load  
—
125  
300  
400  
200  
1.0  
Cycle to Cycle Jitter[7]  
(–2)  
Measured at 66.67 MHz, loaded outputs,  
15-pF load  
—
ps  
Cycle to Cycle Jitter[7]  
(–2)  
Measured at 66.67 MHz, loaded outputs,  
30-pF load  
—
ps  
tJ  
Cycle to Cycle Jitter[7]  
(–3,–4)  
Measured at 66.67 MHz, loaded outputs  
15, 30-pF loads  
—
ps  
tLOCK  
PLL Lock Time[7]  
Stable power supply, valid clocks presented  
on REF and FBK pins  
—
ms  
Document #: 38-07265 Rev. *G  
Page 5 of 10  
[+] Feedback  
CY23S08  
Switching Waveforms  
Figure 2. Duty Cycle Timing  
t
1
t
2
1.4V  
1.4V  
1.4V  
Figure 3. All Outputs Rise/Fall Time  
3.3V  
0V  
2.0V  
0.8V  
2.0V  
0.8V  
OUTPUT  
t
3
t
4
Figure 4. Output-Output Skew  
1.4V  
OUTPUT  
OUTPUT  
1.4V  
t
5
Figure 5. Input-Output Propagation Delay  
VDD/2  
INPUT  
FBK  
VDD/2  
t6  
Figure 6. Device-Device Skew  
VDD/2  
FBK, Device 1  
V
DD/2  
FBK, Device 2  
t7  
Document #: 38-07265 Rev. *G  
Page 6 of 10  
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CY23S08  
Test Circuits  
Figure 7. Test Circuit #1  
VDD  
CLK OUT  
CLOAD  
0.1 μF  
0.1 μF  
OUTPUTS  
VDD  
GND  
GND  
Test Circuit for all parameters except t8  
Figure 8. Test Circuit #2  
Test Circuit # 2  
VDD  
1 KΩ  
CLK  
0.1 μF  
0.1 μF  
out  
OUTPUTS  
1 KΩ  
10 pF  
VDD  
GND  
GND  
Test Circuit for t8, Output slew rate on –1H device  
Document #: 38-07265 Rev. *G  
Page 7 of 10  
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CY23S08  
Ordering Information  
Ordering Code  
CY23S08SC–1  
CY23S08SC–1T  
CY23S08SI–1  
Package Type  
16-pin 150-mil SOIC  
Operating Range  
Commercial  
Status  
Obsolete  
Obsolete  
Obsolete  
Obsolete  
Obsolete  
Obsolete  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Commercial  
Industrial  
CY23S08SI–1T  
CY23S08SC–1H  
CY23S08SC–1HT  
CY23S08SI–1H  
CY23S08SI–1HT  
CY23S08ZC–1H  
CY23S08ZC–1HT  
CY23S08SC–2  
CY23S08SC–2T  
CY23S08SI–2  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Industrial  
Commercial  
Commercial  
Industrial  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Not for new design  
Not for new design  
Not for new design  
Obsolete  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil TSSOP  
Industrial  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
16-pin 150-mil TSSOP–Tape and Reel  
16-pin 150-mil SOIC  
Not for new design  
Not for new design  
Not for new design  
Not for new design  
Obsolete  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
CY23S08SI–2T  
CY23S08SC–2H  
CY23S08SC–2HT  
CY23S08SC–3  
CY23S08SC–3T  
CY23S08SC–4  
CY23S08SC–4T  
CY23S08SI–4  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Industrial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Active  
Obsolete  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Obsolete  
Obsolete  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Obsolete  
Obsolete  
CY23S08SI–4T  
Pb-free  
16-pin 150-mil SOIC–Tape and Reel  
Industrial  
Obsolete  
CY23S08SXC–1  
CY23S08SXC–1T  
CY23S08SXI–1H  
CY23S08SXI–1HT  
CY23S08ZXC-1H  
CY23S08SXC–2  
CY23S08SXC–2T  
CY23S08SXC–2H  
CY23S08SXC–2HT  
CY23S08SXI–2  
CY23S08SXI–2T  
CY23S08SXC-4  
CY23S08SXC-4T  
CY23S08SXI-4  
CY23S08SXI-4T  
16-pin 150-mil SOIC  
Commercial  
Commercial  
Industrial  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil TSSOP  
Industrial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Industrial  
16-pin 150-mil SOIC  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
Industrial  
Commercial  
Commercial  
Industrial  
16-pin 150-mil SOIC–Tape and Reel  
16-pin 150-mil SOIC  
16-pin 150-mil SOIC–Tape and Reel  
Industrial  
Document #: 38-07265 Rev. *G  
Page 8 of 10  
[+] Feedback  
CY23S08  
Package Drawings and Dimensions  
Figure 9. 16-Lead (150-Mil) SOIC S16  
PIN 1 ID  
8
1
DIMENSIONS IN INCHES[MM] MIN.  
MAX.  
REFERENCE JEDEC MS-012  
PACKAGE WEIGHT 0.15gms  
0.150[3.810]  
0.157[3.987]  
0.230[5.842]  
0.244[6.197]  
PART #  
S16.15 STANDARD PKG.  
SZ16.15 LEAD FREE PKG.  
9
16  
0.010[0.254]  
0.016[0.406]  
X 45°  
0.386[9.804]  
0.393[9.982]  
SEATING PLANE  
0.061[1.549]  
0.068[1.727]  
0.004[0.102]  
0.050[1.270]  
BSC  
0.0075[0.190]  
0.0098[0.249]  
0.016[0.406]  
0.035[0.889]  
0°~8°  
0.0138[0.350]  
0.0192[0.487]  
0.004[0.102]  
0.0098[0.249]  
51-85068-*B  
Figure 10. 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16  
PIN 1 ID  
1
6.25[0.246]  
6.50[0.256]  
4.30[0.169]  
4.50[0.177]  
16  
0.65[0.025]  
BSC.  
0.25[0.010]  
BSC  
0.19[0.007]  
0.30[0.012]  
1.10[0.043] MAX.  
GAUGE  
PLANE  
0°-8°  
0.076[0.003]  
0.50[0.020]  
0.70[0.027]  
0.05[0.002]  
0.15[0.006]  
0.85[0.033]  
0.95[0.037]  
0.09[[0.003]  
0.20[0.008]  
SEATING  
PLANE  
4.90[0.193]  
5.10[0.200]  
51-85091-*A  
Document #: 38-07265 Rev. *G  
Page 9 of 10  
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CY23S08  
Document History Page  
Document Title: CY23S08 3.3V Zero Delay Buffer  
Document Number: 38-07265  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
**  
110530  
122863  
130951  
12/02/01  
12/20/02  
11/26/03  
SZV  
Change from Spec number: 38-01107 to 38-07265  
*A  
*B  
RBI  
Added power up requirements to operating conditions information.  
RGL  
Corrected the Switching Characteristics parameters to reflect the W152 device  
and new characterization.  
*C  
*D  
*E  
204201  
231100  
378878  
See ECN  
See ECN  
See ECN  
RGL  
RGL  
RGL  
Corrected the Block Diagram  
Fixed Typo in table 2.  
Added Industrial Temp and Pb Free Devices  
Added typical char data  
Removed “Preliminary”  
*F  
391564  
See ECN  
RGL  
Changed output-to-output skew typical value from 90ps to 45ps  
Added cycle-to-cycle jitter (-2) typical value of 85ps  
*G  
1442823  
See ECN WWZ/AESA Updated ordering info with status update. Added new Pb-free part numbers.  
© Cypress Semiconductor Corporation, 2001-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
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Revised September 05, 2007  
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