CY2410-5 [CYPRESS]
MPEG Clock Generator with VCXO Integrated phase-locked loop (PLL); MPEG时钟发生器， VCXO集成锁相环（ PLL ）
| 型号： | CY2410-5 |
| 厂家： | 
CYPRESS |
| 描述： | MPEG Clock Generator with VCXO Integrated phase-locked loop (PLL) |
| 文件： | 总13页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2410
MPEG Clock Generator with VCXO
MPEG Clock Generator with VCXO
Features
Benefits
■ Integrated phase-locked loop (PLL)
■ Low-jitter, high-accuracy outputs
■ VCXO with analog adjust
■ Highest-performance PLL tailored for multimedia applications
■ Meets critical timing requirements in complex system designs
■ Large ±150-ppm range, better linearity
■ Application compatibility for a wide variety of designs
■ Enables design compatibility
■ 3.3 V operation
■ Compatible with MK3727 (–1, –5)
■ Advanced Features
■ Matches nonlinear MK3727A VCXO control curve (-5)
■ Digital VCXO control
■ Electromagnetic interference (EMI) reduction for standards
compliance
■ Second source for existing designs
Output
Frequencies
VCXO Control
Curve
Part Number Outputs
Input Frequency Range
Other Features
CY2410-1
CY2410-5
1
1
13.5-MHz pullable crystal input per 1 copy of 27 MHz linear
Cypress specification
Compatible with MK3727
13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear
Cypress specification
Matches MK3727A nonlinear
VCXO Control Curve
CY2410-1, -5 Logic Block Diagram
13.5 XIN
OUTPUT
OSC
Q
27 MHz
DIVIDERS
XOUT
VCO
P
VCXO
PLL
VSS
VDD
Cypress Semiconductor Corporation
Document #: 38-07317 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 16, 2011
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CY2410
CY2410-3 Logic Block Diagram
13.5 XIN
OSC
OUTPUT
Q
27 MHz
DIVIDERS
XOUT
VCO
P
PLL
Digital VCXO
SCLK
SDAT
Serial
VSS
VDD
Programming
Interface
Document #: 38-07317 Rev. *G
Page 2 of 13
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CY2410
Contents
Pin Configuration .............................................................4
Pin Definitions for CY2410-1, CY2410-5 .........................4
Pullable Crystal Specifications .......................................5
Absolute Maximum Conditions .......................................7
Recommended Operating Conditions ............................7
DC Electrical Specifications ............................................7
AC Electrical Specifications (VDD = 3.3 V) .....................7
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................13
Worldwide Sales and Design Support .......................13
Products ....................................................................13
PSoC Solutions .........................................................13
Document #: 38-07317 Rev. *G
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CY2410
Pin Configuration
Figure 1. CY2410-1, CY2410-5 8-pin SOIC
XOUT
1
2
3
4
8
7
6
5
XIN
NC or VSS
NC or VDD
27 MHz
VDD
VCXO
VSS
Pin Definitions for CY2410-1, CY2410-5
Name
Pin Number
Description
XIN
1
2
3
4
5
6
7
8
Reference crystal input
Voltage supply
VDD
VCXO
VSS
Input analog control for VCXO
Ground
27 MHz
NC/VDD
NC/VSS
27-MHz clock output
No Connect or voltage supply
No Connect or ground
Reference crystal output
[1]
XOUT
Note
1. Float X
if X is externally driven.
IN
OUT
Document #: 38-07317 Rev. *G
Page 4 of 13
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CY2410
Pullable Crystal Specifications
Parameter [2]
Description
Condition
Min
Typ
Max
Unit
FNOM
Nominal crystal frequency
Parallel resonance, fundamental
mode, AT cut
–
13.5
–
MHz
CLNOM
R1
Nominal load capacitance
–
–
14
–
–
pF
Equivalent series resistance
(ESR)
Fundamental mode
25
R3/R1
Ratio of third overtone mode ESR Ratio used because typical R1 values
3
–
–
to fundamental mode ESR
are much less than the maximum
spec.
DL
Crystal drive level
No external series resistor assumed
–
0.5
–
2.0
–
mW
ppm
F3SEPHI
Third overtone separation from High side
3 × FNOM
300
F3SEPLO
Third overtone separation from Low side
3 × FNOM
–
–
–150
ppm
pF
C0
Crystal shunt capacitance
–
–
–
7
C0/C1
Ratio of shunt to motional
capacitance
180
250
C1
Crystal motional capacitance
14.4
18
21.6
pF
Note
2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M, Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL, PDI HA13500XFSA14XC.
Document #: 38-07317 Rev. *G
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CY2410
Figure 2. Data Valid and Data Transition Periods
Transition
to next bit
Data Valid
SDAT
tDH
tSU
SCLK
CLKHIGH
VIH
CLKLOW
VIL
Figure 3. Start and Stop Frame
SDAT
SCLK
Transition
to next bit
START
STOP
Figure 4. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
50%
Figure 5. Rise and Fall Time Definitions: ER = 0.6 × VDD / t3, EF = 0.6 × VDD / t4
t4
t3
80%
20%
CLK
Document #: 38-07317 Rev. *G
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CY2410
Absolute Maximum Conditions
Parameter
Description
Min
–0.5
–65
–
Max
Unit
V
VDD
TS
Supply Voltage
7.0
125
125
Storage Temperature [3]
Junction Temperature
Digital Inputs
°C
°C
V
TJ
VSS – 0.3 VDD + 0.3
VSS – 0.3 VDD + 0.3
Digital Outputs referred to VDD
Electrostatic Discharge
V
2000
–
V
Recommended Operating Conditions
Parameter
VDD
Description
Min
3.135
0
Typ
3.3
–
Max
3.465
70
Unit
V
Operating Voltage
TA
Ambient Temperature
Max. Load Capacitance
Reference Frequency
°C
CLOAD
fREF
tPU
–
–
15
pF
–
13.5
–
–
MHz
ms
Power up time for VDD to reach minimum specified voltage (power ramp
must be monotonic)
0.05
500
DC Electrical Specifications
Parameter
IOH
Name
Output HIGH Current: -1, -5
Output LOW Current: -1, -5
Input Capacitance
Description
Min
12
12
–
Typ
24
24
–
Max
–
Unit
mA
mA
pF
VOH = VDD – 0.5, VDD = 3.3 V
VOL = 0.5, VDD = 3.3 V
IOL
–
CIN
7
IIZ
Input Leakage Current
VCXO pullability range: -1, -5
VCXO input range
–
5
–
A
fXO
VVCXO
IVDD
+150
0
–
–
ppm
V
–
VDD
35
Supply Current
–
30
mA
AC Electrical Specifications (V = 3.3 V)
DD
Parameter[4]
Name
Output Duty Cycle
Description
Min
Typ
Max
Unit
DC
Duty Cycle is defined in Figure 4
on page 6, 50% of VDD
45
50
55
%
EROR
Rising Edge Rate: -1, -5
Output Clock Edge Rate,
Measured from 20% to 80% of
0.8
0.8
1.4
1.4
–
–
V/ns
V/ns
VDD, CLOAD = 15 pF.
See Figure 5 on page 6.
EROF
Falling Edge Rate: -1, -5
Output Clock Edge Rate,
Measured from 80% to 20% of
VDD, CLOAD = 15 pF.
See Figure 5 on page 6.
t9
Clock Jitter: -1, -5
PLL Lock Time
Peak-to-peak period jitter
–
–
140
–
–
3
ps
t10
ms
Notes
3. Rated for ten years.
4. Not 100% tested.
Document #: 38-07317 Rev. *G
Page 7 of 13
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CY2410
Figure 6. Test and Measurement Setup
VDD
CLK out
CLOAD
0.1 F
OUTPUTS
GND
Document #: 38-07317 Rev. *G
Page 8 of 13
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CY2410
Ordering Information
Operating
Range
Operating
Voltage
Ordering Code
Package Type
Features
Pb-free
CY2410KSXC–5
8-pin SOIC
Commercial
3.3 V
3.3 V
Matches nonlinear MK3727A VCXO control curve
Matches nonlinear MK3727A VCXO control curve
CY2410KSXC–5T 8-pin SOIC - Tape and Reel Commercial
Ordering Code Definitions
CY2410K
S
X
C
-
5
T
Tape and Reel
Configuration Type
Temperature Range:
C = Commercial
Pb-free
Package Type:
S = 8-pin SOIC
Base Part Number
Document #: 38-07317 Rev. *G
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CY2410
Package Diagram
Figure 7. 8-pin SOIC (150 Mils), 51-85066
51-85066 *E
Document #: 38-07317 Rev. *G
Page 10 of 13
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CY2410
Acronyms
Document Conventions
Units of Measure
Acronym
Description
PLL
phase-locked loop
Symbol
C
Unit of Measure
EMI
electromagnetic interference
electrostatic discharge
degree Celsius
Mega Hertz
micro Farad
milli Amperes
milli seconds
milli Watts
ohms
ESD
ESR
PLL
MHz
F
mA
ms
mW
equivalent series resistance
phase locked loop
SOIC
VCXO
small outline integrated circuit
voltage controlled crystal oscillator
ppm
%
parts per million
percent
pF
pico Farad
pico seconds
Volts
ps
V
Document #: 38-07317 Rev. *G
Page 11 of 13
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CY2410
Document History Page
Document Title: CY2410, MPEG Clock Generator with VCXO
Document Number: 38-07317
Submission
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
**
111553
114937
121418
126905
02/12/02
09/24/02
12/06/02
06/17/03
CKN
CKN
CKN
RGL
New Data Sheet
*A
*B
*C
Added -6 to data sheet, Advance Information to Final
Updated the Pullable Crystal Specifications table on page 2
Added -7 part to data sheet
Added new parameter on the Pullable Crystal table
Power up requirements added to the operating conditions
*D
*E
131100
01/20/03
See ECN
RGL
Added VCXO -7 pullability range in the DC Specs with min. value of ±115 ppm
2440886
AESA
Updated template.
Added Note “Not recommended for new designs.”
Added part number CY2410SXC-1, CY2410SXC-1T, CY2410SXC-5,
CY2410SXC-5T, CY2410KSXC-5, and CY2410KSXC-5T in ordering
information table. Removed all part numbers for non-Pb-free packages (part
numbers beginning CY2410SC).
Removed details specific to the -3, -4, -6 and -7 versions.
*F
2897373
3317009
03/22/10
CXQ
Updated ordering information table. Removed part numbers CY2410SXC-1,
CY2410SXC-1T, CY2410SXC-5T, and CY2410SXC-5
Updated package diagram.
Updated copyright section.
*G
07/16/2011
BASH
Added Ordering Code Definitions.
Updated Package Diagram.
Updated Acronyms and Units of Measure.
Updated in new template.
Document #: 38-07317 Rev. *G
Page 12 of 13
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CY2410
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07317 Rev. *G
Revised July 16, 2011
Page 13 of 13
All products and company names mentioned in this document may be the trademarks of their respective holders.
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