CY24210-4 [CYPRESS]

Clock Generator, PDSO8,;
CY24210-4
型号: CY24210-4
厂家: CYPRESS    CYPRESS
描述:

Clock Generator, PDSO8,

光电二极管
文件: 总5页 (文件大小:85K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CY24210  
100-MHz Clock Generator with Spread Spectrum  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• Spread Spectrum  
High-performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Spread Spectrum outputs for EMI reduction  
Enables application compatibility  
• 3.3V operation  
Part Number Outputs  
CY24210  
Input Frequency Range  
Output Frequencies  
3
14.31818 MHz  
Two copies of 100 MHz, 14.31818 MHz  
Logic Block Diagram  
REF  
XIN  
OSC  
Q
Φ
CLK2  
CLK1  
OUTPUT  
DIVIDERS  
SPREAD  
SPECTRUM  
XOUT  
VCO  
P
PLL  
SSON  
VSS  
VDD  
Spread Spectrum Profiles  
Pin Configurations  
Part Numbers  
CY24210SC-3  
CY24210SC-4  
CY24210SC-5  
CY24210SC-6  
CY24210SC-7  
Center Spread Percentage  
+ 1.875%  
CY24210  
8-pin SOIC  
+ 1.375%  
+ 2.375%  
XOUT  
1
2
3
4
8
7
6
5
XIN  
CLK1  
CLK2  
VDD  
SSON  
VSS  
+ 2.875%  
+ 3.375%  
REF  
Pin Description  
Pin Name  
XIN  
Pin Number  
Description  
1
Reference Crystal Input  
Voltage Supply  
VDD  
2
3
4
5
6
7
8
SSON  
VSS  
Spread Spectrum Control for CLK1, CLK2, 0 = SS off, 1 = SS on, Internal Pull-up Resistor  
Ground  
REF  
Buffered Reference Clock Output  
CLK2  
CLK1  
100-MHz Clock Output with Spread Spectrum  
100-MHz Clock Output with Spread Spectrum  
Reference Crystal Output  
[1]  
XOUT  
Note:  
1. Float XOUT if XIN is externally driven.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-07361 Rev. **  
Revised March 27, 2002  
CY24210  
Absolute Maximum Conditions  
Parameter  
Description  
Min.  
0.5  
65  
Max.  
7.0  
Unit  
V
V
Supply Voltage  
TS  
TJ  
Storage Temperature[2]  
Junction Temperature  
Digital Inputs  
125  
°C  
°C  
V
125  
VSS 0.3  
VSS 0.3  
2
VDD + 0.3  
VDD + 0.3  
Digital Outputs referred to VDD  
Electrostatic Discharge  
V
kV  
Recommended Operating Conditions  
Parameter  
VDD  
Description  
Min.  
3.14  
0
Typ.  
Max.  
Unit  
V
Operating Voltage  
3.3  
3.47  
70  
TA  
Ambient Temperature  
Max. Load Capacitance  
Reference Frequency  
°C  
CLOAD  
fREF  
15  
pF  
14.31818  
MHz  
DC Electrical Characteristics  
Parameter  
IOH  
Description  
Conditions  
Min.  
Typ.  
Max.  
Unit  
mA  
mA  
µA  
Output High Current  
Output Low Current  
Input High Current  
Input Low Current  
Input High Voltage  
Input Low Voltage  
Input Capacitance  
Supply Current  
VOH = VDD 0.5, VDD = 3.3 V  
VOL = 0.5, VDD = 3.3 V  
VIH = VDD  
12  
12  
24  
24  
5
IOL  
IIH  
IIL  
VIL = 0V  
50  
µA  
VIH  
CMOS levels, 70% of VDD  
CMOS levels, 30% of VDD  
0.7  
80  
VDD  
VDD  
pF  
VIL  
0.3  
7
CIN  
IDD  
Sum of Core and Output Current  
35  
150  
mA  
kΩ  
RUP  
Pull-up Resistor on Input Pin  
100  
AC Electrical Characteristics  
Parameter[3]  
Description  
Output Duty Cycle  
Conditions  
Min.  
45  
Typ.  
Max.  
55  
2
Unit  
%
DC  
t3  
Duty Cycle is Defined in Figure 1, 50% of VDD  
50  
1.4  
1.4  
Rising Edge Slew Rate Output Clock Rise Time, 20%80% of VDD  
Falling Edge Slew Rate Output Clock Fall Time, 80%20% of VDD  
Output to Output skew CLK1 + CLK2 Equally Loaded  
0.8  
0.8  
V/ns  
V/ns  
ps  
t4  
2
t5  
200  
300  
3
t9  
Clock Jitter  
Peak to Peak Period Jitter with Spread Off  
ps  
t10  
PLL Lock Time  
ms  
Note:  
2. Rated for 10 years.  
3. Not 100% tested.  
Document #: 38-07361 Rev. **  
Page 2 of 5  
CY24210  
Test Circuit  
VDD  
CLK  
0.1 µF  
CLOAD  
OUTPUTS  
GND  
t1  
t2  
50%  
50%  
CLK  
Figure 1. Duty Cycle Definition; DC = t2/t1  
t3  
t4  
80%  
20%  
CLK  
Figure 2. Rise and Fall Time Definitions  
Ordering Information  
Ordering Code  
CY24210-3  
Package Name  
Package Type  
8-pin SOIC  
Operating Range  
Commercial  
Operating Voltage  
S8  
S8  
S8  
S8  
S8  
3.3V  
CY24210-4  
8-pin SOIC  
8-pin SOIC  
8-pin SOIC  
8-pin SOIC  
Commercial  
3.3V  
3.3V  
3.3V  
3.3V  
CY24210-5  
Commercial  
CY24210-6  
Commercial  
CY24210-7  
Commercial  
Document #: 38-07361 Rev. **  
Page 3 of 5  
CY24210  
Package Diagram  
8-lead (150-Mil) SOIC S8  
51-85066-A  
All product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-07361 Rev. **  
Page 4 of 5  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY24210  
Document Title: CY24210 100-MHz Clock Generator with Spread Spectrum  
Document Number: 38-07361  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
112458  
04/04/02  
CKN  
New Data Sheet  
Document #: 38-07361 Rev. **  
Page 5 of 5  

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