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CY24212SXC-5 [CYPRESS]

MediaClock⑩ MPEG Clock Generator with VCXO; MediaClock⑩ MPEG时钟发生器与VCXO
CY24212SXC-5
型号： CY24212SXC-5
厂家： CYPRESS    CYPRESS
描述：

MediaClock⑩ MPEG Clock Generator with VCXO
MediaClock⑩ MPEG时钟发生器与VCXO

晶体 时钟发生器 微控制器和处理器 外围集成电路 石英晶振 压控振荡器 光电二极管
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PRELIMINARY  
CY24212  
MediaClock™  
MPEG Clock Generator with VCXO  
Features  
• Integrated phase-locked loop (PLL)  
• Low jitter, high-accuracy outputs  
• VCXO with analog adjust  
• 3.3V operation  
Benefits  
Highest-performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Large ±150-ppm range, better linearity  
Enables application compatibility  
Part Number Outputs  
Input Frequency Range  
13.5 MHz/27 MHz (selectable)  
13.5 MHz/27 MHz (selectable)  
Output Frequencies  
CY24212-1  
CY24212-2  
CY24212-3  
CY24212-5  
1
2
2
2
27 MHz  
Two copies of 27 MHz  
27 MHz/27.027 MHz (-1 ppm)  
27 MHz/27.027 MHz (0 ppm)  
27 MHz  
27 MHz  
Logic Block Diagram  
OUTPUT  
DIVIDERS  
XIN  
OSC  
Q
Φ
CLKA (27 MHz)  
XOUT  
VCO  
PLL  
27 MHz (-2)  
27/27.027 MHz (-3)  
P
VCXO  
FSEL  
VSS  
VDD  
Pin Configurations  
CY24212-3,-5  
8-pin SOIC  
CY24212-1  
8-pin SOIC  
CY24212-2  
8-pin SOIC  
XOUT  
1
XOUT  
8
1
XOUT  
1
XIN  
8
8
XIN  
XIN  
7
6
5
2
3
4
CLKB (27/27.027 MHz)  
FSEL  
CLKA 27 MHz  
7
6
5
2
3
4
VSS  
FSEL  
CLKA 27 MHz  
2
3
4
7
6
5
VDD  
VCXO  
VSS  
CLKB 27 MHz  
VDD  
VCXO  
VSS  
VDD  
VCXO  
VSS  
FSEL  
CLKA 27 MHz  
Table 1. CY24212 (-1, -2) Frequency Select Option  
FSEL  
0
1
Reference  
13.5 MHz  
27 MHz  
CLKA/CLKB  
27 MHz  
27 MHz  
Table 2. CY24212 (-3, -5) Frequency Select Option  
FSEL  
0
1
Reference  
27 MHz  
27 MHz  
CLKA  
27 MHz  
27 MHz  
CLKB  
27 MHz  
27.027 MHz  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07402 Rev. *C  
Revised April 6, 2005  
PRELIMINARY  
CY24212  
Pin Description  
Name  
XIN  
Pin Number  
1
Description  
Reference Input.  
VDD  
VCXO  
VSS  
CLKA  
FSEL (-1,-2)  
2
3
4
5
6
Voltage Supply.  
Input Analog Control for VCXO.  
Ground.  
27-MHz Clock Output.  
Input Frequency Select, Weak Internal Pull-up.  
FSEL = 0, XIN = 13.5 MHz  
FSEL = 1, XIN = 27 MHz  
FSEL (-3,-5)  
6
Output Frequency Select, Weak Internal Pull-up.  
FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz  
FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz  
VSS (-1)  
7
7
7
8
Ground.  
27 MHz.  
27 MHz/27.027 MHz.  
Reference Output.  
CLKB (-2)  
CLKB (-3,-5)  
XOUT[1]  
Pullable Crystal Specifications  
Parameter  
Name  
Min.  
Typ.  
Max.  
Unit  
CRload  
Crystal Load Capacitance  
14  
pF  
C0/C1  
ESR  
To  
240  
50  
70  
Equivalent Series Resistance  
Operating Temperature  
35  
Ω
0
°C  
Crystal Accuracy  
TTs  
Crystal Accuracy  
Stability over Temperature and Aging  
± 20  
± 50  
ppm  
ppm  
Absolute Maximum Conditions  
Parameter  
VDD  
Description  
Min.  
–0.5  
–65  
Max.  
7.0  
125  
125  
Unit  
V
°C  
°C  
V
Supply Voltage  
TS  
TJ  
Storage Temperature[2]  
Junction Temperature  
Digital Inputs  
V
SS – 0.3  
2
VDD + 0.3  
Electrostatic Discharge  
kV  
Recommended Operating Conditions  
Parameter  
VDD  
Description  
Operating Voltage  
Ambient Temperature  
Max. Load Capacitance  
Reference Frequency  
Min.  
3.135  
0
Typ.  
3.3  
Max.  
3.465  
70  
15  
Unit  
V
°C  
pF  
MHz  
TA  
CLOAD  
fREF  
13.5  
27  
Notes:  
1. Float XOUT if XIN is externally driven.  
2. Rated for ten years.  
Document #: 38-07402 Rev. *C  
Page 2 of 6  
PRELIMINARY  
CY24212  
DC Electrical Specifications  
Parameter  
IOH  
IOL  
CIN  
IIH  
IIL  
f∆XO  
VVCXO  
IDD  
Name  
Description  
VOH = VDD – 0.5, VDD = 3.3V (source)  
VOL = 0.5, VDD = 3.3V (sink)  
Min  
12  
12  
Typ  
24  
24  
Max  
Unit  
mA  
mA  
pF  
µA  
µA  
ppm  
V
mA  
VDD  
VDD  
kΩ  
Output High Current  
Output Low Current  
Input Capacitance  
Input High Current  
Input Low Current  
VCXO Pullability Range  
VCXO Input Range  
Supply Current  
7
10  
50  
VIH = VDD  
VIL = 0V  
–
–
±150  
0
5
–
VDD  
35  
Sum of Core and Output Current  
CMOS levels, 70% of VDD  
CMOS levels, 30% of VDD  
VIH  
VIL  
RUP  
Input High Voltage  
Input Low Voltage  
Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured VIN = 0V  
0.7  
0.3  
150  
100  
AC Electrical Specifications (VDD = 3.3V)  
Parameter[3]  
DC  
Name  
Output Duty Cycle  
Description  
Duty Cycle is defined in Figure 1, 50% of VDD  
Min  
45  
Typ  
50  
Max  
55  
Unit  
%
ER  
Rising Edge Rate  
Output Clock Edge Rate, Measured from 20%  
0.8  
1.4  
V/ns  
to 80% of VDD, CLOAD = 15 pF. See Figure 2.  
EF  
Falling Edge Rate  
Output Clock Edge Rate, Measured from 80%  
0.8  
1.4  
V/ns  
to 20% of VDD, CLOAD = 15 pF. See Figure 2.  
t9  
Clock Jitter  
Peak-to-peak period jitter  
300  
ps  
t10  
PLL Lock Time  
3
ms  
Test and Measurement Set-up  
VDDs  
Outputs  
CLOAD  
0.1 µF  
DUT  
GND  
Note:  
3. Not 100% tested.  
Document #: 38-07402 Rev. *C  
Page 3 of 6  
PRELIMINARY  
CY24212  
Voltage and Timing Definitions  
t1  
t2  
VDD  
50% of VDD  
0V  
Clock  
Output  
Figure 1. Duty Cycle Definition  
t4  
t3  
V DD  
80% of VDD  
20% of VDD  
0V  
Clock  
Output  
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4  
Ordering Information  
Ordering Code  
Package Name  
S8  
Package Type  
8-Pin SOIC  
8-Pin SOIC -Tape and Reel  
8-Pin SOIC  
8-Pin SOIC -Tape and Reel  
8-Pin SOIC  
8-Pin SOIC -Tape and Reel  
8-Pin SOIC  
8-Pin SOIC -Tape and Reel  
Operating Range  
Operating Voltage  
CY24212SC-1  
CY24212SC-1T  
CY24212SC-2  
CY24212SC-2T  
CY24212SC-3  
CY24212SC-3T  
CY24212SC-5  
CY24212SC-5T  
Lead-free  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
Commercial  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
S8  
S8  
S8  
S8  
S8  
S8  
S8  
CY24212SXC-5  
CY24212SXC-5T  
S8  
S8  
8-Pin SOIC  
8-Pin SOIC -Tape and Reel  
Commercial  
Commercial  
3.3V  
3.3V  
Document #: 38-07402 Rev. *C  
Page 4 of 6  
PRELIMINARY  
CY24212  
Package Drawing and Dimensions  
8-lead (150-Mil) SOIC S8  
PIN 1 ID  
4
1
1. DIMENSIONS IN INCHES[MM] MIN.  
MAX.  
2. PIN 1 ID IS OPTIONAL,  
ROUND ON SINGLE LEADFRAME  
RECTANGULAR ON MATRIX LEADFRAME  
0.150[3.810]  
0.157[3.987]  
3. REFERENCE JEDEC MS-012  
4. PACKAGE WEIGHT 0.07gms  
0.230[5.842]  
0.244[6.197]  
PART #  
S08.15 STANDARD PKG.  
SZ08.15 LEAD FREE PKG.  
5
8
0.189[4.800]  
0.196[4.978]  
0.010[0.254]  
0.016[0.406]  
X 45°  
SEATING PLANE  
0.061[1.549]  
0.068[1.727]  
0.004[0.102]  
0.050[1.270]  
BSC  
0.0075[0.190]  
0.0098[0.249]  
0.004[0.102]  
0.0098[0.249]  
0°~8°  
0.016[0.406]  
0.035[0.889]  
0.0138[0.350]  
0.0192[0.487]  
51-85066-*C  
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document  
may be the trademarks of their respective holders.  
Document #: 38-07402 Rev. *C  
Page 5 of 6  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
PRELIMINARY  
CY24212  
Document History Page  
Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO  
Document Number: 38-07402  
Issue  
Date  
09/09/02  
12/06/02  
02/19/03  
See ECN  
Orig. of  
REV.  
**  
*A  
*B  
*C  
ECN NO.  
117089  
120888  
123064  
345540  
Change Description of Change  
CKN  
CKN  
CKN  
RGL  
New Data Sheet  
Added -3  
Added -5  
Added Lead-free for -5 part  
Document #: 38-07402 Rev. *C  
Page 6 of 6  

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