CY24233 [ETC]

Clocks and Buffers ; 时钟和缓冲器\n


型号：	CY24233
厂家：	ETC
描述：	Clocks and Buffers 时钟和缓冲器\n 时钟
文件：	总5页 (文件大小：65K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY24233

MediaClock™ Clock Generator for DVD Players

Product Features

Product Description

• Two reference outputs (27.00 MHz)

• Two 33.8688-MHz outputs

• Two 512fs outputs (22.5792 MHz or 24.576 MHz)

• 27.00-MHz clock or crystal input

• 3.3V or 3.0V operation (2.5V functional)

• High-drive outputs

The CY24233 is a clock generator solution that supports DVD

digital disk players. It produces a complete set of clocks

needed to support the entire system. All output clocks are

synthesized from a single 27.00-MHz fundamental cut crystal

or input reference clock. The output clocks are precisely

synthesized to meet the systems low PPM error requirements.

• 16-pin TSSOP package

Table 1.

27-1Out

27-2Out

33-1Out

512-1Out

512-2Out

Test

FSEL

27.00 MHz

2.700 MHz

1.800 MHz

3.000 MHz

33.8688 MHz

22.5792 MHz

24.576 MHz

Pin Configuration

Block Diagram

XTI

XT0

TEST

VDD

OSC

27-1Out, 27-2Out

33-1Out or N/C¹

FSEL

VSS

27-1Out or N/C¹

27-2Out or N/C¹

33-2Out or N/C¹

PLL

33-1Out, 33-2Out

VDD

VSS

XT1

XT0

VSS

512-1Out

512-2Out

PLL

512-1Out, 512-2Out

FSEL

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07132 Rev. *B

Revised December 14, 2002

CY24233

Pin Description^[1,2]

Pin Number Pin Name I/O

Pin Description

3,4

27-1Out

27-2Out

3.3V fixed-frequency 27.00-MHz clock outputs. See Table 1 on page 1 for frequency

selection for test mode functionality.

9,10

13,15

14*

512-1Out

512-2Out

3.3V or 3.0V fixed frequency clock outputs. See Table 1 on page 1 for frequency selection.

33-1Out

33-2Out

3.3V fixed frequency 33.8688-MHz clock outputs. See Table 1 on page 1 for frequency

selection for test mode functionality.

FSEL

XTO

XTI

Frequency selection input. This pin controls the frequency that is present on two 512 output

clock pins.

On-chip reference oscillator pin. Drives an external crystal. When an externally generated

reference signal is used at XTI, this pin remains unconnected. Bypass with a proper capaci-

tance to ground to match the external crystal’s load capacitance.

On-chip reference oscillator input pin. Requires either an external crystal (nominally 27

MHz) or externally generated reference signal. Bypass with a proper capacitance to ground to

match the external crystal’s load capacitance.

1, 5, 12

2,6,11

VDD

VSS

3.3V or 3.0V power supply.

PWR

Device ground for all circuitry.

TEST

Internal pull up. If this input pin is asserted low, it will set this device into a test mode. See

Table 1 on page 1.

Table 2. Maximum Lumped Capacitative Output Loads

Clock

27-1Out

Max Load

Units

27-2Out

33-1Out,33-2Out, 512-1Out,512-2Out

FSEL Switching Synchronization

The FSEL input is used to select the frequency of the clocks

on the 512-1Out and 512-2Out pins. The device contains

internal clock edge synchronization to insure that when the

state of this pin is changed while the clocks are running no

short (runt) or long (stretched) clocks will occur in the output

streams. This is to say that the transitions will be made at a

naturally occurring clock edge of the former clocks period and

the cycle immediately after the change will be of a full newly

selected clocks period and duty cycle.

FSEL Switching Synchronization

Finish Cycle

Start at Full Cycle

Wait

Notes:

1. Part may be operated with Pins 3,4,13,15 soldered to pads on PCB with no PCB trace connected to these pads, i.e., floating.

2. Table Nomenclature: All pin numbers with an asterisks (*) immediately after them indicates that they have an internal pull-up resistor to ensure that they will

be sensed as a logic HIGH even if no external circuitry is attached to them. I = Input pins, O = Output pins and PWR = Power connection pins.

Document #: 38-07132 Rev. *B

Page 2 of 5

CY24233

Maximum Ratings^[3]

This device contains circuitry to protect the inputs against

damage due to high static voltages or electric fields; however,

precautions should be taken to avoid application of any

voltage higher than the maximum rated voltages to this circuit.

For proper operation, V_inand V_outshould be constrained to the

range:

Maximum Input Voltage Relative to V_SS: ............. V_SS– 0.3V

Maximum Input Voltage Relative to V_DD:.............V_DD+ 0.3V

Storage Temperature: .................................–65°C to +150°C

Operating Temperature:................................–20°C to +85°C

Maximum ESD protection ............................................... 2KV

Maximum Power Supply: ................................................5.5V

Operating Voltage: ...................................................2.5–3.6V

V_SS< (V_INor V_OUT) < V_DD

Unused inputs must always be tied to an appropriate logic

voltage level (either V_SSor V_DD).

DC Parameters (V_DD= 3.3V ± 10%, T_A= –10°C to +75°C or V_DD= 3.0V ± 10%, T_A= –20°C to +85°C)

Parameter

V_IL

Description

Input Low Voltage^[3]

Input High Voltage

Input Low Current

Conditions

Min.

–

Typ.

–

Max.

0.8

–

Unit

Vdc

µA

V_IH

I_IL

2.0

–18

–

For internal Pull-up resistors^[3,5]

I_ILmeasured at V_IN= GND, I_IHmeasured

at V_IN= V_DD

–8

–3.5

I_IH

Input High Current

Input Hysteriss^[3]

Dynamic Supply Current Test = 1, FSEL=1^[6]

–

250

–

410

–

750

0.4

–

µA

V_HYS

I_dd3.3V

I_dd3.0V

V_OL

–

Output Low Voltage

Output High Voltage

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

I_OL= 4.0 mA

I_OH= 4.0 mA

–

V_OH

C_in

2.4

–

C_out

L_pin

–

C_xtal

Crystal Pin Capacitance

–

[7]

AC Parameters (V_DD= 3.3V ± 10%, T_A= –10°C to +75°C)

Parameter

T_R

Description

Conditions

Min.

–

Typ.

Max.

Unit

Rise Time

Fall Time

All clocks at rated load^[8]

All Output Clocks

T_F

–

T_PU

T_DC1

T_j2

Power up to Stable Output

–

Clock Duty Cycle (all output clocks)

Clock Jitter (33-1Out,33-2Out)

Clock Jitter (512-1Out,512-2Out)

Clock Jitter (27-1Out,27-2Out)

Crystal Oscillator Start-up Time

All clocks at rated load^[9]

–

150

–

200

350

Cycle to cycle jitter

(Peak–Peak, 10,000 cycles )

T_j2

–

All clocks at rated load^[9]

T_j3

–

T_XS

–

µs

AC Parameters (V_DD= 3.0V ± 10%, T_A= –20°C to +85°C, only 512-1Out and 512-2out Loaded)

Parameter

T_R

Description

Conditions

All clocks at rated load^[8]

All output clocks

Min.

Typ.

Max.

Units

Rise Time

Fall Time

–

2.5

–

T_F

T_PU

Power-up to Stable Output

Notes:

3. Multiple Supplies:The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

4. Applicable to input signal: FSEL and Test pins.

5. Although internal pull-up resistors have a typical value of 400K, this value may vary between 200K and 800K.

6. All outputs loaded as perTable 2 on page 2.

7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.

8. Measured between 0.2* V_DDand 0.8*V_DDV.

9. Triggering is done at 1.5V.

Document #: 38-07132 Rev. *B

Page 3 of 5

CY24233

AC Parameters (V_DD= 3.0V ± 10%, T_A= –20°C to +85°C, only 512-1Out and 512-2out Loaded) (continued)

Parameter

T_DC1

Description

Conditions

All clocks at rated load⁹

Min.

Typ.

Max.

Units

Clock Duty Cycle (all output

clocks)

T_j2

Clock Jitter (512-1Out,512-2Out) Cycle to cycle jitter

–

200

250

(Peak-to-Peak, 10,000 cycles)

All clocks at rated load⁹

T_XS

Crystal Oscillator Start-up Time

–

µs

Ordering Information

Part Number

CY24233ZC

CY24233ZCT

Package Type

Product Flow

16-pin TSSOP

16-pin TSSOP–Tape and Reel

Commercial, –20° to 85°C

Package Diagram

16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16

51-85091

MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the

trademarks of their respective holders.

Document #: 38-07132 Rev. *B

Page 4 of 5

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY24233

Document Title: CY24233 MediaClock™ Clock Generator for DVD Players

Document Number: 38-07132

Orig. of

REV.

ECN NO. Issue Date Change

Description of Change

110596

116543

11/29/01

08/22/02

DMG

CKN

New Data Sheet

Changed values in DC and AC parameters for operation at 3.0V ±10%, and

ambient temp. range from –20°C to 85°C: jitter, rise time, fall time

Explictly allow use with only 512 outputs loaded.

122795

12/14/02

RBI

Power up Requirements to Operating Conditions Information

Document #: 38-07132 Rev. *B

Page 5 of 5

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