CY24488_技术文档

CY24488

Quad PLL Clock Generator with Serial

Interface (I²C)

Features

Benefits

• Three output frequencies plus reference out

• Meets most Digital Set Top Box, DVD Recorder, and DTV

application requirements

• Programmable output frequencies via I²C serial interface

• Output frequencies from 4.9152 to 148.5 MHz

• Uses an external 27 MHz crystal or 27 MHz input clock

• Optional analog VCXO

• Multiple high-performance PLLs allow synthesis of

unrelated frequencies

• Integration eliminates the need for external loop filter

components

• Programmable output drive strength to minimize EMI

• The non-I²C equivalent is the CY22388 / 89 / 91

• 16-pin TSSOP package

• Complete VCXO solution with ±120 ppm (typical pull range)

• 3.3V operation with 2.5V output buffer option

Pin Configuration

Block Diagram

CLKC

XIN/CLKIN

SCLK

SDAT

VIN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

XOUT

AVDD

DNC

PLL1

XIN/CLKIN

VCXO

CLKD

CLKE

CLKF

CLKG

XOUT

PLL2

PLL3

PLL4

Dividers

&

Multiplexers

VIN

VDD2

VSS

VDD1

VSS

CLKG

CLKF

CLKE

Serial

Interface

&

Select

Logic

SCLK

SDAT

CLKC

CLKD

Table 1. Applications and Frequencies

Output Clock

CLKC

Application

Frequencies (MHz)

6.144, 8.192, 11.2896, 12.288, 16.384, 16.9344, 18.432, 22.5792, 24.576,

33.8688, 36.864

Audio

iLink

HDMI

24.576

25.175, 28.322

CLKD

CLKE

Video

27, 27.027, 54, 54.054, 81

12, 24, 48

USB

Video-Pixel Freq.

Modem

74.25/1.001, 74.25, 148.5/1.001, 148.5

4.9152, 11.0592

iLink

24.576

Video

13.5, 27, 54, 81, 108

25

Ethernet

PCI

33.3333, 66.6666

Processor

see CLKC/D/E

20, 30, 40, 50, 60, 80, 100

REFOUT or Copy of CLKC, CLKD or CLKE

CLKF

CLKG

Cypress Semiconductor Corporation

Document #: 001-09608 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 31, 2006

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CY24488

Pin Description

Pin Name

XIN/CLKIN

XOUT

CLKC

CLKD

CLKE

CLKF

Pin Number

Pin Description

Crystal Input (27 MHz) or External Input Clock (27 MHz)

Crystal Output

1

16

7

Clock Output

8

Clock Output

9

Clock Output

10

11

2

Clock Output

CLKG

SCLK

SDAT

VIN

Clock Output

Serial Interface (I2C) Clock Input

Serial Interface (I2C) Data

Analog Control Input for VCXO

Do Not Connect. This pin should be left floating.

Core and input Voltage Supply

Voltage Supply for Outputs CLKC

Voltage Supply for Outputs CLKD, CLKE, CLKF, CLKG

Ground

3

4

DNC

14

15

5

AVDD

VDD1

VDD2

VSS

13

6,12

frequencies. Because the serial programming memory is

volatile, the device will revert to its default configuration when

power is cycled.

General Description

The CY24488 generates up to three independent clock

frequencies, plus a buffered copy of the reference crystal

frequency, from a single crystal or reference input. Five clock

output pins are available, which allows some frequencies to be

driven on two or more output pins. Outputs can also be individ-

ually enabled or disabled. When a CLK output is individually

disabled, it drives low.

Reference Input

There are three programmable reference operating modes for

the CY24488 family of devices. Table 2 shows the data values

that must be programmed into the device for each of the

reference operating modes. The correct values are required to

ensure frequency accuracy and VCXO pullability.

The analog voltage controlled crystal oscillator (VCXO) allows

the user to “pull” the reference crystal to a frequency that is

slightly higher or lower than nominal. Doing so will cause all

output clocks to shift by an equivalent parts-per-million (PPM).

The VCXO is controlled by the analog control voltage applied

to the VIN pin. For applications that do not require the VCXO

functionality, it can be disabled.

The first mode utilizes an external 27 MHz pullable crystal and

incorporates the internal analog VCXO. The crystal is

connected between the XIN/CLKIN and XOUT pins. See

“Crystal Requirements” for further details.

The second mode disables the VCXO input control and utilizes

a standard 27 MHz crystal. Crystal requirements are relaxed

relative to the VCXO mode. The crystal is connected between

the XIN/CLKIN and XOUT pins. See “Crystal Requirements.”

In this mode, tie the VIN pin to AVDD.

A serial programming interface (SPI) permits in-system config-

uration of the device by writing to internal registers. It is used

to set the output frequencies, enable and disable outputs,

enable and disable the VCXO feature, etc. The SPI provides

volatile programming. When powered down, the device

reverts to its pre-SPI state. When the system is powered back

up, the SPI registers will need to be configured again. Specific

configuration details are given later in this data sheet.

The third mode accepts an external 27 MHz reference clock,

applied to the XIN/CLKIN pin. In this configuration, the XOUT

pin must be unconnected. The VCXO feature is not available;

tie the VIN pin to AVDD.

Customers may contact their Cypress FAE or salesperson for

any frequency that is not listed in this data sheet. The data

sheet can be updated with a new hex code for the requested

frequency.

Analog VCXO

The VCXO feature allows the user to fine tune the output

frequency via a control voltage applied to the VIN pin. A

special pullable crystal must be used in order to have

adequate VCXO pull range. This data sheet lists specific

crystals that have been qualified for used with the CY24488.

Specific serial programming values are also given for each

crystal.

Default Start-up Configuration

The default state of the device refers to its state at power on.

All output clocks are off except CLKG, which outputs a copy of

the 27 MHz reference clock. The serial programming interface

must be used to configure the device for the desired output

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CY24488

The special crystal requirements are eliminated if the VCXO

feature is not needed. To disable the VCXO, the VIN pin must

be tied high, and the appropriate register values given in the

programming table must be programmed into the device.

clock frequencies, as shown in the tables below. To do this,

find the desired frequency from the appropriate table, then use

the serial programming interface to write the specified

hexadecimal data into the specified memory addresses.

The VCXO is completely analog, so there is infinite resolution

on the VCXO pull curve. The analog-to-digital converter steps

that are normally associated with a digital VCXO input are not

present in this device.

In some cases the data at a particular memory address

controls multiple functions, so only some of the bit values are

specified. Since a byte is the smallest unit of data that can be

written, it is necessary to construct the full data byte prior to

writing it. To do this, look in the other tables to find the correct

values for the other bits in that byte.

VCXO Profile

Figure 1 shows an example of what a VCXO profile looks like.

The analog voltage input is on the X-axis and the PPM range

is on the Y-axis. An increase in the VCXO input voltage results

in a corresponding increase in the output frequency. This has

the effect of moving the PPM from a negative to positive offset

Any of the remaining output clocks (CLKF and CLKG) can be

configured to generate duplicate copies of any the three

primary clocks. Any of them can also drive a buffered version

of the reference crystal frequency.

Enabling and Disabling Output Clocks

Figure 1. VCXO Profile

All output clocks can be individually enabled or disabled. Only

CLKG is on at power on. All other clocks are off (driven low),

and their respective PLLs are off. When using the serial

programming interface to set an output to a desired frequency,

the PLL Lock Time (AC Parameters Table) applies.

200

150

100

50

When turning off an output, the output buffer and associated

PLL are turned off by different register addresses. Therefore it

is possible to turn off an output by programming just one byte,

but the PLL will continue to run and consume some power.

Therefore the PLL Lock Time does not apply when turning the

output back on.

0

0.5

1

1.5

2

2.5

3

3.5

-50

-100

-150

-200

VCXO input [V]

The clock configuration tables also show a second off state

that also turns off the PLL, saving additional power. This

requires programming one or two additional bytes, and the

PLL Lock Time applies.

Crystal Requirements

The crystal requirements for the CY24488 differ for the VCXO

and non-VCXO modes. In all cases, the device must be

programmed correctly for the specific crystal used, as

indicated in Table 2.

Output Drive Strength

Output drive strength is configurable, with 2 bits available to

set the drive strength for each output. The default value is ‘10’,

which is medium-high. This is the recommended setting for

outputs operating at 3.3V. The recommended setting for 2.5V

outputs is ‘11’, which must be programmed by the user.

Table 10 shows which bits must be changed, and how to

integrate these bits with other control bits to create valid bytes

for shifting in.

Crystals for Non-VCXO Mode

When not using the VCXO, the VIN pin should be tied high.

The CY24488 uses a standard AT-cut parallel resonant

crystal, which is available in a variety of packages. The key

crystal parameter is load capacitance (C_L). The CY24488 has

programmable load capacitance, to match a range of crystal

C_Lvalues. The specific configurations are shown in Table 2.

Crystals with C_Lvalues outside this range are not recom-

mended.

The user may program any output to a lower drive strength if

EMI is a problem. ‘00’ is the lowest drive strength, while ‘11’ is

the highest. Note that the lowest setting is very weak and is

not suitable for most applications.

Pullable Crystals for VCXO Mode

Output Supply Voltage

When the VCXO mode is used, the crystal requirements

increase considerably in order to ensure the pullable range

and glitch-free pulling. Table 2 lists the crystals that Cypress

has qualified for use with the CY24488, as well as the corre-

sponding programming configurations. Customers wishing to

use non-qualified crystals should first contact Cypress

technical support.

The clock outputs may be operated at either 3.3V or 2.5V.

CLKC has its own power pin (VDD1), while all other clocks are

powered by VDD2. VDD1 and VDD2 may be operated at

different voltages if desired. AVDD must always be 3.3V.

The CY24488 also has internal register settings that should be

configured for the actual output supply voltage. The default

settings are optimized for VDD1 = VDD2 = 3.3V. Table 10 and

Table 3 show the values that need to be programmed for 2.5V

supply voltage.

Output Configurations

CLKC, CLKD, and CLKE are the three primary synthesized

output clocks. For each one, the user can select from several

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CY24488

Example: configure CLKC for 33.8688 MHz and 2.5V output.

For address 48H, start with the value in Table 4: 89H (binary

10001001). Table 9 shows that bits 7 & 6 control the drive

strength, which should be ‘11’ (from Table 10). Therefore, the

final value is 11001001, which is C9H. This value is written

once.

Programming Flow

The device registers may be programmed in any sequence,

but for convenience, a suggested programming flow is shown

in Figure 2.

Any step in this programming sequence may be skipped if the

default value is the desired value.

Figure 2. Programming Flow

When programming an output frequency, the new frequency

will be valid on that output after all of the specified data values

have been written to all of the specified addresses. When

changing an output frequency, the output may transition

through one or more indeterminate frequencies between the

writing of the first byte and the last byte.

Default

CLKC, D & E

Frequency settings

(Tables 4 - 6)

Note that some of the programming steps are not as

independent as they appear in the flow diagram. In particular,

addresses 48H, 53H, and 57H control both output frequencies

and drive strength. Because a byte is the smallest unit that

may be programmed through the serial interface, the user

must consider both the frequency setting and the output drive

strength when constructing the byte value to be written into

these particular address. It is not necessary to write more than

once to any given address, but that one write must have all of

the bits set correctly.

Reference CLK &

Crystal settings

CLKF & G

Frequency settings

(Tables 7 - 8)

(Table 2)

Output Supply

Voltage settings if

2.5V (Table 3)

Drive Strength

settings for 2.5V

or EMI

(Tables 9, 4, 6, 8)

Table 2. Register Settings for VCXO and Reference

Reference Clock and VCXO

Crystal

Package

–

Address

16H

Manufacturer Part No.

Specified C_L

17H

3A

4F

5F

67

CLKIN (external reference), VCXO off

Crystal, VCXO off

–

89

88

any

10.7 pF

12 pF

12.6 pF

14 pF

12.6 pF

10.7 pF

12 pF

Crystal, VCXO off

any

Crystal, VCXO off (default)

Crystal, VCXO off

any

77

Crystal, VCXO on

KDS DSX530GA

RIVER FCX-03

KDK

5x3.2 mm

SMD-49

3A

2A

41

Crystal, VCXO on

3A

39

Crystal, VCXO on

KDS

Crystal, VCXO on

Ecliptek ECX-6277

41

Table 3. Register Settings for Output Supply Voltages

Address

Output

Output Supply Voltages

41H

43H

–

CLKC

VDD1 = 3.3V

VDD1 = 2.5V

VDD2 = 3.3V

VDD2 = 2.5V

BF (default)

7F

–

CLKD, CLKE, CLKF, CLKG

A0 (default)

90

–

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CY24488

Table 4. CLKC Output Frequencies (Audio, iLink, or HDMI)

Frequency

Register Address

Frequency (MHz)

Application

48H^[1]

Error

0AH

0BH

0CH

0DH

0EH

0FH

CLKC off and PLL off

(default)

–

88

–

44

8D

CLKC off

–

HDMI

Audio

Audio, iLink

Audio

–

8D

AD

91

A5

A9

81

89

B5

95

A5

85

A9

89

25.175

0 ppm

01

10

17

07

39

3E

D2

E2

D0

26

94

1C

19

1C

30

18

39

06

0E

06

16

72

6A

64

66

28.322

6.144 (48K x 128)

12.288 (32K x 384)

16.384 (32K x 512)

18.432 (48K x 384)

24.576 (48K x 512)

36.864 (48K x 768)

11.2896 (44.1K x 256)

16.9344 (44.1K x 384)

22.5792 (44.1K x 512)

33.8688 (44.1K x 768)

Table 5. CLKD Output Frequencies (Video, Pixel rate, USB, modem or iLink)

Frequency

Register Address

Frequency (MHz)

Application

Error

10H

11H

–

12H

00

–

50H

8E

A2

86

8A

A2

A6

82

9A

86

8A

96

B6

B2

CLKD off and PLL off (default)

–

CLKD off

12

–

USB

0 ppm

+38 ppm

+11 ppm

6 ppm

0 ppm

01

07

18

39

56

–

08

1E

21

8F

8E

–

30

26

28

33

02

33

30

33

2C

22

30

2C

22

24

USB

48

USB

4.9152

Modem

iLink

11.0592

24.576

27 (reference)

27.027

Video

7B

02

7B

59

00

59

00

F2

0E

F2

F8

03

07

F8

03

54 (ref * 2)

54.054

Video

74.25/1.001

74.25

Video pixel rate

Video

81 (ref * 3)

148.5/1.001

148.5

Video pixel rate

Note

1. Bits [7:6] control CLKC drive strength. The values given in this table correspond to a drive strength setting of ‘10’. See Table 9 and Table 10.

Document #: 001-09608 Rev. *A

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CY24488

Table 6. CLKE Output Frequencies (Ethernet, Video, PCI, Processor)

Frequency

Register Address

Frequency (MHz)

Application

53H^[2]

3E

Error

13H

14H

–

15H

00

–

CLKE off and PLL off (default)

–

CLKE off

–

3E

13.5

Video

0 ppm

00

–

05

–

26

02

24

30

28

30

28

30

8E

27 (reference)

Video

6E

54

Video

00

07

01

19

07

19

01

19

07

19

06

07

06

26

17

08

62

26

62

08

62

26

62

2E

81

Video

DE

5E

108

Video

20

Processor

Ethernet

Processor

PCI

9E

25

AE

2E

30

33.333333

40

Processor

PCI

50

60

DE

5E

66.666666

80

Processor

100

Table 7. CLKF Output Clock

Frequency (MHz)

Address 55H

Data value (hex)

CLKF off (default)

27 MHz reference

Copy of CLKC

0C

18

copy of data from Table 4 address 48H

Copy of CLKD

copy of data from Table 5 address 50H

Copy of CLKE

copy of data from Table 6 address 53H, divided by 4^[3]

\

Table 8. CLKG Output Clock (Default = Reference out)

Frequency (MHz)

Address 57H

bits [7:6]

10

bits [5:0]

001100

011000

CLKG off

27 MHz reference (default)

Copy of CLKC

Copy of CLKD

Copy of CLKE

drive strength (default=10) – see Table 10

bits[5:0] of address 48H – see Table 4

bits[5:0] of address 50H – see Table 5

bits[7:2] of address 53H – see Table 6

Notes

2. Bits [1:0] control CLKD drive strength. The values given in this table correspond to a drive strength setting of ‘10’. See Table 9 and Table 10.

3. Bits [7:6] of address 55H are don’t care. Dividing by 4 is equivalent to right shifting by 2 bits.

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CY24488

Table 9. Register Settings for Output Drive Strength^[4]

Output Clock

CLKC

Drive strength bits

bits[7:6] of 48H

bits[1:0] of 53H

bits[7:6] of 54H

bits[5:4] of 56H

bits[7:6] of 57H

bit 7

bit 6

bit 5

bit 4

see address 48H in Table 4

see address 53H in Table 6

bit 3

bit 2

bit 1

bit 0

DS

CLKD

CLKE

CLKF

CLKG

DS

0

1

DS

see address 57H in Table 8

[]

Table 10. Drive Strength (DS) Values^[4]

DS Value

Drive Strength

Very low

3.3V Output

2.5V Output

EMI Adjustment

Standard

00

01

EMI Adjustment

Standard

Medium low

Medium high

High

10 (default)

11

Extra Drive

Notes

4. The default drive strength (DS) setting for all clocks is ‘10’. All output specifications for 3.3V outputs are given for this value. Output specifications for 2.5V outputs

are given for a setting of ‘11’. To change the DS settings, the serial programming interface must be used to program in the desired values. Users may program

in any 2-bit value, but certain output specifications will not be valid for settings other than ‘10’ (3.3V) or ‘11’ (2.5V). See the DC Parameters and AC Parameters

tables for further details.

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CY24488

Writing Multiple Bytes

Serial Programming Interface Protocol and

Timing

In order to write more than one byte at a time, the master does

not end the write sequence with a STOP condition. Instead,

the master can send multiple contiguous bytes of data to be

stored. After each byte, the slave responds with an

acknowledge bit, the same as after the first byte, and will

accept data until the acknowledge bit is responded to by the

STOP condition. When receiving multiple bytes, the CY24488

internally increments the register address.

The CY24488 utilizes pins SDAT and SCLK for a 2-wire serial

interface that operates up to 400 kbit/s in Read or Write mode.

The basic Write protocol is as follows:

Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; etc. until STOP Bit. The basic serial format is

illustrated in Figure 4.

Read Operations

Read operations are initiated the same way as Write opera-

tions except that the R/W bit of the slave address is set to ‘1’

(HIGH). There are three basic read operations: current

address read, random read, and sequential read.

Device Address

The device address is a 7-bit value. The default serial interface

address is 47H.

Data Valid

Current Address Read

Data is valid when the clock is HIGH, and may only be transi-

tioned when the clock is LOW, as illustrated in Figure 5.

The CY24488 has an onboard address counter that retains 1

more than the address of the last word access. If the last word

written or read was word ‘n’, then a current address read

operation would return the value stored in location ‘n+1’. When

the CY24488 receives the slave address with the R/W bit set

to a ‘1’, the CY24488 issues an acknowledge and transmits

the 8-bit word. The master device does not acknowledge the

transfer, but does generate a STOP condition, which causes

the CY24488 to stop transmission.

Data Frame

Every new data frame is indicated by a start and stop

sequence, as illustrated in Figure 6.

START Sequence - Start Frame is indicated by SDAT going

LOW when SCLK is HIGH. Every time a start signal is given,

the next 8-bit data must be the device address (seven bits) and

a R/W bit, followed by register address (eight bits) and register

data (eight bits).

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first

set the word address. Send the address to the CY24488 as

part of a write operation. After the word address is sent, the

STOP Sequence - Stop Frame is indicated by SDAT going

HIGH when SCLK is HIGH. A Stop Frame frees the bus to

write to another part on the same bus or writing to another

random register address.

master generates

a

START condition following the

acknowledge. This terminates the write operation before any

data is stored in the address, but not before the internal

address pointer is set. Next the master reissues the control

byte with the R/W byte set to ‘1’. The CY24488 then issues an

acknowledge and transmits the 8-bit word. The master device

does not acknowledge the transfer, but does generate a STOP

condition, which causes the CY24488 to stop transmission.

Acknowledge Pulse

During Write Mode the CY24488 will respond with an

Acknowledge (ACK) pulse after every eight bits. This is

accomplished by pulling the SDAT line LOW during the N*9^th

clock cycle, as illustrated in Figure 7 (N = the number of bytes

transmitted). During Read Mode the acknowledge pulse after

the data packet is sent is generated by the master.

Sequential Read

Write Operations

Sequential read operations follow the same process as

random reads except that the master issues an acknowledge

instead of a STOP condition after transmission of the first 8-bit

data word. This action results in an incrementing of the internal

address pointer, and subsequently output of the next 8-bit data

word. By continuing to issue acknowledges instead of STOP

conditions, the master may serially read the entire contents of

the slave device memory. Note that register addresses outside

of 0AH to 17H and 40H to 57H can be read from but are not

real registers and do not contain configuration information.

When the internal address pointer points to the FFH register,

after the next increment, the pointer will point to the 00H

register.

Writing Individual Bytes

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is

followed by an acknowledge bit from the slave (SDAT =

0/LOW). The next eight bits must contain the data word

intended for storage. After the data word is received, the slave

responds with another acknowledge bit (SDAT = 0/LOW), and

the master must end the write sequence with a STOP

condition.

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CY24488

Figure 3. Data Transfer Sequence on the Serial Bus

SCL

SDAT

STOP

Condition

Address or

Acknowledge

Valid

Data may

be changed

START

Condition

Figure 4. Data Frame Architecture

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

R/W = 0

SDAT Write

Multiple

Contiguous

Registers

7-bit

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

Device

Address

Register Register Register

Address Data

Data

(XXH+1)

(XXH)

(XXH+2)

(FFH)

(00H)

Stop Signal

Start Signal

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

R/W = 1

SDAT Read

7-bit

Device

Address

Current

Address

Read

8-bit

Register

Data

Stop Signal

Start Signal

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

R/W = 0

SDAT Read

Multiple

Contiguous

Registers

7-bit

Device

Address

8-bit

7-bit

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

Register Device

Address

(XXH)

Address

+R/W=1

(XXH)

(XXH+1)

(FFH)

(00H)

Stop Signal

Start Signal

Repeated

Start bit

Figure 5. Data Valid and Data Transition Periods

Transition

to next Bit

Data Valid

SDAT

t_DH

t_SU

CLK_HIGH

VIH

VIL

SCLK

CLK_LOW

Document #: 001-09608 Rev. *A

Page 9 of 15

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Serial Programming Interface Timing

Figure 6. Start and Stop Frame

SDAT

SCLK

Transition

to next Bit

START

STOP

Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)

SDAT

+

START

D7

D6

D1

D0

DA6

DA5 DA0

R/W

ACK

RA7

RA6 RA1

RA0

ACK

STOP

+

SCLK

Serial Programming Interface Timing Specifications

Parameter

f_SCLK

Description

Frequency of SCLK

Min.

Max.

Unit

–

0.6

1.3

0.6

100

0

400

–

kHz

s

ns

s

Start Mode Time from SDA LOW to SCL LOW

SCLK LOW Period

CLK_LOW

CLK_HIGH

t_SU

–

SCLK HIGH Period

–

Data Transition to SCLK HIGH

Data Hold (SCLK LOW to data transition)

Rise Time of SCLK and SDAT

Fall Time of SCLK and SDAT

–

t_DH

–

300

–

Stop Mode Time from SCLK HIGH to SDAT HIGH

Stop Mode to Start Mode

0.6

1.3

–

Document #: 001-09608 Rev. *A

Page 10 of 15

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Absolute Maximum Conditions

Parameter

Description

Condition

Min.

Max.

Unit

AV_DD/V_DD1Core Supply Voltage

/V_DD2

–0.5

4.6

V

V_IN

Input Voltage

Relative to VSS

Non-Functional

–0.5

–65

2000

–

V_DD+ 0.5 VDC

T_S

Temperature, Storage

+125

–

°C

ESD_HBM

UL-94

MSL

ESD Protection (Human Body Model) MIL-STD-883, Method 3015

Volts

ppm

Flammability Rating

V-0 @1/8 in.

16 TSSOP

10

Moisture Sensitivity Level

1

Pullable Crystal Specifications (for VCXO applications)^[5]

Parameter

F_NOM

Description

AT-cut Crystal

Comments

Min. Typ. Max. Unit

Parallel resonance, Fundamental mode

27

12

MHz

pF

C_LNOM

Nominal Load Capacitance

Order crystal at one specific C_LNOM

0 ppm

11.4

12.6

R₁

DL

Equivalent Series Resistance (ESR)

Crystal Drive Level

Fundamental mode (CL = Series)

–

40



Nominal V_DD@ 25°C over ±120 ppm Pull

Range

300

W

[6]

F_3SEPHI

Third Overtone Separation from 3*F_NOMMechanical Third (High side of 3*F_NOM

Third Overtone Separation from 3*F_NOMMechanical Third (Low side of 3*F_NOM

)

240

–

ppm

[6]

F_3SEPLO

)

–

–120 ppm

Non-pullable Crystal Specifications (for non-VCXO applications)^[5]

Parameter

F_NOM

Description

AT-cut Crystal

Comments

Min. Typ. Max. Unit

Parallel resonance, Fundamental mode

27

12

MHz

pF

C_LNOM

Nominal Load Capacitance

Order crystal at one specific C_LNOM

0 ppm

10.7

14.0

R₁

DL

Equivalent Series Resistance (ESR)

Crystal Drive Level

Fundamental mode (CL = Series)

Nominal V_DD@ 25°C

–

40



300

W

Recommended Operating Conditions

Parameter

Description

Min. Typ. Max. Unit

AV_DD

Core Operating Voltage

3.0

2.3

–10

–

3.3

2.5

–

3.6

2.7

70

V

V_DD1/V_DD2Output Operating Voltage

V

T_A

Ambient Temperature

°C

pF

ms

C_LOAD

t_PU

Maximum Load Capacitance

–

15

Power up time for all V_DDs reach minimum specified voltage (power ramps must be 0.05

monotonic)

–

500

Notes

5. Device operates to following specs which are guaranteed by design.

6. Increased tolerance available from pull range less than ±120 PPM.

Document #: 001-09608 Rev. *A

Page 11 of 15

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DC Parameters ^[7]

Parameter

Description

Conditions

V_OH= V_DD– 0.5, V_DD= 3.3V

V_OL= 0.5, V_DD= 3.3V

Min.

Typ.

Max.

–

Unit

mA

µA

V

[8]

I_OH

Output High Current

Output Low Current

Input High Current

Input Low Current

Input High Voltage

Input Low Voltage

12

–

5

–

[8]

I_OL

I_IH

12

–

V_IH= V_DD, excluding Vin, XIN/CLKIN

V_IL= 0V, excluding Vin, XIN/CLKIN

XIN/CLKIN input CMOS levels

–

10

–

I_IL

–

0.7xAV_DD

–

V_IH

V_IL

0.3xAV_D

D

V

V_VCXO

C_IN

VIN Input Range

Input Capacitance

Supply Current

0

–

AV_DD

V

XIN/CLKIN pin only

TBD

pF

mA

pF

I_VDD

V_DDCurrent

60

15

–

C_INXIN

Input Capacitance at

XIN/CLKIN

VCXO Disabled External Reference

C_INXTAL

Input Capacitance at Crystal VCXO Disabled Fixed Freq. Oscillator

–

12

–

pF

AC Parameters^[7]

Parameter

Description

Conditions

PLL _minmax/Divider_maximum

Min. Typ. Max. Units

1/t1

DC1^{[8, 9]}

Output Frequency

4.2

45

–

166 MHz

Output Duty Cycle

(excluding REFOUT

Duty Cycle is defined in Figure 9; t₂/t₁, 50% of V_DD

50

55

60

%

External reference duty cycle between 40% and 60%

measured at V /2 (Clock output is 125 MHz)

DD

DC2^{[8, 9]}

Output Duty Cycle

(excluding REFOUT

Duty Cycle is defined in Figure 9; t₂/t₁, 50% of V_DD

40

50

External reference duty cycle between 40% and 60%

measured at V /2 (Clock output is 125 MHz)

DD

[8, 9]

DC_REFOUT

ER^[8]

EF^[8]

T₉

Output Duty Cycle

Rising Edge Rate

Falling Edge Rate

Clock Jitter

Duty Cycle is defined in Figure 9; t₂/t₁, 50% of V_DD

(XIN/CLKIN Duty Cycle = 45/55%)

50

1.2

±250

1

60

–

%

Output Clock Edge Rate. Measured from 20% to 80% 0.75

of V_DD. C_LOAD= 15 pF. See Figure 10.

V/ns

ps

Output Clock Edge Rate. Measured from 80% to 20% 0.75

of V_DD. C_LOAD= 15 pF See Figure 10.

–

Period Jitter; VDD1 = VDD2 = 3.3V, drive strength =

‘10’

–

T₁₀

PLL Lock Time

From end of serial programming sequence to correct

output frequency

5

ms

f_XO

VCXO Crystal Pull Range Using non-SMD-49 crystal specified in Table 2.

Nominal Crystal Frequency Input assumed (0 ppm)

@ 25°C and 3.3V

±110 ±120

–

ppm

Using SMD-49 crystal specified in Table 2. Nominal ±105 ±120

Crystal Frequency Input assumed (0 ppm) @ 25°C

and 3.3V

–

ppm

Notes

7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.

8. Drive strength settings: ‘10’ for 3.3V outputs; ‘11’ for 2.5V outputs.

9. Guaranteed when values in Table 3 and Table 9 are programmed to match the output supply voltage.

Document #: 001-09608 Rev. *A

Page 12 of 15

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Test and Measurement Set-up

Figure 8. Test and Measurement Diagram

V_DDs

Outputs

C_LOAD

DUT

GND

0.1F

Voltage and Timing Definitions

Figure 9. Duty Cycle Definition

t₁

t₂

V_DD

50% of V_DD

0V

Clock

Output

Figure 10. ER = (0.6 V_DD)/t₃, EF = (0.6 V_DD)/t₄

t₃t₄

V_DD

80% of V_DD

20% of V_DD

0V

Clock

Output

Document #: 001-09608 Rev. *A

Page 13 of 15

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Ordering Information

Part Number

Lead-free

Type

Production Flow

CY24488ZXC

16-pin TSSOP

16-pin TSSOP - Tape and Reel

Commercial, 0°C to +70°C

CY24488ZXCT

Package Drawing and Dimensions

Figure 11. 16-lead TSSOP 4.40 mm Body Z16.173

51-85091-*A

All product and company names mentioned in this document are trademarks of their respective holders.

Document #: 001-09608 Rev. *A

Page 14 of 15

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Document History Page

Document Title: CY24488 Quad PLL Clock Generator with Serial Interface (I²C) (Final)

Document Number: 001-09608

Orig. of

Change

REV.

ECN NO.

Issue Date

Description of Change

**

497098

504259

See ECN

RGL

New data sheet

*A

RGL

Minor text additions

Change status from Advance Information to Final

Document #: 001-09608 Rev. *A

Page 15 of 15

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型号：	CY24488
厂家：	CYPRESS
描述：	Quad PLL Clock Generator with Serial Interface (I2C) 四PLL时钟发生器，串行接口（ I2C ）时钟发生器
文件：	总15页 (文件大小：289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY24488 [CYPRESS]

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