CY24C08-SXI [CYPRESS]
EEPROM, 8KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8;
| 型号： | CY24C08-SXI |
| 厂家： | 
CYPRESS |
| 描述： | EEPROM, 8KX8, Serial, CMOS, PDSO8, LEAD FREE, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总16页 (文件大小：571K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY24C01/02/04/08/16
1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8)
Two Wire (I2C) Serial EEPROM
■ High reliability
❐ Endurance: 1 million write cycles
❐ Data retention: 100 years
Features
■ Continuous voltage operation
❐ VCC = 1.65V to 5.5V
■ Industrial temperature range
■ Internally organized as 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),
1024 x 8 (8K), or 2048 x 8 (16K)
■ 8-Pin SOIC and 8-Pin TSSOP packages
■ Pb-free and RoHS compliant
■ Industry standard two wire serial interface
■ Schmitt trigger, filtered inputs for noise suppression
■ Bidirectional data transfer protocol
Functional Description
The CY24C01/02/04/08/16 range of products provide 1K, 2K,
4K, 8K, and 16K bits of serial Electrically Erasable and Program-
mable Read Only Memory (EEPROM) organized as 128, 256,
512, 1024, and 2048 words of eight bits each. The device is
optimized for use in many industrial applications where low
power and low voltage operations are essential. The
CY24C01/02/04/08/16 is available in space saving 8-Pin SOIC
and 8-Pin TSSOP packages and is accessed through a two-wire
serial interface. In addition, the entire family is available in 1.65V
(1.65V to 5.5V) version.
■ 1 MHz (2.5V - 5.5V), 400 KHz (1.65V - 5.5V), and 100 KHz
(1.65V - 5.5V) compatibility
■ Write protect pin for hardware data protection
■ 16-byte page write mode
■ Partial page writes enabled
■ Self timed write cycle (5 ms max)
Logic Block Diagram
V
CC
SCL
SDA
CY24C01/02/04/08/16
A0–A2
WP
V
SS
Cypress Semiconductor Corporation
Document #: 001-15632 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 05, 2009
[+] Feedback
CY24C01/02/04/08/16
Pinouts
Figure 1. Pin Diagram - 8-Pin SOIC/TSSOP Package
A0
A1
A2
1
2
VCC
WP
8
7
6
5
Top View
SCL
SDA
3
4
(not to scale)
V
SS
Table 1. Pin Definitions - 8-Pin SOIC/TSSOP Package
Pin
Name
8-SOIC/TSSOP
Pin Number
I/O Type
Description
A0–A2
1,2,3
Input
Device Address Pins. The CY24C01 and CY24C02 uses the A2, A1, and A0
inputs for hard wire addressing and a total of eight 1K and 2K devices may be
addressed on a single bus system.
The CY24C04 uses the A2 and A1 inputs for hard wire addressing and a total of
four 4K devices may be addressed on a single bus system. The A0 pin is a no
connect.
The CY24C08 uses only the A2 input for hardwire addressing and a total of two
8K devices may be addressed on a single bus system. The A0 and A1 pins are
no connects.
The CY24C16 does not use the device address pins which limit the number of
devices on a single bus to one. The A0, A1, and A2 pins are no connects.
VSS
4
5
Ground
Ground. The ground for the device. It must be connected to the ground of the
system.
SDA
Input/Output Serial Data. The SDA pin is bidirectional for serial data transfer. This pin is open
drain driven and is wired-ORed with any number of other open drain or open
collector devices.
SCL
WP
6
7
Input
Serial Clock. The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
Input
Write Protect. The CY24C01/02/04/08/16 has a write protect pin that provides
hardware data protection. The write protect pin allows normal read and write
operations when connected to ground (GND). When the write protect pin is
connected to VCC, the write protection feature is enabled and operates as shown
in Table 2 on page 3.
VCC
8
Power Supply Power Supply. The power supply inputs to the device.
Document #: 001-15632 Rev. *C
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CY24C01/02/04/08/16
Stop Condition
Memory Organization
A low to high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command places the EEPROM
in a standby power mode (see Figure 2).
CY24C01
Internally organized with eight pages of 16 bytes each, the 1K
requires a 7-bit data word address for random word addressing.
Acknowledge
CY24C02
All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM acknowledges each
word received by sending a zero during the ninth clock cycle.
Internally organized with 16 pages of 16-bytes each, the 2K
requires a 8-bit data word address for random word addressing.
Standby Mode
CY24C04
The CY24C01/02/04/08/16 features a low power standby mode,
which is enabled on power up, after the receipt of the STOP bit
and the completion of any internal operations.
Internally organized with 32 pages of 16 bytes each, the 4K
requires a 9-bit data word address for random word addressing.
CY24C08
Device Internal Reset
Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10-bit data word address for random word addressing.
To prevent inadvertent write operations during power up, a
Power On Reset (POR) circuit is included. During power up
(continuous rise of VCC), the device does not respond to any
instruction until the VCC reaches the POR threshold voltage (this
threshold is lower than the VCC minimum operating voltage
defined in DC Electrical Characteristics on page 8). When VCC
has passed over the POR threshold, the device is reset and is in
standby power mode. During power down (continuous decay of
VCC), when VCC drops from the normal operating voltage to
below the POR threshold voltage, the device stops responding
to any instruction sent to it. Before selecting and issuing instruc-
tions to the memory, a valid and stable VCC voltage must be
applied. This voltage must remain stable and valid until the end
of the transmission of the instruction and, for a write instruction,
until the completion of the internal write cycle (tWR).
CY24C16
Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word
addressing.
Device Operating Features
Clock and Data Transitions
The SDA pin is normally pulled high with an external device. Data
on the SDA pin changes only during SCL low time periods. Data
changes during SCL high periods indicate a start or stop
condition as defined in the following section.
Memory Reset
Start Condition
After an interruption in protocol, power loss, or system reset, any
two-wire part is reset with the following steps:
A high to low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 2).
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
Table 2. Write Protect
WP Pin Status
Part of the Memory Protected
CY24C01
CY24C02
CY24C04
CY24C08
CY24C16
VCC
VSS
Full 1K Array
Full 2K Array
Full 4K Array
Full 8K Array
Full 16K Array
Normal Read/Write Operations
Figure 2. Start/Stop Definition
S C L
S D A
S T A R T B IT
S T O P B IT
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CY24C01/02/04/08/16
Figure 3. Acknowledge Timing
SCL
Data In
9
1
8
Data Out
Start
Acknowledge
Device Addressing
Write Operations
The CY24C01/02/04/08/16 EEPROM requires an 8-bit device
address word after a start condition, to enable the chip for a read
or write operation (refer to Table 3 on page 5).
Byte Write
A write operation requires an 8-bit data word address following
the device address word and acknowledgment. On receipt of this
address, the EEPROM responds with a zero and then clocks in
the first 8-bit data word. Following the receipt of the 8-bit data
word, the EEPROM outputs a zero. The addressing device, such
as a microcontroller, must terminate the write sequence with a
stop condition. At this time the EEPROM enters an internally
timed write cycle, tWR, to the nonvolatile memory. All inputs are
disabled during this write cycle and the EEPROM does not
respond until the write is complete (see Figure 4 on page 6).
The device address word consists of a mandatory one, zero
sequence for the first four most significant bits as shown in
Table 3 on page 5. This is common to all the EEPROM devices.
The next three bits are the A2, A1, and A0 device address bits
for CY24C01 and CY24C02. These three bits must compare to
their corresponding hard wired input pins.
CY24C04 uses only the A2 and A1 device address bits. The third
bit is a memory page address bit. The two device address bits
must compare to their corresponding hard wired input pins. The
A0 pin is no connect.
Page Write
The CY24C01/02/04/08/16/CY24C08/CY24C16 devices are
capable of 16-byte page writes.
CY24C08 only uses the A2 device address bit with the next 2 bits
being for memory page addressing. The A2 bit must compare to
its corresponding hard wired input pin. The A1 and A0 pins are
no connect.
A page write is initiated in the same way as a byte write, but the
microcontroller does not send a stop condition after the first data
word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up
to 15 more data words. The EEPROM responds with a zero after
each data word is received. The microcontroller must terminate
the page write sequence with a stop condition
CY24C16 does not use any device address bits and the 3 bits
are used for memory page addressing. The page addressing bits
on the 4K, 8K, and 16K devices must be considered the most
significant bits of the data word address which follows. The A0,
A1, and A2 pins are no connect.
(see Figure 5 on page 6).
The eighth bit of the device address is the read or write operation
select bit. A read operation is initiated if this bit is high and a write
operation is initiated if this bit is low.
The lower four bits of the data word address are internally
incremented following the receipt of each data word. The higher
data word address bits are not incremented, retaining the
memory page row location. When the internally generated word
address reaches the page boundary, the next byte is placed at
the beginning of the same page. If more than 16 data words are
transmitted to the EEPROM, the data word address rolls over
and the previous data is overwritten.
When the device address is compared, the EEPROM outputs a
zero. If a compare is not made, the chip returns to the standby
state.
Acknowledge Polling
When the internally timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling is initiated.
This involves sending a start condition followed by the device
address word. The read or write bit is representative of the
operation desired. After the internal write cycle is complete, the
EEPROM responds with a zero, enabling the read or write
sequence to continue.
Document #: 001-15632 Rev. *C
Page 4 of 16
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CY24C01/02/04/08/16
Random Read
Read Operations
A random read needs a ‘dummy’ byte write sequence to load in
the data word address. After the device address word and data
word address are clocked in and acknowledged by the
EEPROM, the microcontroller must generate another start
condition. The microcontroller initiates a current address read by
sending a device address with the read or write select bit high.
The EEPROM acknowledges the device address and serially
clocks out the data word. The microcontroller does not respond
with a zero but generates a stop condition as shown in
Figure 7 on page 6.
Read operations are initiated in the same way as write opera-
tions except that the read or write select bit in the device address
word is set to one. There are three read operations: current
address read, random address read, and sequential read.
Current Address Read
The internal data word address counter maintains the last
address accessed during the last read or write operation, incre-
mented by one. This address stays valid between operations as
long as the chip power is maintained. The address roll over
during read and byte write is from the last byte of the last memory
page to the first byte of the first page. The address roll over
during write is from the last byte of the current page to the first
byte of the same page. After the device address with the read or
write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but
generates a stop condition (see Figure 6 on page 6).
Sequential Read
Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data
word, it responds with an acknowledgement. As long as the
EEPROM receives an acknowledgement, it continues to
increment the data word address and serially clocks out
sequential data words. When the address memory limit is
reached, the data word address rolls over and the sequential
read continues. The sequential read operation is terminated
when the microcontroller does not respond with a zero but
generates a stop condition (see Figure 8 on page 7).
Table 3. Device Addressing [1,2,3]
Device Type Identifier
Density
Chip Enable Address
b7
1
b6
0
b5
1
b4
0
b3
A2
A2
A2
P2
b2
A1
A1
P1
P1
b1
A0
P0
P0
P0
b0
1K/2K
4K
R/W
R/W
R/W
R/W
1
0
1
0
8K
1
0
1
0
16K
1
0
1
0
Table 4. Operating Modes
Mode
WP
X
Bytes
Initial Sequence
R/W Bit
Current Address Read
Random Address Read
1
1
1
Start, Device Select, R/W = 1
0
1
1
0
0
X
Start, Device Select, R/W = 0, Address
reStart, Device Select, R/W = 1
X
Sequential Read
Byte Write
X
>1
1
Similar to Current or Random Address Read
Start, Device Select, R/W = 0
0
Page Write
0
<16
Start, Device Select, R/W = 0
Notes
1. P2, P1, P0 are used for memory page addressing.
2. A2, A1 and A0 are compared against the respective external pins on the memory device.
3. The MSB b7 is sent first.
Document #: 001-15632 Rev. *C
Page 5 of 16
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CY24C01/02/04/08/16
Figure 4. Byte Write Timing [4]
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
T
O
P
S
P
SDA Line
A
C
K
A
C
K
A
C
K
Figure 5. Page Write Timing
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS (n)
T
DATA n+1
DATA n+P
DATA n
O
P
P
S
SDA Line
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 6. Current Address Read Timing
S
T
A
R
T
S
SLAVE
ADDRESS
T
DATA
O
P
P
S
SDA Line
N
O
A
C
K
A
C
K
Figure 7. Random Address Read Timing
S
T
A
R
T
S
T
A
R
T
S
SLAVE
ADDRESS
BYTE
ADDRESS
SLAVE
ADDRESS
T
DATA n
O
P
S
S
P
SDA Line
N
O
A
C
K
A
C
K
A
C
K
Dummy Write
A
C
K
Note
4. P = 15 for CY24C04/08/16.
Document #: 001-15632 Rev. *C
Page 6 of 16
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CY24C01/02/04/08/16
Figure 8. Sequential Read Timing
S
T
SLAVE
ADDRESS
O
DATA n
DATA n+1
DATA n+2
DATA n+x
P
P
SDA Line
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
Document #: 001-15632 Rev. *C
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CY24C01/02/04/08/16
Package power dissipation
capability (TA = 25°C).................................................... 1.0W
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface mount lead soldering
temperature (3 Seconds)...................+260°C for 10 seconds
Output short circuit current[5]....................................... 50 mA
Storage temperature .................................. –65°C to +150°C
Ambient temperature with
power applied............................................. –55°C to +125°C
Static discharge voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Supply voltage on VCC relative to GND..........–1.0V to +6.0V
Latch up current .................................................... > 200 mA
DC voltage applied to outputs
in high-Z state........................................ –0.5V to VCC + 1.0V
Operating Range
Range
Ambient Temperature
VCC
Input voltage.......................................... –0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
1.65V to 5.5V
Transient voltage (<20 ns) on
any pin to ground potential.................... –1.0V to VCC + 2.0V
DC Electrical Characteristics
Over the Operating Range (VCC = 1.65V to 5.5V)
Parameter
VCC
Description
Supply Voltage
Test Conditions
Min
Max
Unit
V
1.65
5.5
ISB1
ISB2
ISB3
ICC1
ICC2
ICC3
ILI
Standby Current
VCC = 1.65V, VIN = VSS or VCC
VCC = 2.7V, VIN = VSS or VCC
VCC = 5.5V, VIN = VSS or VCC
VCC = 5.5V at 1 MHz
1
μA
μA
μA
mA
mA
mA
μA
μA
V
Standby Current
1.1
Standby Current
1.2
Operating Current (READ)
Operating Current (READ)
Operating Current (Write)
Input Leakage Current
Output Leakage Current
Input LOW Voltage
2
VCC = 5.5V at 400 KHz
VCC = 5.5V
1
2
VIN = VCC or VSS
.
1
1
ILO
VOUT = VCC or VSS
.
VIL
VCC = VCC Min
–0.6 [6]
0.3 VCC
VCC + 0.5 [6]
0.4
VIH
Input HIGH Voltage
Output LOW Voltage
VCC = VCC Max
0.7 VCC
V
VOL
IOL = 3 mA, VCC = 5.5V
OL = 0.15 mA, VCC = 1.8V
V
I
0.2
Note
5. Outputs shorted for only one second. Only one output shorted at a time.
6. This parameter is characterized but not tested.
Document #: 001-15632 Rev. *C
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CY24C01/02/04/08/16
Capacitance
In the following table, the capacitance parameters are listed. [7]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
CC = 1.65V
Max
Unit
CIN
CIO
Input Capacitance
(A0,A1, A2, SCL)
6
pF
V
Input/Output Capaci-
tance (SDA)
8
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [7]
Parameter
Description
Test Conditions
8-SOIC
8-TSSOP
Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard test methods and proce- 120.83
dures for measuring thermal impedance, per EIA /
119.31
°C/W
JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
90.31
82.77
°C/W
Reliability Characteristics
In the following table, the reliability characteristics parameters are listed. [7]
Parameter
NEND
Description
Endurance
Test Method
JEDEC Standard A117
Min
1 Million
100
Unit
Cycles
Years
mA
TDR
Data Rentention
Latch Up
JEDEC Standard A103
JEDEC Standard 78
ILTH
100 + ICC
Figure 9. AC Test Loads and Waveforms
R
VCC
OUTPUT
C
L
Frequency
1 MHz
R (ohm)
1.2K
CL (pF)
30
100 KHz, 400 KHz
2.7K
100
Figure 10. AC Input and Output Reference Waveforms
VIHT
VILT
VHT
VLT
VHT
VLT
OUTPUT
REFERENCE POINTS
INPUT
AC test inputs are driven at VIHT (0.9 VCC) for a logic ‘1’ and VILT (0.1 VCC) for a logic ‘0’. Measurement reference points for inputs
and outputs are VLT (VCC/2 - 0.1V) and VHT (VCC/2 + 0.1V). Input rise and fall times (10%–90%) are <100 ns.
Note
7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Document #: 001-15632 Rev. *C
Page 9 of 16
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CY24C01/02/04/08/16
AC Switching Characteristics
400 KHz
100 KHz
1 MHz
Cypress
Parameter
Alt
Parameter
(2.5V - 5.5V)
(1.65V - 5.5V)
(1.65V - 5.5V)
Description
Unit
Min
Max
Min
Max
Min
Max
fSCL
fSCL
Clock Frequency, SCL
1000
400
100
KHz
μs
μs
μs
ns
μs
μs
ns
μs
ns
μs
ns
ns
ms
μs
tCL
tLOW
tHIGH
tAA
Clock Pulse Width Low
Clock Pulse Width High
Clock Low To Data Out Valid
Noise Suppression Time
Start Setup Time
0.4
0.4
0.6
0.6
4
4
tCH
tAA
0.4
25
0.9
50
4.5
50
tI
tI
tS.STA
tH.STA
tSD
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tDH
0.25
0.25
100
0
0.6
0.6
100
0
4
4
Start Hold Time
Data In Setup Time
Data In Hold Time
Data Out Hold Time
Stop Setup Time
200
0
tHD
tDOH
tS.STO
tR
50
50
100
4
tSU.STO
tR
0.25
0.6
Inputs Rise Time
100
100
5
250
250
5
1000
1000
5
tF
tF
Inputs Fall Time
tWC
tWR
Write Cycle Time
[6]
tBUF
tBUF
Bus Free Time for New Data Transmission 0.5
1.3
4.7
Figure 11. Bus Timing
tF
tCH
tR
tCL
tCL
SCL
tS.STO
tS.STA
tHD
tH.STA
tSD
SDA In
tBUF
tAA
tDOH
SDA Out
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CY24C01/02/04/08/16
Figure 12. Write Timing
SCL
SDA
ACK
8TH BIT
BYTE N
tWR
ADDRESS
STOP
CONDITION
START
CONDITION
Part Numbering Nomenclature
CY24 C 01 - SX
I T
Option:
T = Tape & Reel
Blank = Std.
Temperature:
I = Industrial (–40 to 85°C)
X = Pb-Free
Package:
S = SOIC
Z = TSSOP
Density:
01 = 1 Kb
02 = 2 Kb
04 = 4 Kb
08 = 8 Kb
16 = 16 Kb
Voltage:
C = 1.65V - 5.5V
24 = I2C Interface
Cypress
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Page 11 of 16
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CY24C01/02/04/08/16
Ordering Information
Package
Diagram
Operating
Range
Density
Ordering Code
Package Type
8-Pin SOIC
1 Kbit
CY24C01-SXI
CY24C01-SXIT
CY24C01-ZXI
CY24C01-ZXIT
CY24C02-SXI
CY24C02-SXIT
CY24C02-ZXI
CY24C02-ZXIT
CY24C04-SXI
CY24C04-SXIT
CY24C04-ZXI
CY24C04-ZXIT
CY24C08-SXI
CY24C08-SXIT
CY24C08-ZXI
CY24C08-ZXIT
CY24C16-SXI
CY24C16-SXIT
CY24C16-ZXI
CY24C16-ZXIT
51-85066
51-85093
51-85066
51-85093
51-85066
51-85093
51-85066
51-85093
51-85066
51-85093
Industrial
Industrial
Industrial
Industrial
Industrial
8-Pin SOIC (Tape & Reel)
8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
8-Pin SOIC
2 Kbit
4 Kbit
8 Kbit
16 Kbit
8-Pin SOIC (Tape & Reel)
8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
8-Pin SOIC
8-Pin SOIC (Tape & Reel)
8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
8-Pin SOIC
8-Pin SOIC (Tape & Reel)
8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
8-Pin SOIC
8-Pin SOIC (Tape & Reel)
8-Pin TSSOP
8-Pin TSSOP (Tape & Reel)
Above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-15632 Rev. *C
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CY24C01/02/04/08/16
Package Diagrams
Figure 13. 8-Pin (150-Mil) SOIC, 51-85066
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 001-15632 Rev. *C
Page 13 of 16
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CY24C01/02/04/08/16
Package Diagrams (continued)
Figure 14. 8-Pin (4.4 mm) TSSOP, 51-85093
51-85093-*A
Document #: 001-15632 Rev. *C
Page 14 of 16
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CY24C01/02/04/08/16
Document History Page
Document Title: CY24C01/02/04/08/16, 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, and 16 Kbit (x8) Two Wire (I2C) Serial EEPROM
Document Number: 001-15632
Revision ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
1069220
UHA
See ECN
06/27/08
New Data Sheet
*A
2522135 GVCH/PYRS
Added Pb-Free and RoHS Compliant information in “Features”
Removed PDIP Package
Removed Automotive Temperature range
Updated Figure 4.
Changed Memory page addressing naming convention from A10,A9,A8 to
P2,P1,P0
Changed Supply voltage on VCC relative to GND max value from 5.0V to 6.0V
Corrected Typo of Vcc max value from 5.0V to 5.5V
Added ICC1 spec for 1 MHz
Table 8: Added Thermal Resistance values for 8-TSSOP package
Added AC test load values for different Frequency
Table 10: Added tl (Noise suppression time) value for 1 MHz and 100 KHz
Frequency
Updated Part Numbering Nomenclature and Ordering Information
*B
*C
2611873
2656511
VKN/PYRS
VKN/PYRS
11/24/08
02/09/09
Added 1 Kbit and 2 Kbit parts and their related information
Converted from preliminary to final
Changed VCC operating range for 1MHz operation from 1.65V-5.5V to 2.5V-5.5V
Changed ICC3 spec from 1.5mA to 2mA
Added footnote #6
Updated VOL test conditions
On page 9, corrected AC measurement reference points from VIT and VOT to VLT
and VHT respectively
Changed VLT level from 0.3VCC to VCC/2 - 0.1V
Changed VHT level from 0.7VCC to VCC/2 + 0.1V
Document #: 001-15632 Rev. *C
Page 15 of 16
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CY24C01/02/04/08/16
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Document #: 001-15632 Rev. *C
Revised February 05, 2009
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