CY25402SXI-XXXT [CYPRESS]
Two PLL Programmable Clock Generator with Spread Spectrum; 两个PLL可编程时钟发生器，带有扩频
| 型号： | CY25402SXI-XXXT |
| 厂家： | 
CYPRESS |
| 描述： | Two PLL Programmable Clock Generator with Spread Spectrum |
| 文件： | 总10页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25402/CY25422/CY25482
Two PLL Programmable Clock Generator
with Spread Spectrum
■ Three clock outputs with Programmable drive strength
■ Glitch-free outputs while frequency switching
■ 8-pin SOIC package
Features
■ Two fully integrated phase locked loops (PLLs)
■ Input frequency range
■ Commercial and Industrial temperature ranges
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
Benefits
■ Reference Clock input voltage range
❐ 2.5V, 3.0V, and 3.3V for CY25482
❐ 1.8V for CY25402 and CY25422
■ Multiple high performance PLLs allow synthesis of unrelated
frequencies
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Nonvolatile programming for personalization of PLL
frequencies,spreadspectrumcharacteristics,drivestrength,
crystal load capacitance, and output frequencies
■ Programmable Spread Spectrum with Center and Down
Spread option and Lexmark and Linear modulation profiles
■ Application specific Programmable EMI reduction using
Spread Spectrum for clocks
■ VDD supply voltage options:
❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482
❐ 1.8V for CY25422
■ Programmable PLLs for system frequency margin tests
■ Meets critical timing requirements in complex system
designs
■ Selectable output clock voltages independent of VDD:
❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482
❐ 1.8V for CY25422
■ Suitability for PC, consumer, portable, and networking appli-
cations
■ Frequency Select feature with option to select four different
frequencies
■ Capable of Zero PPM frequency synthesis error
■ Uninterrupted system operation during clock frequency
■ Power Down, Output Enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
switch
■ Application compatibility in standard and low power systems
■ Ability to synthesize nonstandard frequencies with
Fractional-N capability
Block Diagram
Crossbar
XIN/
CLK1
Output
Switch
EXCLKIN
PLL 1
(SS)
OSC
Dividers
and
XOUT
MUX
and
REFOUT
CLK2
Drive
PLL 2
(SS)
Control
Logic
Strength
Control
FS0
FS1
SSON
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12565 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2007
[+] Feedback
CY25402/CY25422/CY25482
Table 1. Device Selector Guide
Device
CY25402
CY25482
CY25422
Crystal Input
EXCKLKIN Input
VDD
Yes
No
1.8V LVCMOS
2.5V, 3.0V, 3.3V
2.5V, 3.0V, 3.3V LVCMOS
1.8V LVCMOS
2.5V, 3.0V, 3.3V
1.8V
Yes
Figure 1. Pin Diagram - CY25402 8-LD SOIC
XIN/
EXCLKIN
XOUT
8
1
VDD
GND
7
6
5
2
3
4
CY25402
CLK1
CLK2/SSON
PD#/OE/FS1
REFOUT/
FS0
Table 1. Pin Definition - CY25402 (2.5V, 3.0V or 3.3V Supply)
Pin Number
Name
IO
Description
1
XIN/EXCLKIN Input
Crystal Input or 1.8V External Clock Input
Power Supply: 2.5V, 3.0V or 3.3V
2
3
4
5
VDD
Power
Output
CLK1
Programmable Clock Output with Spread Spectrum
REFOUT/FS0 Output/Input
PD#/OE/FS1 Input
Multifunction Programmable pin: Reference Clock Output or Frequency Select pin
Multifunction Programmable pin: Power Down, Output Enable or Frequency Select
pin
6
CLK2/SSON
Output/Input
Multifunction Programmable pin: Programmable Clock Output with Spread
Spectrum or Spread Spectrum ON/OFF control pin
7
8
GND
Power
Output
Power Supply Ground
Crystal Output
XOUT
Document #: 001-12565 Rev. *B
Page 2 of 10
[+] Feedback
CY25402/CY25422/CY25482
Figure 2. Pin Diagram - CY25482 8-LD SOIC
EXCLKIN
VDD
DNU
GND
8
1
7
6
5
2
3
4
CY25482
CLK1
CLK2/SSON
PD#/OE/FS1
REFOUT/
FS0
Table 2. Pin Definition - CY25482 (2.5V, 3.0V or 3.3V Supply)
Pin Number
Name
EXCLKIN
VDD
IO
Description
1
Input
2.5V, 3.0V or 3.3V External Clock Input
2
3
4
5
Power
Power Supply: 2.5V, 3.0V or 3.3V
CLK1
Output
Programmable Clock Output with Spread Spectrum
Multifunction Programmable pin: Reference Clock Output or Frequency Select pin
REFOUT/FS0 Output/Input
PD#/OE/FS1 Input
Multifunction Programmable pin: Power Down, Output Enable or Frequency Select
pin
6
CLK2/SSON
Output/Input
Multifunction Programmable pin: Programmable Clock Output with Spread
Spectrum or Spread Spectrum ON/OFF control pin
7
8
GND
DNU
Power
Output
Power Supply Ground
Do not use this pin
Figure 3. Pin Diagram - CY25422 8-LD SOIC
XIN/
EXCLKIN
XOUT
8
1
VDD
GND
7
6
5
2
3
4
CY25422
CLK1
CLK2/SSON
PD#/OE/FS1
REFOUT/
FS0
Table 3. Pin Definition - CY25422 (1.8V Supply)
Pin Number
Name
IO
Description
1
XIN/EXCLKIN Input
Crystal Input or 1.8V External Clock Input
2
3
4
5
VDD
Power
Output
Power Supply: 1.8V
CLK1
Programmable Clock Output with Spread Spectrum
Multifunction Programmable pin: Reference Clock Output or Frequency Select pin
REFOUT/FS0 Output/Input
PD#/OE/FS1
Input
Multifunction Programmable pin: Power Down, Output Enable or Frequency Select
pin
6
CLK2/SSON
Output/Input
Multifunction Programmable pin: Programmable Clock Output with Spread
Spectrum or Spread Spectrum ON/OFF control pin
7
8
GND
Power
Output
Power Supply Ground
Crystal Output
XOUT
Document #: 001-12565 Rev. *B
Page 3 of 10
[+] Feedback
CY25402/CY25422/CY25482
General Description
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
2 Configurable PLLs
The CY25402, CY25482 and CY25422 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is that a
single device generates two independent frequencies from a
single crystal.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables uninter-
rupted system operation while clock frequency is being switched.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5V/3.0V/3.3V while that for CY25402 and CY25422 is 1.8V.
This gives user an option for this device to be compatible for
different input clock voltage levels in the system.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
VDD Power Supply Options
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5V, 3.0V, or 3.3V while
CY25422 is a low voltage part that can operate at 1.8V.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 shows the typical rise
and fall times for different drive strength settings.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two independent clock outputs.
Table 4. Output Drive Strength
Rise/Fall Time (ns)
Output Drive Strength
(Typical Value)
Low
Mid Low
Mid High
High
6.8
3.4
2.0
1.0
Spread Spectrum Control
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress propri-
etary PLL and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with Lexmark or Linear profile.
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25482 and CY25422 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
Field Application Engineer (FAE) or sales representative.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
Document #: 001-12565 Rev. *B
Page 4 of 10
[+] Feedback
CY25402/CY25422/CY25482
Absolute Maximum Conditions
Parameter
VDD
Description
Supply Voltage for CY25402/CY25482
Supply Voltage for CY25422
Input Voltage for CY25402/CY25482
Input Voltage for CY25422
Temperature, Storage
Condition
Min
–0.5
–0.5
Max
4.5
Unit
V
VDD
2.6
V
VIN
Relative to VSS
–0.5 VDD+0.5
V
VIN
Relative to VSS
–0.5
–65
2.2
V
TS
Non Functional
+150
°C
ESDHBM
UL-94
MSL
ESD Protection (Human Body Model)
Flammability Rating
JEDEC EIA/JESD22-A114-E
V-0 @1/8 in.
2000
Volts
ppm
10
SOIC package
Moisture Sensitivity Level
3
Recommended Operating Conditions
Parameter
Description
VDD Operating Voltage for CY25402/CY25482
Min
2.25
1.65
0
Typ
–
Max
3.60
1.95
+70
+85
15
Unit
V
V
DD
VDD
VDD Operating Voltage for CY25422
Commercial Ambient Temperature
Industrial Ambient Temperature
Maximum Load Capacitance
1.8
–
V
T
°C
°C
pF
ms
AC
T
–40
–
--
AI
C
–
LOAD
t
Power up time for all V to reach minimum specified voltage (power ramps 0.05
–
500
PU
DD
must be monotonic)
Document #: 001-12565 Rev. *B
Page 5 of 10
[+] Feedback
CY25402/CY25422/CY25482
DC Electrical Specifications
Parameter
Description
Output Low Voltage
Conditions
Min
Typ
Max
Unit
V
IOL = 2 mA, drive strength = [00]
IOL = 3 mA, drive strength = [01]
–
–
0.4
V
OL
OH
IL1
I
OL = 7 mA, drive strength = [10]
OL = 12 mA, drive strength = [11]
I
V
Output High Voltage
IOH = –2 mA, drive strength = [00]
VDD – 0.4
–
–
V
I
OH = –3 mA, drive strength = [01]
OH = –7 mA, drive strength = [10]
I
IOH = –12 mA, drive strength = [11]
V
Input Low Voltage of PD#/OE, FS0,
FS1 and SSON
–
–
0.2*VDD
V
V
V
Input Low Voltage of EXCLKIN
–
–
–
0.18
–
V
V
IL2
Input High Voltage of PD#/OE, FS0,
FS1 and SSON
0.8*VDD
IH1
V
V
Input High Voltage of EXCLKIN for
CY25402/CY25422
1.62
–
–
2.2
–
V
V
IH2
IH3
Input High Voltage of EXCLKIN for
CY25482
0.8*VDD
IIL
Input Low Current, PD#/OE/FS1
Input High Current, PD#/OE/FS1
VIN = 0V
–
–
–
–
–
–
10
10
10
µA
µA
µA
IIH
VIN = VDD
IILDN
Input Low Current, SSON and FS0 pins VIN = 0V (Internal pull down resistor
= 160k typ.)
IIHDN
RDN
Input High Current, SSON and FS0
pins
VIN = VDD (Internal pull down
resistor = 160k typ.)
14
–
36
µA
Pull Down Resistor of CLK1,
REFOUT/FS0 and CLK2/SSON pins PD# = Low
Output clocks in off state by setting
100
160
250
kΩ
[1,2]
I
Supply Current for CY25422
PD# = High, No load
–
–
–
–
12
14
3
–
–
–
7
mA
mA
µA
pF
DD
Supply Current for CY25402/CY25482 PD# = High, No load
[1]
I
Standby Current
PD# = Low
DDS
[1]
C
Input Capacitance
SSON, PD#/OE/FS1 and FS0 pins
–
IN
Notes
1. Guaranteed by design but not 100% tested
2. Configuration dependent
Document #: 001-12565 Rev. *B
Page 6 of 10
[+] Feedback
CY25402/CY25422/CY25482
AC Electrical Specifications
Parameter
Description
Conditions
Min
8
Typ Max Unit
F
F
(crystal) Crystal Frequency, XIN
–
–
48
MHz
IN
IN
(clock)
Input Clock Frequency
(EXCLKIN)
8
166 MHz
F
Output Clock Frequency
3
–
166 MHz
CLK
DC
Output Duty Cycle, All
Clocks except Ref Out
Duty Cycle is defined in Figure 5 on page 8; t /t , measured
45
50
55
%
1
2
at 50% of V
DD
DC
Ref Out Duty Cycle
Ref In Min 45%, Max 55%
40
–
–
60
–
%
[1]
TRF1
Output Rise/Fall Time
Measured from 20% to 80% of VDD, as shown in Figure 6
on page 8, CLOAD = 15 pF, drive strength [00]
6.8
ns
[1]
TRF2
TRF3
TRF4
TCCJ
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Measured from 20% to 80% of VDD, as shown in Figure 6
on page 8, CLOAD = 15 pF, drive strength [01]
–
–
–
–
–
3.4
2.0
1.0
100
1
–
–
–
–
3
ns
ns
ns
ps
ms
[1]
Measured from 20% to 80% of VDD, as shown in Figure 6
on page 8, CLOAD = 15 pF, drive strength [10]
[1]
Measured from 20% to 80% of VDD, as shown in Figure 6
on page 8, CLOAD = 15 pF, drive strength [11]
[1,2]
[1]
Cycle-to-cycle Jitter
(peak)
Configuration dependent. See Table 5
TLOCK
PLL Lock Time
Measured from 90% of the applied power supply level
Table 5. Configuration Example for C-C Jitter
CLK1 Output
CLK2 Output
Ref. Frequency
C-C Jitter Typ
C-C Jitter Typ
(MHz)
Freq. (MHz)
Freq. (MHz)
(ps)
134
99
(ps)
14.3181
19.2
27
8.0
74.25
48
48
8
92
91
67
166
166
103
137
48
48
93
Recommended Crystal Specification for SMD Package
Parameter
Fmin
Description
Range 1 Range 2 Range 3
Unit
Minimum Frequency
8
14
135
4
14
28
50
4
28
48
30
2
MHz
MHz
Ω
Fmax
R1
Maximum Frequency
Motional Resistance (ESR)
Shunt Capacitance
C0
pF
CL
Parallel Load Capacitance
Maximum Crystal Drive Level
18
300
14
300
12
300
pF
DL(max)
µW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Fmin
Description
Range 1 Range 2 Range 3
Unit
MHz
MHz
Ω
Minimum Frequency
8
14
14
24
24
32
Fmax
R1
Maximum Frequency
Motional Resistance (ESR)
Shunt Capacitance
90
50
30
C0
7
7
7
pF
CL
Parallel Load Capacitance
Maximum Crystal Drive Level
18
12
12
pF
DL(max)
1000
1000
1000
µW
Document #: 001-12565 Rev. *B
Page 7 of 10
[+] Feedback
CY25402/CY25422/CY25482
Test and Measurement Setup
Figure 4. Test and Measurement Setup
VDD
Outputs
0.1 μF
CLOAD
DUT
GND
Voltage and Timing Definitions
Figure 5. Duty Cycle Definition
t1
t2
VDD
50% of VDD
0V
Clock
Output
Figure 6. Rise Time = TRF, Fall Time = TRF
T
T
RF
RF
VDD
80% of VDD
20% of VDD
0V
Clock
Output
Document #: 001-12565 Rev. *B
Page 8 of 10
[+] Feedback
CY25402/CY25422/CY25482
Ordering Information
Part Number[3]
Type
VDD(V)
Production Flow
Pb-free
CY25402SXC-xxx
CY25402SXC-xxxT 8-pin SOIC -Tape & Reel
CY25482SXC-xxx 8-pin SOIC
CY25482SXC-xxxT 8-pin SOIC -Tape & Reel
CY25422SXC-xxx 8-pin SOIC
CY25422SXC-xxxT 8-pin SOIC -Tape & Reel
8-pin SOIC
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 1.8V
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Supply Voltage: 1.8V
CY25402SXI-xxx
CY25402SXI-xxxT
CY25482SXI-xxx
CY25482SXI-xxxT
CY25422SXI-xxx
CY25422SXI-xxxT
8-pin SOIC
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 2.5V, 3.0V or 3.3V
Supply Voltage: 1.8V
8-pin SOIC -Tape & Reel
8-pin SOIC
8-pin SOIC -Tape & Reel
8-pin SOIC
8-pin SOIC -Tape & Reel
Supply Voltage: 1.8V
Package Drawing and Dimensions
Figure 7. 8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
Note
3. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document #: 001-12565 Rev. *B
Page 9 of 10
[+] Feedback
CY25402/CY25422/CY25482
Document History Page
Document Title: CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-12565
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
690296
815788
1428744
See ECN
See ECN
RGL
RGL
New Data Sheet
Minor Change: To post on web
*A
*B
See ECN RGL/AESA Changed data sheet format to match generic part, CY2544/46
Added new device and specification for high ref. input voltage part, CY25482
Removed Preliminary from Title page
Replaced CLK2 with REFOUT
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-12565 Rev. *B
Revised November 13, 2007
Page 10 of 10
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
相关型号：
©2020 ICPDF网 联系我们和版权申明