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CY26187-2 [CYPRESS]

Broadcom Reference Design Clock Generator; Broadcom的参考设计时钟发生器
CY26187-2
型号： CY26187-2
厂家： CYPRESS    CYPRESS
描述：

Broadcom Reference Design Clock Generator
Broadcom的参考设计时钟发生器

时钟发生器
文件： 总6页 (文件大小：175K)
中文：  中文翻译
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THIS SPEC IS OBSOLETE  
Spec No: 38-07131  
Spec Title: CY26187-2 Broadcom Reference Design Clock  
Generator  
Sunset Owner: RGL  
Replaced by: NA  
1CY2295  
CY26187-2  
Broadcom Reference Design  
Clock Generator  
Features  
• Integrated phase-locked loop  
• Low skew, low jitter, high accuracy outputs  
• 3.3V Operation  
Benefits  
Highest Performance PLL tailored for multimedia applications  
Meets critical timing requirements in complex system designs  
Broadcom Reference  
Part Number  
CY26187-2  
Outputs  
Design  
Input Frequency  
50 MHz  
Output Frequencies  
1 copy of 142.8 MHz (3.3V)  
1
BCM5680_5404  
Logic Block Diagram  
OUTPUT  
MULTIPLEXER  
AND  
P Comp  
Q
50 XIN  
OSC  
XOUT  
DIVIDERS  
142.8 MHz  
VCO  
P
PLL  
OE  
VSS  
VSS  
VDD VDD  
Pin Configuration  
CY26187  
8-pin SOIC  
8
XOUT  
VSS  
142.8 MHz  
1
XIN  
AVDD  
OE  
7
6
5
2
3
4
AVSS  
VDD  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-07131 Rev. OBS  
Revised December 02, 2004  
CY26187-2  
Summary  
Name  
Pin Number  
1
Description  
XIN[1]  
Reference Crystal Input  
Analog Voltage Supply  
Output enable (0-off; 1-on)  
Ground  
Voltage Supply  
142.8-MHz clock output  
Ground  
AVDD  
OE  
AVSS  
VDD  
142.8 MHz  
VSS  
XOUT[1]  
2
3
4
5
6
7
8
Reference Crystal Output  
Absolute Maximum Conditions  
Parameter  
VDD  
TS  
TJ  
Description  
Min.  
Max.  
7.0  
125  
125  
VDD + 0.3  
VDD + 0.3  
Unit  
V
°C  
°C  
V
Supply Voltage  
Storage Temperature[2]  
Junction Temperature  
Digital Inputs  
–65  
VSS – 0.3  
VSS – 0.3  
2
Digital Outputs referred to VDD  
Electro-Static Discharge  
V
kV  
Recommended Operating Conditions  
Parameter Description  
VDD Operating Voltage  
Min.  
3.135  
0
Typ.  
3.3  
Max.  
3.465  
70  
15  
Unit  
V
C
pF  
mW  
TA  
CLOAD  
Pmax  
Ambient Temperature  
Max. Load Capacitance  
Max. Output Power Dissipation,  
150  
8-pin package  
fREF  
tPU  
Reference Frequency  
50  
MHz  
ms  
Power-up time for all VDD's to  
reach minimum specified voltage  
(power ramps must be monotonic)  
0.05  
500  
DC Electrical Characteristics  
Parameter  
Name  
Description  
OH = VDD – 0.5, VDD = 3.3V  
OL = 0.5, VDD = 3.3V  
Min.  
12  
12  
Typ.  
24  
24  
Max.  
Unit  
mA  
mA  
pF  
µA  
mA  
Output High Current  
Output Low Current  
Input Capacitance  
Input Leakage Current  
IVDD  
V
V
7
5
3.3V, All outputs @ 10 MHz  
35  
Notes:  
1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal).  
2. Rated for 10 years.  
Document #: 38-07131 Rev. OBS  
Page 2 of 5  
CY26187-2  
(3.)  
AC Electrical Characteristics (VDD = 3.3V)  
Parameter  
Name  
Output Duty Cycle  
Description  
Duty Cycle is defined in Figure 1, 50% of VDD  
Min.  
45  
Typ.  
50  
Max.  
55  
Unit  
%
t3  
t4  
t9  
Rising Edge Slew Rate Output Clock Rise Time, 20%-80% of VDD  
Falling Edge Slew Rate Output Clock Fall Time, 80% to 20% of VDD  
0.8  
0.8  
1.4  
1.4  
V/ns  
V/ns  
ps  
Clock Jitter  
Peak to Peak period jitter  
200  
3
t10  
PLL Lock Time  
ms  
Note:  
3. Not 100% tested.  
Test Circuit  
VDD  
CLK out  
CLOAD  
0.1 µF  
OUTPUTS  
GND  
VDD  
0.1 µF  
CLK  
CLK  
t1  
t2  
50%  
Figure 1. Duty Cycle Definition; DC = t2/t1.  
t3  
t4  
80%  
20%  
Figure 2. Rise and Fall Time Definitions.  
Ordering Information  
Ordering Code  
CY26187SC-2  
Package Name  
S8  
Package Type  
8-Pin SOIC  
Operating Range  
Commercial  
Operating Voltage  
3.3V  
Document #: 38-07131 Rev. OBS  
Page 3 of 5  
CY26187-2  
Package Diagram  
8-Lead (150-Mil) SOIC S8  
51-85066-A  
Document #: 38-07131 Rev. OBS  
Page 4 of 5  
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CY26187-2  
Revision History  
Document Title: CY26187-2 Broadcom Reference Design Clock Generator  
Document Number: 38-07131  
Issue  
Date  
02/19/02  
12/14/02  
See ECN  
Orig. of  
REV.  
**  
*A  
ECN NO.  
110096  
121872  
294822  
Change Description of Change  
CKN  
RBI  
RGL  
New data sheet  
Power up requirements added to Operating Conditions Information  
TO Obsolete the DS  
OBS  
Document #: 38-07131 Rev. OBS  
Page 5 of 5  

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