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CY26200SCT [CYPRESS]

T1/E1 Clock Generator; T1 / E1时钟发生器
CY26200SCT
型号： CY26200SCT
厂家： CYPRESS    CYPRESS
描述：

T1/E1 Clock Generator
T1 / E1时钟发生器

晶体 时钟发生器 微控制器和处理器 外围集成电路 光电二极管
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CY26200  
T1/E1 Clock Generator  
Benefits  
Features  
• High-performance PLL tailored for T1/E1 clock genera-  
tion  
• Meets critical timing requirements in complex system  
designs  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• 3.3V operation  
• Enables application compatibility  
Part Number Outputs  
CY26200  
Input Frequency Range  
19.44 MHz  
Output Frequencies  
1
1.544 MHz/2.048 MHz (selectable)  
Logic Block Diagram  
19.44 XIN  
XOUT  
OSC  
Q
Φ
VCO  
PLL  
OUTPUT  
CLK1  
DIVIDERS  
P
AVSS  
AVDD  
VSS  
VDD  
Pin Configuration  
CY26200  
8-pin SOIC  
Table 1. CY26200 Frequency Select Option  
Frequency Select  
CLK1  
1.544  
2.048  
Unit  
MHz  
MHz  
XOUT  
1
2
3
4
8
7
6
5
XIN  
0
1
VSS  
AVDD  
FS  
CLK1  
AVSS  
VDD  
Cypress Semiconductor Corporation  
Document #: 38-07335 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 3, 2005  
CY26200  
Pin Summary  
Pin Name  
XIN  
Pin Number  
Pin Description  
1
2
3
4
5
6
7
8
19.44-MHz Reference Input  
Analog Voltage Supply  
Frequency Select – see Table 1  
Analog Ground  
AVDD  
FS  
AVSS  
VDD  
Voltage Supply  
CLK1  
1.544-MHz/2.048-MHz Clock Output  
Ground  
VSS  
XOUT[1]  
Reference Output  
Absolute Maximum Conditions  
Parameter  
Description  
Min.  
–0.5  
–65  
Max.  
7.0  
Unit  
V
VDD  
TS  
Supply Voltage  
Storage Temperature[2]  
Junction Temperature  
Digital Inputs  
125  
°C  
°C  
V
TJ  
125  
V
SS – 0.3  
VDD + 0.3  
VDD + 0.3  
Digital Outputs Referred to VDD  
Electrostatic Discharge  
VSS – 0.3  
2000  
V
V
Recommended Operating Conditions  
Parameter  
DD/AVDD  
Description  
Operating Voltage  
Min.  
3.135  
0
Typ.  
Max.  
Unit  
V
V
3.3  
3.465  
70  
TA  
TA  
Ambient Temperature (Commercial)  
Ambient Temperature (Industrial)  
Max. Load Capacitance  
° C  
° C  
pF  
–40  
+85  
15  
CLOAD  
fREF  
tPU  
Reference Frequency  
19.44  
MHz  
ms  
Power-up time for all VDDs to reach  
minimum specified voltage (power  
ramps must be monotonic)  
0.05  
500  
DC Electrical Characteristics (Commercial)  
Parameter  
IOH  
Description  
Output High Current  
Output Low Current  
Input Capacitance  
Input Leakage Current  
Supply Current  
Conditions  
Min.  
Typ.  
Max.  
Unit  
mA  
mA  
pF  
VOH = VDD – 0.5, VDD = 3.3V  
VOL = 0.5, VDD = 3.3V  
12  
12  
24  
24  
IOL  
CIN  
IIZ  
7
5
µA  
IDD  
Sum of Core and Output Current  
20  
mA  
DC Electrical Characteristics (Industrial)  
Parameter  
IOH  
Description  
Output High Current  
Output Low Current  
Input Capacitance  
Input Leakage Current  
Supply Current  
Conditions  
VOH = VDD – 0.5, VDD = 3.3V  
VOL = 0.5, VDD = 3.3V  
Min.  
11  
Typ.  
24  
Max.  
Unit  
mA  
mA  
pF  
IOL  
CIN  
IIZ  
11  
24  
7
5
µA  
IDD  
Sum of Core and Output Current  
25  
mA  
Notes:  
1. Float XOUT if XIN is externally driven  
2. Rated for 10 years  
Document #: 38-07335 Rev. *B  
Page 2 of 5  
CY26200  
AC Electrical Characteristics (VDD = 3.3V, Commercial)  
Parameter[3]  
Description  
Output Duty Cycle  
Rising Edge Slew Rate  
Conditions  
Min.  
45  
Typ.  
50  
Max.  
Unit  
%
DC  
t3  
Duty Cycle is defined in Figure 1, 50% of VDD  
Output Clock Rise Time, 20% - 80% of VDD  
55  
0.8  
0.8  
1.4  
1.4  
200  
V/ns  
V/ns  
ps  
t4  
Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD  
t9  
Clock Jitter  
Peak to Peak period jitter  
t10  
PLL Lock Time  
3
ms  
AC Electrical Characteristics (VDD = 3.3V, Industrial)  
Parameter[3]  
Name  
Description  
Min.  
45  
Typ.  
50  
Max.  
Unit  
%
DC  
t3  
Output Duty Cycle  
Rising Edge Slew Rate  
Duty Cycle is defined in Figure 1, 50% of VDD  
Output Clock Rise Time, 20% - 80% of VDD  
55  
0.8  
0.8  
1.4  
1.4  
200  
V/ns  
V/ns  
ps  
t4  
Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD  
t9  
Clock Jitter  
Peak to Peak period jitter  
t10  
PLL Lock Time  
3
ms  
Test Circuit  
V
DD  
CLK out  
LOAD  
0.1 mF  
C
OUTPUTS  
GND  
t3  
t4  
t1  
t2  
80%  
CLK  
20%  
50%  
CLK  
50%  
Figure 2. Rise and Fall Time Definitions  
Figure 1. Duty Cycle Definition; DC = t2/t1  
Ordering Information  
Ordering Code  
CY26200SC  
CY26200SCT  
CY26200SI  
Package Type  
Operating Range  
Commercial  
Commercial  
Industrial  
Operating Voltage  
8-lead SOIC  
3.3V  
3.3V  
3.3V  
3.3V  
8-lead SOIC - Tape and Reel  
8-lead SOIC  
CY26200SIT  
Lead-free  
8-lead SOIC - Tape and Reel  
Industrial  
CY26200SXC  
CY26200SXCT  
CY26200SXI  
CY26200SXIT  
8-lead SOIC  
Commercial  
Commercial  
Industrial  
3.3V  
3.3V  
3.3V  
3.3V  
8-lead SOIC - Tape and Reel  
8-lead SOIC  
8-lead SOIC - Tape and Reel  
Industrial  
Notes:  
3. Not 100% tested  
Document #: 38-07335 Rev. *B  
Page 3 of 5  
CY26200  
Package Diagram  
8-lead (150-Mil) SOIC S8  
PIN 1 ID  
4
1
1. DIMENSIONS IN INCHES[MM] MIN.  
MAX.  
2. PIN 1 ID IS OPTIONAL,  
ROUND ON SINGLE LEADFRAME  
RECTANGULAR ON MATRIX LEADFRAME  
0.150[3.810]  
0.157[3.987]  
3. REFERENCE JEDEC MS-012  
4. PACKAGE WEIGHT 0.07gms  
0.230[5.842]  
0.244[6.197]  
PART #  
S08.15 STANDARD PKG.  
SZ08.15 LEAD FREE PKG.  
5
8
0.189[4.800]  
0.196[4.978]  
0.010[0.254]  
0.016[0.406]  
X 45°  
SEATING PLANE  
0.061[1.549]  
0.068[1.727]  
0.004[0.102]  
0.050[1.270]  
BSC  
0.0075[0.190]  
0.0098[0.249]  
0.004[0.102]  
0.0098[0.249]  
0°~8°  
0.016[0.406]  
0.035[0.889]  
0.0138[0.350]  
0.0192[0.487]  
51-85066-*C  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-07335 Rev. *B  
Page 4 of 5  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY26200  
Document History Page  
Document Title: CY26200 T1/E1 Clock Generator  
Document Number: 38-07335  
Issue  
Date  
Orig. of  
REV.  
**  
ECN No.  
111745  
121890  
400148  
Change Description of Change  
05/06/02  
12/14/02  
See ECN  
CKN  
RBI  
New Data Sheet  
*A  
Power up requirements added to Operating Conditions Information  
Added lead-free devices  
*B  
RGL  
Document #: 38-07335 Rev. *B  
Page 5 of 5  

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