CY28346-2_技术文档

PRELIMINARY

CY28346-2

Clock Synthesizer with Differential CPU Outputs

Features

• Compliant with Intel^®CK 408 Mobile Clock Synthesizer

• Spread Spectrum electromagnetic interference (EMI)

reduction

specifications

• 3.3V power supply

• Dial-a-Frequency^features

• 3 differential CPU clocks

• 10 copies of PCI clocks

• 5/6 copies of 3V66 clocks

• SMBus support with Read Back capabilities

• Dial-a-dB™ features

• Extended operating temperature range, 0°C to 85°C

• 56-pin TSSOP packages

Table 1. Frequency Table^[1]

CPU

66BUFF(0:2)/

3V66(0:4)

66IN/

USB/

DOT

48M

S2

1

0

S1

0

1

0

1

S0

0

1

0

1

0

1

0

1

(0:2)

3V66

66M

3V66-5

PCIF/PCI

66IN/2

33 M

Hi-Z

REF

66M

100M

200M

133M

66M

100M

200M

133M

Hi-Z

66IN

66M

Hi-Z

66-MHz clock input

14.318M

Hi-Z

66M

Hi-Z

48M

Hi-Z

TCLK/2

M

0

1

Hi-Z

TCLK/4

TCLK/2

TCLK/4

TCLK/8

TCLK

Block Diagram

Pin Configuration

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

REF

VDD

XIN

REF

2

S1

S0

XOUT

3

XOUT

4

CPU_STP#

CPUT0

CPUC0

VDD

VSS

CPUT(0:2)

5

PLL1

PCIF0

CPUC(0:2)

6

PCIF1

7

PCIF2

CPU_STP#

8

CPUT1

CPUC1

VSS

VDD

IREF

9

VSS

VSSIREF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PCI0

3V66_0

S(0:2)

VDD

PCI1

CPUT2

CPUC2

MULT0

IREF

PCI2

3V66_1/VCH

MULT0

PCI3

VDD

VTT_PWRGD#

PCI_STP#

/2

PCI(0:6)

VSS

VSSIREF

S2

PCI4

PCI_F(0:2)

48M_USB

48M_DOT

PCI5

48M_USB

48M_DOT

VDD

PLL2

PCI6

VDD

VSS

66B0/3V66_2

66B1/3V66_3

66B2/3V66_4

66IN/3V66_5

PD#

WD

PD#

3V66_1/VCH

PCI_STP#

3V66_0

VDD

Logic

I2C

SDATA

SCLK

Logic

VSS

66B[0:2]/3V66[2:4]

66IN/3V66-5

VDDA

SCLK

Power

Up Logic

VSSA

VDDA

SDATA

VTT_PWRGD#

Note:

1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a

0 state will be latched into the devices internal state register.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07509 Rev. *B

Revised March 11, 2005

PRELIMINARY

CY28346-2

Pin Description

Name

PWR

VDD

I/O

I

O

Description

2

3

XIN

Oscillator Buffer Input. Connect to a crystal or to an external clock.

XOUT

Oscillator Buffer Output. Connect to a crystal. Do not connect when an

external clock is applied at XIN.

52, 51, 49, 48, CPUT(0:2),

45, 44 CPUC(0:2)

VDD

VDDP

VDD

O

Differential host output clock pairs. See Table 1 for frequencies and

functionality.

10, 11, 12, 13, PCI(0:6)

PCI clock outputs. Are synchronous to 66IN or 3V66 clock. See Table 1.

16, 17, 18

5, 6, 7

PCIF (0:2)

33-MHz PCI clocks, which are ÷2 copies of 66IN or 3V66 clocks, may

be free running (not stopped when PCI_STP# is asserted LOW) or

may be stoppable depending on the programming of SMBus

register Byte3, Bits (3:5).

56

42

REF

IREF

VDD

O

I

Buffered output copy of the device’s XIN clock.

Current reference programming input for CPU buffers. A resistor is

connected between this pin and VSSIREF.

28

VTT_PWRGD#

VDD

I

Qualifying input that latches S(0:2) and MULT0. When this input is at

a logic low, the S(0:2) and MULT0 are latched.

39

38

33

35

48M_USB

48M_DOT

3V66_0

VDD48

VDD

O

Fixed 48-MHz USB clock outputs.

Fixed 48-MHZ DOT clock outputs.

3.3V 66-MHz fixed frequency clock.

3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.

When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When

byte0, Bit5 is a logic 0, then this is a 66M output clock (default).

3V66_1/VCH

VDD

25

43

PD#

VDD

I

This pin is a power-down mode pin. A logic LOW level causes the

PU device to enter a power-down state. All internal logic is turned off except

for the SMBus logic. All output buffers are stopped.

MULT0

I

Programming input selection for CPU clock current multiplier.

PU

55, 54

29

S(0,1)

SDATA

I

Frequency select inputs. See Table 1

Serial data input. Conforms to the SMBus specification of a Slave

Receive/Transmit device. It is an input when receiving data. It is an open

drain output when acknowledging or transmitting data.

30

40

SCLK

S2

I

Serial clock input. Conforms to the SMBus specification.

VDD

I

Frequency select input. See Table 1. This is a Tri-level input that is

T

driven HIGH, LOW, or driven to a intermediate level.

34

PCI_STP#

VDD

I

PCI clock disable input. When asserted LOW, PCI (0:6) clocks are

PU synchronously disabled in a LOW state. This pin does not effect PCIF

(0:2) clocks’ outputs if they are programmed to be PCIF clocks via the

device’s SMBus interface.

53

CPU_STP#

I

CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are

PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are

synchronously disabled in a LOW state.

24

66IN/3V66_5

VDD

–

I/O Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or

output clock for fixed 66-MHz clock if S2 = 0. See Table 1.

21, 22, 23

66B(0:2)/

3V66(2:4)

O

3.3V clock outputs. These clocks are buffered copies of the 66IN clock

or fixed at 66 MHz. See Table 1.

1, 8, 14, 19, 32, VDD

PWR 3.3V power supply.

37, 46, 50

4, 9, 15, 20, 27, VSS

31, 36, 47

–

PWR Common ground.

Document #: 38-07509 Rev. *B

Page 2 of 20

PRELIMINARY

CY28346-2

Pin Description (continued)

Name

PWR

I/O

Description

41

26

VSSIREF

–

PWR Current reference programming input for CPU buffers. A resistor is

connected between this pin and IREF. This pin should also be returned

to device VSS.

PWR Analog power input. Used for PLL and internal analog circuits. It is also

specifically used to detect and determine when power is at an acceptable

level to enable the device to operate.

VDDA

–

Serial Data Interface

Data Protocol

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initializes to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface can also be used during system

operation for power management functions.

The clock driver serial protocol accepts block write and block

read operations from the controller. For block write/read

operation, the bytes must be accessed in sequential order

from lowest to highest byte (most significant bit first) with the

ability to stop after any complete byte has been transferred.

The block write and block read protocol is outlined in Table 2.

The slave receiver address is 11010010 (D2h).

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Bit

1

Description

Bit

1

Description

Start

2:8

9

Slave address – 7 bits

Write = 0

2:8

9

Slave address – 7 bits

Write = 0

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code – 8 bit

11:18

Command Code – 8 bit

‘00000000’ stands for block operation

19

20:27

28

29:36

37

38:45

46

....

Acknowledge from slave

Byte Count – 8 bits

Acknowledge from slave

Data byte 1 – 8 bits

Acknowledge from slave

Data byte 2 – 8 bits

Acknowledge from slave

......................

Data Byte (N–1) –8 bits

Acknowledge from slave

Data Byte N –8 bits

Acknowledge from slave

Stop

19

20

21:27

28

29

30:37

38

39:46

47

48:55

56

....

Acknowledge from slave

Repeat start

Slave address – 7 bits

Read = 1

Acknowledge from slave

Byte count from slave – 8 bits

Acknowledge

Data byte from slave – 8 bits

Acknowledge

Data byte from slave – 8 bits

Acknowledge

Data bytes from slave/Acknowledge

Data byte N from slave – 8 bits

Not Acknowledge

....

Stop

Document #: 38-07509 Rev. *B

Page 3 of 20

PRELIMINARY

CY28346-2

Byte 0: CPU Clock Register

Bit @Pup Name

Description

7

0

Spread Spectrum Enable, 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit.

CPU clock Power-down Mode Select.

0 = Drive CPUT(0:2) to 4 or 6 IREF and drive CPUC(0:2) to low when PD# is asserted LOW.

1 = Three-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to

CPU_STP#.

6

0

3V66_1/VCH 3V66_1/VCH frequency Select, 0 = 66M selected, 1 = 48M selected

5

4

3

0

This is a Read and Write control bit.

Pin 53 CPUT,CPUC CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read-only.

PCI

Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is

Pin 34

a logical AND function of the internal SMBus register bit and the external PCI_STP# pin.

2

1

0

Pin 40

Pin 55

Pin 54

Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read-only.

Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read-only.

Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read-only.

Byte 1: CPU Clock Register

Bit @Pup

Name

Description

7

Pin 43

MULT0

MULT0 (Pin 43) Value. This bit is Read-only.

Controls functionality of CPUT/C(0:2) outputs when CPU_STP# is asserted. 0 = Drive CPUT(0:2) to

4 or 6 IREF and drive CPUC(0:2) to low when CPU_STP# asserted LOW. 1 = Three-state all CPU

outputs. This bit will override Byte0, Bit6 such that even if it is a 0, when PD# goes low the CPU

outputs will be three-stated.

6

0

CPU_STP#

Controls CPU2 functionality when CPU_STP# is asserted LOW

1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW

This is a Read and Write control bit.

Controls CPU1 functionality when CPU_STP# is asserted LOW

1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW

This is a Read and Write control bit.

Controls CPUT0 functionality when CPU_STP# is asserted LOW

1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW

This is a Read and Write control bit.

CPUT2

CPUC2

5

4

3

0

CPUT1

CPUC1

CPUT0

CPUC0

CPUT2 CPUT/C2 Output Control, 1 = enabled, 0 = disable HIGH and CPUC2 disables LOW

2

1

0

1

CPUC2 This is a Read and Write control bit.

CPUT1 CPUT/C1 Output Control, 1 = enabled, 0 = disable HIGH and CPUC1 disables LOW

CPUC1 This is a Read and Write control bit.

CPUT0 CPUT/C0 Output Control, 1 = enabled, 0 = disable HIGH and CPUC0 disables LOW

CPUC0 This is a Read and Write control bit.

Byte 2: PCI Clock Control Register (all bits are read and write functional)

Bit

7

6

5

4

3

2

1

0

@Pup

Name

REF

Description

0

1

REF Output Control. 0 = high strength, 1 = low strength

PCI6 Output Control. 1 = enabled, 0 = forced LOW

PCI5 Output Control. 1 = enabled, 0 = forced LOW

PCI4 Output Control. 1 = enabled, 0 = forced LOW

PCI3 Output Control. 1 = enabled, 0 = forced LOW

PCI2 Output Control. 1 = enabled, 0 = forced LOW

PCI1 Output Control. 1 = enabled, 0 = forced LOW

PCI0 Output Control. 1 = enabled, 0 = forced LOW

PCI6

PCI5

PCI4

PCI3

PCI2

PCI1

PCI0

Document #: 38-07509 Rev. *B

Page 4 of 20

PRELIMINARY

CY28346-2

Byte 3: PCIF Clock and 48M Control Register (all bits are read and write functional)

Bit

7

6

@Pup

Name

48M_DOT

48M_USB

PCIF2

Description

1

0

48M_DOT Output Control,1 = enabled, 0 = forced LOW

48M_USB Output Control,1 = enabled, 0 = forced LOW

5

PCI_STP#, control of PCIF2.

0 = Free Running, 1 = Stopped when PCI_STP# is LOW

4

3

0

PCIF1

PCIF0

PCI_STP#, control of PCIF1.

0 = Free Running, 1 = Stopped when PCI_STP# is LOW

PCI_STP#, control of PCIF0.

0 = Free Running, 1 = Stopped when PCI_STP# is LOW

2

1

0

1

PCIF2

PCIF1

PCIF0

PCIF2 Output Control. 1=running, 0=forced LOW

PCIF1 Output Control. 1= running, 0=forced LOW

PCIF0 Output Control. 1= running, 0=forced LOW

Byte 4: DRCG Control Register(all bits are read and write functional)

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Description

0

1

SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread)

Reserved

3V66_0

3V66_1/VCH

3V66_5

66B2/3V66_4

66B1/3V66_3

66B0/3V66_2

3V66_0 Output Enabled. 1 = enabled, 0 = disabled

3V66_1/VCH Output Enable. 1 = enabled, 0 = disabled

3V66_5 Output Enable. 1 = enabled, 0 = disabled

66B2/3V66_4 Output Enabled. 1 = enabled, 0 = disabled

66B1/3V66_3 Output Enabled. 1 = enabled, 0 = disabled

66B0/3V66_2 Output Enabled. 1 = enabled, 0 = disabled

Byte 5: Clock Control Register (all bits are read and write functional)

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Description

SS1 Spread Spectrum control bit

SS0 Spread Spectrum control bit

66IN to 66M delay Control MSB

66IN to 66M delay Control LSB

0

1

0

Reserved

48M_DOT edge rate control. When set to 1, the edge is slowed by 15%.

Reserved

USB edge rate control. When set to 1, the edge is slowed by 15%

Byte 6: Silicon Signature Register^[2](all bits are read-only)

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Description

0

1

0

1

Vendor Code, 011 = IMI

Note:

2. When writing to this register the device will acknowledge the write operation, but the data itself will be ignored.

Document #: 38-07509 Rev. *B

Page 5 of 20

PRELIMINARY

CY28346-2

Byte 7: Watchdog Time Stamp Register

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Description

0

Reserved

Byte 8: Dial-a-Frequency Control Register N (all bits are read and write functional)

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Description

0

N7, MSB

N6

N5

N4

N3

N2

N3

N0, LSB

Byte 9: Dial-a-Frequency Control Register R (all bits are read and write functional)

Bit

7

6

5

4

3

2

1

0

@Pup

Name

Description

0

R6 MSB

R5

R4

R3

R2

R1

R0, LSB

R and N register load gate 0 = gate closed (data is latched), 1 = gate

open (data is loading from SMBus registers into R and N)

Dial-a-Frequency Feature

Dial-a-dB Features

SMBus Dial-a-Frequency feature is available in this device via

Byte8 and Byte9. See our App Note AN-0025 for details on our

Dial-a-Frequency feature.

P is a large value PLL constant that depends on the frequency

selection achieved through the hardware selectors (S1, S0).

P value may be determined from Table 3.

SMBus Dial-a-dB feature is available in this device via Byte8

and Byte9.

Spread Spectrum Clock Generation (SSCG)

Spread Spectrum is a modulation technique used to

minimizing EMI radiation generated by repetitive digital

signals. A clock presents the greatest EMI energy at the center

frequency it is generating. Spread Spectrum distributes this

energy over a specific and controlled frequency bandwidth

therefore causing the average energy at any one point in this

band to decrease in value. This technique is achieved by

modulating the clock away from its resting frequency by a

certain percentage (which also determines the amount of EMI

reduction). In this device, Spread Spectrum is enabled by

setting specific register bits in the SMBus control Bytes.

Table 4 is a listing of the modes and percentages of Spread

Spectrum modulation that this device incorporates.

Table 3. P Value

S(1:0)

0 0

0 1

1 0

1 1

P

32005333

48008000

96016000

64010667

Document #: 38-07509 Rev. *B

Page 6 of 20

PRELIMINARY

CY28346-2

Configured as VCH (48M), SMBus Byte0, Bit 5 = ‘1’

Table 4. Spread Spectrum

SS2 SS1 SS0 Spread Mode

In this mode, the output is configured as a 48-MHz non-spread

spectrum output. This output is phase aligned with the other

48M outputs (USB and DOT), to within 1 ns pin-to-pin skew.

The switching of 3V66_1/VCH into VCH mode occurs at

system power on. When the SMBus Bit 5 of Byte 0 is

programmed from a ‘0’ to a ‘1’, the 3V66_1/VCH output may

glitch while transitioning to 48M output mode.

Spread%

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Down

Center

+0.00, –0.25

+0.00, –0.50

+0.00, –0.75

+0.00, –1.00

+0.13, –0.13

+0.25, –0.25

+0.37, –0.37

+0.50, –1.50

PD# (Power-down) Clarification

The PD# (Power-down) pin is used to shut off ALL clocks prior

to shutting off power to the device. PD# is an asynchronous

active LOW input. This signal is synchronized internally to the

device powering down the clock synthesizer. PD# is an

asynchronous function for powering up the system. When PD#

is low, all clocks are driven to a LOW value and held there and

the VCO and PLLs are also powered down. All clocks are shut

down in a synchronous manner so has not to cause glitches

while transitioning to the low ‘stopped’ state.

Special Functions

PCIF and IOAPIC Clock Outputs

The PCIF clock outputs are intended to be used, if required,

for systems IOAPIC clock functionality. ANY two of the PCIF

clock outputs can be used as IOAPIC 33-MHz clock outputs.

They are 3.3V outputs will be divided down via a simple

resistive voltage divider to meet specific system IOAPIC clock

voltage requirements. In the event these clocks are not

required, then these clocks can be used as general PCI clocks

or disabled via the assertion of the PCI_STP# pin.

PD#—Assertion

When PD# is sampled LOW by two consecutive rising edges

of the CPUC clock, then on the next HIGH-to-LOW transition

of PCIF, the PCIF clock is stopped LOW. On the next

HIGH-to-LOW transition of 66Buff, the 66Buff clock is stopped

LOW. From this time, each clock will stop LOW on its next

HIGH-to-LOW transition, except the CPUT clock. The CPU

clocks are held with the CPUT clock pin driven HIGH with a

value of 2 x Iref, and CPUC undriven. After the last clock has

stopped, the rest of the generator will be shut down.

3V66_1/VCH Clock Output

The 3V66_1/VCH pin has a dual functionality that is selectable

via SMBus.

Configured as DRCG (66M), SMBus Byte0, Bit 5 = ‘0’

The default condition for this pin is to power up in a 66M

operation. In 66M operation this output is SSCG capable and

when spreading is turned on, this clock will be modulated.

66Buff

PCIF

PWRDWN#

CPU 133MHz

CPU# 133MHz

3V66

66In

USB 48MHz

REF 14.318MHz

Figure 1. Power-down Assertion Timing Waveforms—Buffered Mode

Document #: 38-07509 Rev. *B

Page 7 of 20

PRELIMINARY

CY28346-2

PW R D W N #

C PU T 133M H z

C PU C 133M H z

PC I 33M H z

AG P 66M H z

U SB 48M H z

R EF 14.318M H z

DD R T 133M H z

D D R C 133M H z

SD R AM 133M H z

Figure 2. Power-down Assertion Timing Waveforms—Unbuffered Mode

PD# Deassertion

The power-up latency between PD# rising to a valid logic ‘1’

level and the starting of all clocks is less than 3.0 ms.

30uS min

<1.8mS

400uS max

66Buff1 / GMCH

66Buff

PCIF / APIC

33MHz

PCI 33MHz

PWRDWN#

CPU 133MHz

CPU# 133MHz

3V66

66In

USB 48MHz

REF 14.318MHz

Figure 3. Power-down Deassertion Timing Waveforms

Table 5. PD# Functionality

PD#

1

0

DRCG

66M

Low

66CLK (0:2)

66Input

Low

PCIF/PCI

66Input/2

Low

PCI

66Input/2

Low

USB/DOT

48M

Low

Document #: 38-07509 Rev. *B

Page 8 of 20

PRELIMINARY

CY28346-2

CPU_STP# Clarification

The CPU_STP# signal is an active LOW input used for

synchronous stopping and starting the CPU output clocks

while the rest of the clock generator continues to function.

(Mult 0 ‘select’) x (Iref), and the CPUC signal will not be driven.

Due to external pull-down circuitry CPUC will be LOW during

this stopped state.

CPU_STP# Deassertion

CPU_STP# Assertion

The deassertion of the CPU_STP# signal will cause all

CPUT/C outputs that were stopped to resume normal

operation in a synchronous manner. Synchronous manner

meaning that no short or stretched clock pulses will be

produces when the clock resumes. The maximum latency

from the deassertion to active outputs is no more than two

CPUC clock cycles.

When CPU_STP# pin is asserted, all CPUT/C outputs that are

set with the SMBus configuration to be stoppable via assertion

of CPU_STP# will be stopped after being sampled by two

falling CPUT/C clock edges. The final state of the stopped

CPU signals is CPUT = HIGH and CPU0C = LOW. There is no

change to the output drive current values during the stopped

state. The CPUT is driven HIGH with a current value equal to

CPU_STP#

CPUT

CPUC

CPUT

CPUC

Figure 4. CPU_STP# Assertion Waveforms

CPU_STP#

CPUT

CPUC

CPUT

CPUC

Figure 5. CPU_STP# Deassertion Waveforms

Document #: 38-07509 Rev. *B

Page 9 of 20

PRELIMINARY

CY28346-2

PCI_STP# Deassertion

Three-state Control of CPU Clocks Clarification

The deassertion of the PCI_STP# signal will cause all PCI and

stoppable PCIF clocks to resume running in a synchronous

manner within two PCI clock periods after PCI_STP# transi-

tions to a high level.

During CPU_STP# and PD# modes, CPU clock outputs may

be set to driven or undriven (three-state) by setting the corre-

sponding SMBus entry in Bit6 of Byte0 and Bit6 of Byte1.

PCI_STP# Assertion

Note that the PCI STOP function is controlled by two inputs.

One is the device PCI_STP# pin number 34 and the other is

SMBus byte 0 bit 3. These two inputs to the function are

logically ANDed. If either the external pin or the internal

SMBus register bit is set low then the stoppable PCI clocks will

be stopped in a logic low state. Reading SMBus Byte 0 Bit 3

will return a 0 value if either of these control bits are set LOW

thereby indicating the devices stoppable PCI clocks are not

running.

The PCI_STP# signal is an active LOW input used for

synchronous stopping and starting the PCI outputs while the

rest of the clock generator continues to function. The set-up

time for capturing PCI_STP# going LOW is 10 ns (t_setup). (See

Figure 2.) The PCIF (0:2) clocks will not be affected by this pin

if their control bits in the SMBus register are set to allow them

to be free running.

Table 6. Cypress Clock Power Management Truth Table

Stoppable

CPUC

Running

Iref x6

Low

Running

Hi Z

Running

Iref x6

Hi Z

B0b6

B1b6

PD#

1

0

1

0

1

0

1

0

CPU_STP#

CPUT

Running

Iref x6

Iref x2

Running

Hi Z

Non-Stop CPUT Non-Stop CPUC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Running

Iref x2

Running

Hi Z

Running

Low

Running

Hi Z

Running

Iref x6

Hi Z

Running

Hi Z

Running

Hi Z

Running

Hi Z

Running

Hi Z

Running

Hi Z

Running

Hi Z

t _setup

PCI_STP#

PCIF 33M

PCI 33M

Figure 6. PCI_STP# Assertion Waveforms

Document #: 38-07509 Rev. *B

Page 10 of 20

PRELIMINARY

CY28346-2

t _setup

PCI_STP#

PCIF

PCI

Figure 7. PCI_STP# Deassertion Waveforms

VID

SEL

VTT_PWRGD#

PWRGD

0.2-0.3mS

Wait for

Device is not affected,

VTT_PWRGD# is ignored.

Sample Sels

State 2

VDD Clock Gen

Clock State

Delay

VTT_PWRGD#

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 8. VTT_PWRGD# Timing Diagram

S2

S1

VTT_PWRGD# = Low

Delay

>0.25mS

Sample

Inputs straps

VDDA = 2.0V

S0

Wait for <1.8ms

S3

VDD3.3= off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 9. Clock Generator Power-up/Run State Program

Iout is selectable depending on implementation. The param-

eters above apply to all configurations. Vout is the voltage at

the pin of the device.

The various output current configurations are shown in the

host swing select functions table. For all configurations, the

deviation from the expected output current is ±7% as shown in

the current accuracy table.

Document #: 38-07509 Rev. *B

Page 11 of 20

PRELIMINARY

CY28346-2

Table 7. Host Clock (HCSL) Buffer Characteristics

Characteristic

Minimum

Maximum

Ro

3000 Ohms (recommended)

N/A

Ros

Vout

N/A

1.2V

Table 8. CPU Clock Current Select Function

Mult0

0

1

Board Target Trace/Term Z

50 Ohms

Reference R, Iref – Vdd (3*Rr)

Rr = 221 1%, Iref = 5.00 mA

Rr = 475 1%, Iref = 2.32 mA

Output Current

Ioh = 4*Iref

Voh @ Z

1.0V @ 50

0.7V @ 50

50 Ohms

Ioh = 6*Iref

Table 9. Group Timing Relationship and Tolerances

Description

Offset

2.5 ns

0.0 ns

2.5 ns

Tolerance

±1.0 ns

Conditions

3V66 Leads PCI (unbuffered mode)

0 degrees phase shift

66B leads PCI (buffered mode)

3V66 to PCI

48M_USB to 48M_DOT Skew

66B to PCI offset

±1.0 ns

Table 10.Maximum Lumped Capacitive Output Loads

66IN to 66B Buffered Prop Delay

The 66IN to 66B(0:2) output delay is shown in Figure 11.

The Tpd is the prop delay from the input pin (66IN) to the

output pins (66B[0:2]). The outputs’ variation of Tpd is

described in the AC parameters section of this data sheet. The

measurement is taken at 1.5V.

Clock

PCI Clocks

3V66

Max Load

Unit

pF

30

20

10

50

66B

48M_USB Clock

48M_DOT

REF Clock

66B to PCI Buffered Clock Skew

Figure 12 shows the difference (skew) between the 3V33(0:5)

outputs when the 66M clocks are connected to 66IN. This

offset is described in the Group Timing Relationship and Toler-

ances section of this data sheet. The measurements were

taken at 1.5V.

USB and DOT 48M Phase Relationship

The 48M_USB and 48M_DOT clocks are in phase. It is under-

stood that the difference in edge rate will introduce some in

inherent offset. When 3V66_1/VCH clock is configured for

VCH (48-MHz) operation it is also in phase with the USB and

DOT outputs. See Figure 10.

3V66 to PCI Unbuffered Clock Skew

Figure 13 shows the timing relationship between 3V66(0:5)

and PCI(0:6) and PCIF when configured to run in the unbuf-

fered mode.

48MUSB

48MDOT

Figure 10. 48M_USB and 48M_DOT Phase Relationship

66IN

66B

Tpd

Figure 11. 66IN to 66B(0:2) Output Delay Figure

Document #: 38-07509 Rev. *B

Page 12 of 20

PRELIMINARY

CY28346-2

66B

1.5-

3.5ns

PCI

PCIF

Figure 12. Buffer Mode – 33V66(0:1); 66BUF(0:2) Phase Relationship

3V66

Tpci

PCI

PCIF

Figure 13. Unbuffered Mode – 3V66(0:5) to PCI (0:6) and PCIF(0:2) Phase Relationship

Buffer Characteristics

Current Mode CPU Clock Buffer Characteristics

The current mode output buffer detail and current reference

circuit details are contained in the previous table of this data

sheet. The following parameters are used to specify output

buffer characteristics:

1. Output impedance of the current mode buffer circuit – Ro

(see Figure 14).

2. Minimum and maximum required voltage operation range

of the circuit – Vop (see Figure 14).

3. Series resistance in the buffer circuit – Ros (see Figure 14).

4. Current accuracy at given configuration into nominal test

load for given configuration.

VDD3 (3.3V +/- 5%)

Slope ~ 1/R₀

Ro

Iout

Ros

0V

1.2V

Iout

Vout = 1.2V max

Vout

Figure 14.

Document #: 38-07509 Rev. *B

Page 13 of 20

PRELIMINARY

CY28346-2

Absolute Maximum Conditions

Parameter

V_DD

V_{DD_A}

V_IN

T_S

T_A

T_J

Ø_JC

Ø_JA

Description

Core Supply Voltage

Analog Supply Voltage

Input Voltage

Temperature, Storage

Temperature, Operating Ambient

Temperature, Junction

Dissipation, Junction to Case

Dissipation, Junction to Ambient

ESD Protection (Human Body Model) MIL-STD-883, Method 3015

Flammability Rating

Condition

Min.

–0.5

–65

0

–

2000

–

Max.

4.6

V_DD+ 0.5

150

85

Unit

V

VDC

°C

Relative to V_SS

Non-functional

Functional

150

45

15

–

10

°C

Mil-Spec 883E Method 1012.1

JEDEC (JESD 51)

°C/W

V

ESD_HBM

Ul-94

MSL

V–0 @1/8 in.

ppm

Moisture Sensitivity Level

1

DC Parameters (V_DD= V_DDA= 3.3V ±5%)

Parameter Description

Idd3.3V Dynamic Supply Current

Ipd3.3V Power-down Supply Current PD# Asserted

Conditions

All frequencies at maximum values^[3]

Min.

Typ.

Max.

280

Note 4

Unit

mA

pF

nH

pF

Cin

Cout

Lpin

Cxtal

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

5

6

7

Crystal Pin Capacitance

Measured from the Xin or Xout Pin to Ground.

30

36

42

AC Parameters (V_DD= V_DDA= 3.3V ±5%)

66 MHz

100 MHz

133 MHz

200 MHz

Min. Max. Unit

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Notes

Crystal

Tdc

Xin Duty Cycle

Xin Period

Xin High Voltage

Xin Low Voltage

47.5

69.84

0.7Vdd

0

52.5

71.0

Vdd

0.3Vdd

10.0

47.5

69.84

0.7Vdd

0

52.5

71.0

Vdd

0.3Vdd

10.0

47.5

69.84

0.7Vdd

0

52.5

71.0

Vdd

0.3Vdd

10.0

47.5

69.84

0.7Vdd

0

52.5

71.0

Vdd

0.3Vdd

10.0

%

ns

V

ns

5, 6, 7

5, 8, 9, 6

Tperiod

Vhigh

Vlow

Tr/Tf

Xin Rise and Fall

10

Times

Tccj

Xin Cycle to Cycle

Jitter

500

ps

8, 11, 6

CPU at 0.7V Timing

Tdc

CPUT and CPUC

45

55

45

55

45

55

45

55

5.1

100

%

ns

ps

11, 12, 13

8, 11, 12

Duty Cycle

Tperiod

CPUT and CPUC

14.85

15.3

100

9.85

10.2

100

7.35

7.65

100

4.85

Period

Tskew

Any CPU to CPU

Clock Skew

Notes:

3. All outputs loaded as per maximum capacitive load table.

4. Absolute value = ((Programmed CPU Iref) x (2)) + 10 mA.

5. This parameter is measured as an average over 1-µs duration, with a crystal center frequency of 14.31818 MHz

6. When Xin is driven from an external clock source.

7. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock

duty cycle will not be within data sheet specifications.

8. All outputs loaded as perTable 10.

9. Probes are placed on the pins and measurements are acquired at 1.5V for 3.3V signals (see test and measurement set-up section of this data sheet).

10. Measured between 0.2Vdd and 0.7Vdd.

11. This measurement is applicable with Spread ON or Spread OFF.

12. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0 volts Measured from Vol = 0.175V to Voh = 0.525V.

13. Test load is Rta = 33.2 ohms, Rd = 49.9 ohms.

Document #: 38-07509 Rev. *B

Page 14 of 20

PRELIMINARY

CY28346-2

AC Parameters (V_DD= V_DDA= 3.3V ±5%) (continued)

66 MHz 100 MHz

133 MHz

200 MHz

Min. Max. Unit

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Notes

Tccj

CPU Cycle to Cycle

150

700

20%

150

700

20%

150

700

20%

150

700

20%

ps

11, 12, 13

Jitter

Tr/Tf

CPUT and CPUC

175

ps 11, Notes:,

16

Rise and Fall Times

Rise/Fall Matching

Notes:, 15,

13

DeltaTr

DeltaTf

Vcross

Rise Time Variation

Fall Time Variation

Crossing Point

Voltage at 0.7V

Swing

125

430

125

430

125

430

125

430

ps Notes:, 13

280

mV

11, 13

CPU at 1.0V Timing

Tdc

CPUT and CPUC

45

55

15.3

100

150

467

325

45

55

45

55

45

55

%

nS

pS

ps

11, 12

8, 11, 12

8, 12

Duty Cycle

Tperiod

Tskew

Tccj

CPUT and CPUC

14.85

9.85

10.2

100

150

467

325

7.35

7.65

100

150

467

325

4.85

5.1

Period

Any CPU to Any

CPU Clock Skew

100

150

467

325

CPU Cycle to Cycle

Jitter

Differential CPUT and CPUC

175

510

175

510

175

510

175

510

11, 16

17, 18

Tr/Tf

SE-

Rise and Fall Times

Absolute Single-

DeltaSlew ended Rise/Fall

Waveform

Symmetry

Vcross

Cross Point at 1.0V

760

mV

18

swing

3V66

Tdc

3V66 Duty Cycle

3V66 Period

3V66 High Time

3V66 Low Time

45

55

15.3

45

55

15.3

45

55

15.3

45

55

15.3

%

ns

8, 9

5, 8, 9

19

20

21

Tperiod

Thigh

Tlow

15.0

4.95

4.55

0.5

15.0

4.95

4.55

0.5

15.0

4.95

4.55

0.5

15.0

4.95

4.55

0.5

Tr / Tf

3V66 Rise and Fall

2.0

500

250

2.0

500

250

2.0

500

250

2.0

500

250

Times

Tskew

3V66 to 3V66 Clock

ps

8, 9

Unbuffered Skew

Tskew

3V66 to 3V66 Clock

Buffered

Skew

Tccj

DRCG Cycle to

Cycle Jitter

Notes:

14. Measured from Vol = 0.175V to Voh = 0.525V.

15. Determined as a fraction of 2*(Trise – Tfall)/ (Trise + Tfall).

16. Measurement taken from differential waveform, from –0.35V to +0.35V.

17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is definedas “the instantaneous difference

between maximum clk rise (fall) and minimum clk# fall (rise) time or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is designed form

waveform symmetry.

18. Measured in absolute voltage, i.e. single-ended measurement.

19. THIGH is measured at 2.4V for non host outputs.

20. TLOW is measured at 0.4V for all outputs.

21. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data

sheet).

Document #: 38-07509 Rev. *B

Page 15 of 20

PRELIMINARY

CY28346-2

AC Parameters (V_DD= V_DDA= 3.3V ±5%) (continued)

66 MHz 100 MHz

133 MHz

200 MHz

Min. Max. Unit

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Notes

66B

Tdc

66B(0:2) Duty Cycle

45

55

45

55

45

55

45

55

%

8, 9

Tr / Tf

Tskew

Tpd

66B(0:2) Rise and

0.5

2.0

0.5

2.0

0.5

2.0

0.5

2.0

ns

8, 21

Fall Times

Any 66B to Any 66B

Skew

175

4.5

175

4.5

175

4.5

175

4.5

ps

ns

ps

8, 9

66IN to 66B(0:2)

2.5

Propagation Delay

Tccj

66B(0:2) Cycle to

100

8, 9, 22

Cycle Jitter

PCI

Tdc

PCIF(0:2) PCI (0:6)

Duty Cycle

45

55

45

55

45

55

45

30

55

%

8, 9

5, 8, 9

19

Tperiod

Thigh

Tlow

PCIF(0:2) PCI (0:6)

30.0

12.0

0.5

30.0

12.0

0.5

30.0

12.0

0.5

nS

pS

ps

period

PCIF(0:2) PCI (0:6)

high time

12.0

0.5

PCIF(0:2) PCI (0:6)

20

low time

Tr/Tf

PCIF(0:2) PCI (0:6)

rise and fall times

2.0

500

250

2.0

500

250

2.0

500

250

2.0

500

250

21

Tskew

Tccj

Any PCI clock to

8, 9

Any PCI clock Skew

PCIF(0:2) PCI (0:6)

Cycle to Cycle Jitter

48M_USB

Tdc

48M_USB Duty

Cycle

45

55

45

55

45

55

45

55

%

8, 9

Tperiod

Tr/Tf

48M_USB Period

20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 20.8299 20.8333 ns

8, 9

8, 21

48M_USB Rise and

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.10

ns

Fall Times

Tccj

48M_USB Cycle to

Cycle Jitter

350

ps

5, 8, 9

48M_DOT

Tdc

48M_DOT Duty

Cycle

45

55

45

55

45

55

45

55

%

8, 9

Tperiod

Tr/Tf

48M_DOT Period

20.837

0.5

20.837

0.5

20.837

0.5

20.837

0.5

ns

8, 9

48M_DOT Rise and

1.0

Fall Times

Tccj

48M_DOT Cycle to

Cycle Jitter

350

ps

8, 9

REF

Tdc

REF Duty Cycle

REF Period

45

69.84

1.0

55

71.0

4.0

45

69.84

1.0

55

71.0

4.0

45

69.84

1.0

55

71.0

4.0

45

69.84

1.0

55

71.0

4.0

%

ns

8, 9

8, 21

Tperiod

Tr / Tf

REF Rise and Fall

Times

Tccj

REF Cycle to Cycle

Jitter

1000

ps

8, 9

Note:

22. This figure is additive to any jitter already present when the 66IN pin is being used as an input. Otherwise a 500-ps jitter figure is specified.

Document #: 38-07509 Rev. *B

Page 16 of 20

PRELIMINARY

CY28346-2

AC Parameters (V_DD= V_DDA= 3.3V ±5%) (continued)

66 MHz 100 MHz

133 MHz

200 MHz

Min. Max. Unit

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Notes

Tpzl/Tpzh Output Enable

Delay (all outputs)

1.0

10.0

3

1.0

10.0

3

1.0

10.0

3

1.0

10.0

3

ns

6

Tplz/Tpzh Output disable

delay (all outputs)

Tstable

All Clock Stabili-

zation from

ms

Power-up

Tss

Tsh

Tsu

Stopclock Set-up

10.0

0

10.0

0

10.0

0

10.0

0

ns

23

24

Time

Stopclock Hold

Time

Oscillator Start-up

1.2

ms

Time

Test and Measurement Set-up

For Differential CPU Output Signals

The following diagram shows lumped test load configurations

for the differential Host Clock Outputs.

T_PCB

33.2Ω

Measurement Point

Measurem ent Point

CPUT

2pF

475Ω

33.2Ω

MULTSEL

T_PCB

CPUC

63.4Ω

220Ω

Figure 15. 1.0V Test Load Termination

Notes:

23. CPU_STP# and PCI _STP# setup time with respect to any PCIF clock to guarantee that the effected clock will stop or start at the next PCIF clock’s rising edge.

24. When Crystal meets minimum 40-ohm device series resistance specification.

Document #: 38-07509 Rev. *B

Page 17 of 20

PRELIMINARY

CY28346-2

T_PCB

33Ω

Measurement Point

CPUT

VDD

49.9Ω

2pF

MULTSEL

T_PCB

CPUC

221Ω

Figure 16. 0.7V Test Load Termination

For Single-Ended Output Signals

Output under Test

Probe

Load Cap

3.3V signals

tDC

-

3.3V

2.4V

1.5V

0.4V

0V

Tr

Tf

Figure 17.

Ordering Information

Part Number

Package Type

56-pin TSSOP–Tube

Product Flow

Commercial, 0° to 70°C

CY28346ZC-2

CY28346ZC-2T

CY28346ZI-2

CY28346ZI-2T

56-pin TSSOP–Tape and Reel

56-pin TSSOP–Tube

56-pin TSSOP–Tape and Reel

Commercial, 0° to 70°C

Industrial, 0° to 85°C

Lead-free

CY28346ZXC-2

CY28346ZXC-2T

56-pin TSSOP–Tube

56-pin TSSOP–Tape and Reel

Commercial, 0° to 70°C

Document #: 38-07509 Rev. *B

Page 18 of 20

PRELIMINARY

CY28346-2

Package Drawings and Dimensions

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56

0.249[0.009]

28

1

DIMENSIONS IN MM[INCHES] MIN.

MAX.

7.950[0.313]

8.255[0.325]

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.42gms

5.994[0.236]

6.198[0.244]

PART #

Z5624 STANDARD PKG.

ZZ5624 LEAD FREE PKG.

29

56

13.894[0.547]

14.097[0.555]

1.100[0.043]

MAX.

GAUGE PLANE

0.25[0.010]

0.20[0.008]

0.508[0.020]

0.762[0.030]

0.051[0.002]

0.152[0.006]

0.851[0.033]

0.950[0.037]

0.500[0.020]

BSC

0°-8°

0.100[0.003]

0.200[0.008]

0.170[0.006]

0.279[0.011]

SEATING

PLANE

51-85060-*C

Intel is a registered trademark of Intel Corporation. Dial-a-Frequency is a registered trademark, and Dial-a-dB is a trademark, of

Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective

holders.

Document #: 38-07509 Rev. *B

Page 19 of 20

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

PRELIMINARY

CY28346-2

Document History Page

Document Title: CY28346-2 Clock Synthesizer with Differential CPU Outputs

Document Number: 38-07509

Issue

Date

12/11/02

06/10/03

Orig. of

Change

RGL

REV.

**

*A

ECN NO.

122429

127147

Description of Change

New Data Sheet

Corrected the value of T_SUparameter in the AC parameters table from x to 1.2

Removed “Preliminary” (it is a final data sheet)

*B

333295

See ECN

RGL

Added Lead-free for tssop commercial only

Document #: 38-07509 Rev. *B

Page 20 of 20


型号：	CY28346-2
厂家：	CYPRESS
描述：	Clock Synthesizer with Differential CPU Outputs 时钟合成器，差分CPU输出时钟
文件：	总20页 (文件大小：237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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