CY2CC910OXIT [CYPRESS]
1:10 Clock Fanout Buffer; 1:10时钟扇出缓冲器
| 型号： | CY2CC910OXIT |
| 厂家： | 
CYPRESS |
| 描述： | 1:10 Clock Fanout Buffer |
| 文件： | 总9页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
COMLINK™ SERIES
CY2CC910
1:10 Clock Fanout Buffer
Features
• Low-voltage operation
Description
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the indus-
tries fastest logic and buffers.
• Full-range support:
— 3.3V
The Cypress CY2CC910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V
— 2.5V
— 1.8V
Designed for Data Communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
• Over voltage tolerant input hot swappable
• 1:10 fanout
• Drives either a 50-Ohm or 75-Ohm load
• Low-input capacitance
• Low-output skew
Cypress employs unique AVCMOS type outputs VOI™
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors and reduce noise overall.
• Low-propagation delay
• Typical (tpd < 4 ns)
• High-speed operation:
— 200 MHz@1.8V
— 650 MHz@2.5V/3.3V
• Industrial versions available
• Available packages include: SOIC, SSOP
Pin Configuration
Block Diagram
3
Q 1
20
19
18
17
16
15
14
13
12
11
VDD
IN
1
2
3
4
5
6
7
8
5
7
Q10
Q9
Q 2
Q 3
Q 4
Q 5
Q 6
Q 7
Q 8
Q 9
Q 10
GND
Q1
VDD
Q2
GND
Q8
VD D
9
VDD
Q7
4,8
15,20
GND
Q3
11
GND
Q6
VDD
Q4
IN
1
9
10
12
14
16
18
19
Q5
INPUT
(AVCMOS)
2,6,10
GND
20 pin SOIC/SSOP
13,17
G N D
OUTPUT
(AVCMOS)
Cypress Semiconductor Corporation
Document #: 38-07348 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 27, 2005
COMLINK™ SERIES
CY2CC910
Pin Description
Pin Number
Pin Name
Description
1
IN
Input
2,6,10,13,17
GND
VDD
Ground
4,8,15,20
Power Supply
Output
3,5,7,9,11,12,14,16,18,19
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10
Maximum Ratings[1]
Storage Temperature: .................................–65°C to +150°C
Ambient Temperature:...................................–40°C to +85°C
Supply Voltage to Ground Potential
Supply Voltage to Ground Potential
(Outputs only)........................................... –0.5V to VDD + 1V
DC Output Voltage.................................... –0.5V to VDD + 1V
Power Dissipation........................................................ 0.75W
VCC .................................................................. –0.5V to 4.6V
Input................................................................. –0.5V to 5.8V
Variable Output Impedance Control (VOI™)
Pull Up
Pull Down
3.5
3.5
3
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Ioh (A)
Iol (A)
Vdd = 3.3 V
Vdd = 2.5 V
Vdd = 1.8 V
Vdd = 3.3 V
Vdd = 2.5 V
Vdd = 1.8 V
Figure 1. Output Voltage vs. Output Current (TA = 25°C)
DC Electrical Characteristics @ 3.3V (see Figure 2)
Parameter
VOH
Description
Output High Voltage
Output Low Voltage
Input High Voltage
Conditions
Min.
Typ.
Max.
Unit
V
VDD = Min., VIN = VIH or VIL IOH = –12 mA 2.3
VDD = Min., VIN = VIH or VIL IOL = 12 mA
3.3
0.2
VOL
VIH
0.5
5.8
V
Guaranteed Logic High
Level
2
V
VIL
IIH
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Continuous Clamp Current
Power-down Disable
Input Hysteresis
Guaranteed Logic Low Level
VDD = Max.
0.8
1
V
VIN = 2.7V
VIN = 0.5V
µA
µA
µA
V
IIL
VDD = Max.
–1
II
VDD = Max., VIN = VDD(Max.)
VDD = Min., IIN = –18 mA
VDD = Max., VOUT = GND
VDD = GND, VOUT = < 4.5V
20
VIK
IOK
OOFF
VH
–0.7
80
–1.2
–50
100
mA
µA
mV
Note:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Document #: 38-07348 Rev. *B
Page 2 of 9
COMLINK™ SERIES
CY2CC910
DC Electrical Characteristics @ 2.5V (see Figure 2)
Parameter
Description
Conditions
Min.
1.8
Typ.
Max.
Unit
V
VOH
Output High Voltage
VDD = Min., VIN = VIH or VIL
IOH = –7 mA
OH = 12 mA
I
1.6
V
VOL
VIH
VIL
IIH
Output Low Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
VDD = Min., VIN = VIH or VIL
Guaranteed Logic High Level
Guaranteed Logic Low Level
VDD = Max.
IOL = 12 mA
0.65
5.0
0.8
1
V
1.6
V
V
VIN = 2.4V
VIN = 0.5V
µA
µA
µA
V
IIL
VDD = Max.
–1
II
VDD = Max., VIN = VDD(Max.)
VDD = Min., IIN = –18 mA
20
VIK
IOK
OOFF
VH
–0.7
80
–1.2
–50
100
Continuous Clamp Current VDD = Max., VOUT = GND
mA
µA
mV
Power Down Disable
Input Hysteresis
VDD = GND, VOUT = < 4.5V
DC Electrical Characteristics @ 1.8V (see Figure 6)
Parameter
VDD
Description
Supply Voltage
Test Condition[2]
Min.
Max.
Unit
V
1.71
0.65VDD[1.1]
–0.3
1.89
4.3
VIH
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
V
VIL
0.35 VDD[0.6]
V
VOH
IOH = –2 mA
IOH = 2 mA
VDD – 0.45[1.2]
V
VOL
0.45
V
Capacitance
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
2.5
Max.
Unit
VIN = 0V
VOUT = 0V
pF
pF
COUT
6.5
Power Supply Characteristics (see Figure 2)
Parameter
Description
Test Conditions
Min.
Typ
Max
Unit
∆
Delta ICC Quiescent Power (IDD @ VDD = Max and VIN = VDD) – (IDD
@
50
µA
ICC
Supply Current
VDD = Max and VIN = VDD – 0.6V)
ICCD
Dynamic Power Supply
Current
VDD = Max
Input toggling 50% Duty Cycle, Outputs
Open
0.63
25
mA/
MHz
IC
Total Power Supply Current VDD = Max
Input toggling 50% Duty
Cycle, Outputs Open fL = 40 MHZ
mA
Note:
2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency.
Document #: 38-07348 Rev. *B
Page 3 of 9
COMLINK™ SERIES
CY2CC910
High Frequency Parametrics
Parameter
Description
Test Conditions
50% duty cycle tW(50–50)
Min. Typ. Max.
Unit
DJ
Jitter, Deterministic
See Figure 4
20
ps
The “point to point load circuit”
| Output Jitter – Input Jitter |
Fmax
3.3V
Maximum frequency
VDD = 3.3V
50% duty cycle tW(50–50)
Standard Load Circuit.
See Figure 2
See Figure 4
See Figure 4
See Figure 6
See Figure 5
160
650
200
200
250
MHz
50% duty cycle tW(50–50)
The “point to point load circuit”
Fmax
2.5V
Maximum frequency
VDD = 2.5V
The “point-to-point load circuit”
VIN = 2.4V/0.0V VOUT = 1.7V/0.7V
MHz
MHz
MHz
Fmax
1.8V
Maximum frequency
VDD = 1.8V
The “6-pF load circuit”
VIN = 1.7/0.0V VOUT = 1.2V/0.4V
Fmax(20)
Maximum frequency
20% duty cycle tW(20-80)
VDD = 3.3V
The “point to point load circuit”
VIN = 3.0V/0.0V VOUT = 2.3V/0.4V
tW
3.3V
Minimum pulse
VDD = 3.3V
The “point-to-point load circuit”
VIN = 3.0V/0.0V F = 100 MHz
VOUT = 2.0V/0.8V
See Figure 4
See Figure 4
See Figure 6
1
1
1
ns
ns
ns
tW
2.5V
Minimum pulse
VDD = 2.5V
The “point-to-point load circuit”
VIN = 2.4V/0.0V F = 100 MHz
VOUT = 1.7V/0.7V
tW
1.8V
Minimum pulse
VDD = 1.8V
The “6-pF load circuit”
VIN = 1.7V/0.0V VOUT = 1.2V/0.4V
AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, Temperature = –40°C to +85°C
Parameter Description
tPLH
tPHL
tR
Min. Typ. Max. Unit
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time
See Figure 3
1.5
1.5
2.7
2.7
0.8
0.8
3.5
3.5
ns
ns
V/ns
V/ns
ns
tF
Output Fall Time
tSK(0)
Output Skew: Skew between outputs of the same package (in See Figure 10
phase).
0.2
0.2
0.4
tSK(p)
tSK(t)
Pulse Skew: Skew between opposite transitions of the same
output (tPHL – tPLH).
See Figure 9
ns
ns
Package Skew: Skew between outputs of different packages at See Figure 11
the same power supply voltage, temperature and package type.
AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, Temperature = –40°C to +85°C
Parameter
tPLH
Description
Min. Typ. Max. Unit
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time
See Figure 3
1.5
1.5
2.7 3.5 ns
2.7 3.5 ns
tPHL
tR
0.8
0.8
V/ns
V/ns
tF
Output Fall Time
tSK(0)
tSK(p)
Output Skew: Skew between outputs of the same package (in phase). See Figure 10
0.2 ns
0.2 ns
Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 9
– tPLH).
tSK(t)
Package Skew: Skew between outputs of different packages at the same See Figure 11
power supply voltage, temperature and package type.
0.4 ns
Document #: 38-07348 Rev. *B
Page 4 of 9
COMLINK™ SERIES
CY2CC910
AC Switching Characteristics @ 1.8V VDD = 1.8V ±5%, Temperature = –40°C to +85°C
Parameter
Description
Min. Typ. Max. Unit
tPLH
tPHL
tR
Propagation Delay – Low to High
Propagation Delay – High to Low
Output Rise Time 20 – 80%
Output Fall Time 20 – 80%
See Figure 7
1.5
1.5
0.2
0.2
2.7 3.5
2.7 3.5
1.5
ns
ns
ns
ns
ns
tF
1.5
tSK(0)
Output Skew: Skew between outputs of the same package (in phase). See Figure 10
0.2
Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 9
– tPLH).
tSK(p)
tSK(t)
0.2
0.4
ns
ns
Package Skew: Skew between outputs of different packages at the same See Figure 11
power supply voltage, temperature and package type.
Parameter Measurement Information: VDD@3.3V–2.5V
From Output
Under Test
From Output
Under Test
CL = 50 pF
500 ohm
CL = 3 pF
500 ohm
Figure 2. Load Circuit [3,4,5]
0.8VDD
Figure 4. Point to Point Load Circuit[3,4,5]
tw(50-50)
0.8VDD
VDD/2
VDD/2
Input
0 V
VDD/2
Input
VDD/2
tPLH
tPHL
0 V
tw(20-80)
VOH
VOL
0.8VDD
VDD/2
VDD/2
Output
Input
VDD/2
0 V
Figure 3. Voltage Waveforms Propagation Delay Times[6]
[4]
Figure 5. Voltage Waveforms–Pulse Duration
Parameter Measurement Information: VDD@1.8V
From Output
Under Test
tw(50-50)
1.8V
Input
Input
0.9V
0.9V
0.9V
CL = 6 pF
500 ohm
0 V
tw(20-80)
1.8V
[3,4,5]
Figure 6. Load Circuit
0.9V
0 V
1.8V
[4]
Figure 8. Voltage Waveforms–Pulse Duration
0.9V
Input
0 V
tPLH
tPHL
VOH
VOL
0.9V
0.9V
Output
Figure 7. Voltage Waveforms Propagation
[6]
Delay Times
Notes:
3. C includes probe and jig capacitance.
L
4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z = 50Ω, t < 2.5 ns, t < 2.5 ns.
0
R
F
5. The outputs are measured one at a time with one transition per measurement.
6. T and T are the same as t
.
pd
PLH
PHL
Document #: 38-07348 Rev. *B
Page 5 of 9
COMLINK™ SERIES
CY2CC910
3V
1.5V
0V
INPUT
tPHL
tPLH
VOH
1.5V
VOL
OUTPUT
tsk(P) = l tPHL - tPLH
l
Figure 9. Pulse Skew–tsk
(p)
3V
1.5V
0V
INPUT
tPHL1
tPLH1
tsk(O)
tPLH 2
VOH
1.5V
OUTPUT 1
OUTPUT 2
VOL
VOH
1.5V
tsk(O)
VOL
tPLH 2
tsk(P) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1
Figure 10. Output Skew–tsk
l
(0)
3V
1.5V
0V
INPUT
tPHL1
tPLH1
VOH
1.5V
VOL
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tsk(t)
tsk(t)
VOH
1.5V
VOL
tPLH 2
tPLH 2
tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1
Figure 11. Package Skew - tsk
l
(t)
Document #: 38-07348 Rev. *B
Page 6 of 9
COMLINK™ SERIES
CY2CC910
Ordering Information
Part Number
CY2CC910SI
Package Type
Product Flow
20-pin SOIC
Industrial, –40° to 85°C
CY2CC910SIT
CY2CC910SC
CY2CC910SCT
CY2CC910OI
20-pin SOIC–Tape and Reel
20-pin SOIC
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
20-pin SOIC–Tape and Reel
20-pin SSOP
CY2CC910OIT
CY2CC910OC
CY2CC910OCT
Lead-free
20-pin SSOP–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
CY2CC910OXI
CY2CC910OXIT
CY2CC910OXC
CY2CC910OXCT
20-pin SSOP
Industrial, –40° to 85°C
Industrial, –40° to 85°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
20-pin SSOP–Tape and Reel
20-pin SSOP
20-pin SSOP–Tape and Reel
Document #: 38-07348 Rev. *B
Page 7 of 9
COMLINK™ SERIES
CY2CC910
Package Drawing and Dimensions
20-Lead (300-Mil) SOIC S5
PIN 1 ID
10
1
MIN.
MAX.
DIMENSIONS IN INCHES [MM]
0.291[7.391]
0.300[7.620]
*
REFERENCE JEDEC MO-119
PACKAGE WEIGHT 0.55 gms
0.394[10.007]
0.419[10.642]
PART #
11
20
S20.3 STANDARD PKG.
SZ20.3 LEAD FREE PKG.
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.497[12.623]
0.513[13.030]
0.092[2.336]
0.105[2.667]
*
0.004[0.101]
*
0.0091[0.231]
0.0125[0.317]
0.050[1.270]
TYP.
0.004[0.101]
0.0118[0.299]
0.015[0.381]
0.050[1.270]
0.013[0.330]
0.019[0.482]
51-85024-*B
20-pin Shrunk Small Outline Package O20
51-85077-*C
VOI is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks
of their respective holders.
Document #: 38-07348 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
COMLINK™ SERIES
CY2CC910
Document History Page
TM
Document Title: CY2CC910 COMLINK SERIES 1:10 Clock Fanout Buffer
Document #: 38-07348
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
114318
119148
Description of Change
05/10/02
10/07/02
TSM
RGL
New Data Sheet
*A
Added 5.8 as the Max. value for V in the DC Electrical Characteristics
IH
@3.3V table.
Changed the Max. value of V from 5.8 to 5.0 in the DC Electrical Charac-
IH
teristics @2.5V table.
Changed the value of V from V +0.3 [2.25] to 4.3 in the DC Electrical
IH
DD
Characteristics @1.8V table.
*B
404287
See ECN
RGL
Added Lead-free devices for SSOP
Document #: 38-07348 Rev. *B
Page 9 of 9
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