CY2DL814ZXCT [CYPRESS]
ComLink⑩ Series; COMLINK ™系列
| 型号： | CY2DL814ZXCT |
| 厂家： | 
CYPRESS |
| 描述： | ComLink⑩ Series |
| 文件： | 总8页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ComLink™ Series
CY2DL814
1:4 Clock Fanout Buffer
Features
Description
• Low-voltage operation
• VDD = 3.3V
• 1:4 Fanout
• Single-input configurable for
— LVDS, LVPECL, or LVTTL
The Cypress CY2 series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industry’s fastest logic.
The Cypress CY2DL814 fanout buffer features a single
LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS
output pairs.
Designed for data-communication clock management applica-
tions, the fanout from a single input reduces loading on the
input clock.
The CY2DL814 is ideal for both level translations from single
ended to LVDS and/or for the distribution of LVDS-based clock
signals. The Cypress CY2DL814 has configurable input and
output functions. The input can be selectable for
LVPECL/LVTTL or LVDS signals while the output driver’s
support standard and high drive LVDS. Drive either a 50-ohm
or 100-ohm line with a single part number/device.
— Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• 85 ps typical output-to-output skew
• <4 ns typical propagation delay
• Does not exceed Bellcore 802.3 standards
• Operation at ⇒ 350 MHz – 700 Mbps
• Industrial versions available
• Packages available include TSSOP/SOIC
Block Diagram
Pin Configuration
EN1
EN2
EN1
16
15
14
13
12
11
Q1A
Q1B
1
2
3
4
5
6
7
8
CONFIG
CNTRL
VDD
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
GND
IN+
IN-
Q2A
Q2B
IN+
IN-
10
EN2
9
LVDS /
LVPECL /
LVTTL
Q3A
Q3B
16-pin TSSOP/SOIC
CONFIG
Q4A
Q4B
CNTRL
OUTPUT
LVDS
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07057 Rev. *B
Revised June 20, 2005
ComLink™ Series
CY2DL814
Pin Description
Pin Number
Pin Name
Pin Standard Interface
Description
6,7
IN+, IN–
Configurable
Differential input pair or single line.
LVPECL default. See config below.
3
2
CNTRL
CONFIG
EN1, EN2
LVTTL/LVCMOS
LVTTL/LVCMOS
Converts into a High drive driver from a standard LVDS.
Standard drive (logic = 0)
B/High drive/Bus (logic = 1)
Converts inputs (IN+/IN–), (EN, EN#) from the default
LVPECL/LVDS (logic = 0)
To LVTTL/LVCMOS (logic = 1)
1,8
LVTTL/LVCMOS
LDVS
Enable/disable logic. See Table 1 below for details.
Differential outputs.
16,15,14,13
Q1A, Q1B, Q2A,
12,11,10,9
Q2B,
Q3A, Q3B, Q4A,
Q4B
4
5
VDD
GND
POWER
POWER
Positive supply voltage
Ground
Maximum Ratings[1, 2]
Storage Temperature: ................................–65°C to + 150°C
Ambient Temperature:...................................–40°C to +85°C
(Outputs only)........................................ –0.3V to VDD + 0.3V
DC Input Voltage ................................... –0.3V to VDD + 0.3V
DC Output Voltage................................. –0.3V to VDD + 0.9V
Power Dissipation........................................................ 0.75W
Supply Voltage to Ground Potential
(Inputs and VCC only)....................................... –0.3V to 4.6V
Supply Voltage to Ground Potential
Table 1. EN1 EN2 Function Table–Differential Input Mode
Enable Logic
Input
Outputs
EN1
H
EN2
X
IN+
H
IN–
L
QnA
H
QnB
L
H
X
L
H
L
H
X
L
H
L
H
L
X
L
L
H
L
H
L
H
X
X
Z
Z
Table 2. Output Drive Control for Standard and Bus/B/High Drive B
CNTRL Pin 3 Binary Value
Drive STD
Standard
Impedance
Output Voltage Value
V0 = Voutput
V = 1/2 * V0
V = 2 * V0
V = V0
0
100 ohm
50 ohm
100 ohm
50 ohm
1
High Drive/Bus/B
Notes:
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07057 Rev. *B
Page 2 of 8
ComLink™ Series
CY2DL814
Table 3. Input Receiver Configuration for Differential or LVTTL/LVCMOS
CONFIG
Pin 2
Binary Value
Input Receiver Family
LVTTL in LVCMOS
LVDS
Input Receiver Type
Single-ended, Non-inverting, Inverting, Void of Bias Resistors
Low-voltage Differential Signaling
1
0
LVPECL
Low-voltage Pseudo (Positive) Emitter Coupled Logic
Table 4. Function Control of the TTL Input Logic Used to Accept or Invert the Input Signal
LVTTL/LVCMOS Input Logic
Input Condition
IN– Pin 7
Input Logic
Output Logic Q Pins, Q1A or Q1
Ground
VCC
IN+ Pin 6
IN– Pin 7
IN+ Pin 6
IN+ Pin 6
IN– Pin 7
IN+ Pin 6
IN– Pin 7
Input
True
Invert
True
Input
Ground
VCC
Input
Input
Invert
Table 5. Power Supply Characteristics
Parameter
ICCD
Description
Dynamic Power Supply Current
Test Conditions
Min.
Typ.
1.5
Max.
2.0
Unit
mA/MHz
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs Open
IC
Total Power Supply Current
VDD = Max.
90
100
mA
Input toggling 50% Duty Cycle,
Outputs Open
fL=100 MHz
Table 6. D.C Electrical Characteristics: 3.3V–LVDS Input
Parameter
Description
Conditions
Min.
Typ. Max. Unit
VID
VIC
VIH
VIL
IIH
IIL
Magnitude of Differential Input Voltage
Common-mode of Differential Input Voltage IVIDI (min. and max.)
100
600 mV
IVIDI/2 2.4–(IVIDI/2)
V
V
V
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Guaranteed Logic High Level
Guaranteed Logic Low Level
VDD = Max.
VDD = Max.
VDD = Max., VIN = VDD(max.)
Config/Cntrl Pins
2
0.8
VIN = VDD
VIN = VSS
±10
±10
±20 µA
±20 µA
±20 µA
II
Table 7. D.C Electrical Characteristics: 3.3V–LVPECL Input
Parameter
Description
Conditions
Min.
400
1.65
Typ.
Max.
2600
2.25
±20
±20
±20
Unit
mV
V
µA
µA
µA
VID
VCM
IIH
IIL
Differential Input Voltage p-p Guaranteed Logic High Level
Common-mode Voltage
Input High Current
Input Low Current
Input High Current
VDD = Max.
VDD = Max.
VIN = VDD
VIN = VSS
±10
±10
II
VDD = Max., VIN = VDD(Max.)
Document #: 38-07057 Rev. *B
Page 3 of 8
ComLink™ Series
CY2DL814
Table 8. D.C Electrical Characteristics: 3.3V–LVTTL/LVCMOS Input
Parameter
Description
Input High Voltage
Conditions
Guaranteed Logic High Level
Guaranteed Logic Low Level
VDD= Max.
VDD= Max.
VDD = Max., VIN = VDD(Max.)
VDD = Min., IIN = –18 mA
Min.
2
Typ.
Max.
Unit
V
V
µA
µA
µA
V
VIH
VIL
IIH
IIL
II
VIK
VH
Input Low Voltage
Input High Current
Input Low Current
Input High Current
Clamp Diode Voltage
Input Hysteresis
0.8
1
–1
20
–1.2
VIN = 2.7V
VIN = 0.5V
–0.7
80
mV
Table 9. D.C Electrical Characteristics: 3.3V–LVDS OUTPUT
Parameter Description
I VOD
Conditions
Min. Typ. Max. Unit
I
Differential output voltage p-p VDD = 3.3V, VIN = VIH, or VIL
RL = 100 ohm
RL = 100 ohm
0.25
–
0.45
V
VOC(SS)
Steady-state common-mode
–
–
226
mV
output voltage
Delta
Change in VOC(SS) between
logic states
–50
–
3
–
50
mV
mV
mA
VOC(SS)
VOC(PP)
Peak to peak common mode
150
–20
output voltage
IOS
Voh
Vol
Output short circuit
Output voltage high
Output voltage low
QA = 0V or QB = 0V
–
–
925
–
–
–
1475 mV
mV
–
Table 10.AC Parameters
Parameter
Description
Conditions
Min. Typ. Max. Unit
Rise Time Pin control (pin 3) logic is “FALSE”
CL–10 pF
RL = 100 ohm
–
–
1.4 ns
defaulting to 100 ohm output drivers. RL and CL to GND
Differential 20% to 80%
3 CL = Cintrinsic and Cexternal
Fall Time
–
–
–
1.4 ns
Rise Time Pin control (pin 3) logic is “True”
CL–10 pF
RL = 50 ohm
Output boost
350 600 ps
350 600 ps
defaulting to 50 ohm output drivers. RL and CL to GND
Differential 20% to 80%
Fall Time
3 CL = Cintrinsic and Cexternal
–
Table 11.AC Switching Characteristics @ 3.3 V (VDD = 3.3V ±5%, Temperature = –40°C to +85°C)
Parameter Description Conditions Min. Typ. Max. Unit
IN [+,-] to Q[A,B] Data and Clock Speed
tPLH
tPHL
Tpd
Propagation Delay – Low to High
Propagation Delay – High to Low
Propagation Delay
VOD = 100 mV
3
3
3
4
4
4
5
5
5
ns
ns
ns
IN [1,2] to Q[A,B] Control Speed
TPe
Tpd
Enable (EN) to functional operation
Functional operation to Disable
–
–
–
–
6
5
ns
ns
Q[A,B] Output Skews
tSK(0)
tSK(p)
tSK(t)
Output Skew: Skew between outputs of the same
–
–
–
0.085 0.2
ns
ns
ns
package (in phase)
Pulse Skew: Skew between opposite transitions of the
0.2
–
–
1
same output (tPHL–tPLH
)
Package Skew: Skew between outputs of different
packages at the same power supply voltage, temper-
ature and package type. Same input signal level and
output load.
VID = 100 mV
Document #: 38-07057 Rev. *B
Page 4 of 8
ComLink™ Series
CY2DL814
Table 12.High Frequency Parametrics
Parameter
Fmax
Description
Conditions
Min.
–
Typ.
–
Max.
400
Unit
MHz
Maximum frequency
50% duty cycle tW(50–50)
V
DD = 3.3V
Standard Load Circuit.
Fmax(20)
Maximum frequency
20% duty cycle tW(50–50)
–
1
–
–
200
–
MHz
ns
VDD = 3.3V
LVPECL Input
V
IN = VIH(Max.)/VIL(Min.)
VOUT = VOH(Min.)/VOL (Max.) (Limit)
TW
Minimum pulse
VDD = 3.3V
LVPECL Input
VIN = VIH(Max.)/VIL(Min.) F= 100 MHz
VOUT = VOH(Min.)/VOL(Max.)(Limit)
A
TPA
50
Pulse
10pF
TPC
Generator
B
50
TPB
Standard Termination
V1A
1.4 V
1.2 V CM
0V Differential
V1B
1.0 V
V0Y
1.4 V
1.2 V CM
0V Differential
1.0 V
V0Z
TPLH
TPHL
80%
0V Differential
V0Y - V0Z
20%
tR
tF
Figure 1. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3, 4, 5, 6]
A
TPA
50
TPC
50
Pulse
Generator
B
TPB
VOC
VOD
Standard Termination
Next Device
VI(A)
VI(B)
2.0V
1.6V
Figure 2. Test Circuit and Voltage Definitions for the Driver Common-mode Output Voltage[3, 4, 5, 6]
Notes:
3. All input pulses are supplied by a frequency generator with the following characteristics: t and t ≤ 1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns.
R
F
4. RL= 50 ohm ± 1% Zline = 50 ohm 6”.
5. CL includes instrumentation and fixture capacitance within 6 mm of the UT.
6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to V
.
DD- 2
Document #: 38-07057 Rev. *B
Page 5 of 8
ComLink™ Series
CY2DL814
A
B
TPA
50
Pulse
10pF
TPC
Generator
50
TPB
Standard Termination
100%
80%
VI(A)
VI(B)
1.4V
1.0V
0.0V
20%
0%
tF
tR
Figure 3. Test Circuit and Voltage Definitions for the Differential Output Signal[3, 4, 5, 6]
IN P U T
A
L V P E C L
L V D S
&
L V C M O S / L V T T L
IN P U T
G N D
B
I n C o n f i g
L V D S / L V P E C L
In C o n fig
L V T T L /L V C M O S
0
1
Figure 4. LVCMOS/LVTTL Single-ended Input Value[7]
Figure 5. LVPECL or LVDS Differential Input Value[8]
Ordering Information
Part Number
Package Type
16-pin TSSOP
Product Flow
Industrial, –40°C to 85°C
CY2DL814ZI
CY2DL814ZIT
CY2DL814SI
CY2DL814SIT
CY2DL814ZC
CY2DL814ZCT
CY2DL814SC
CY2DL814SCT
Lead-free
16-pin TSSOP–Tape and Reel
16-pin SOIC
16-pin SOIC–Tape and Reel
16-pin TSSOP
16-pin TSSOP–Tape and Reel
16-pin SOIC
16-pin SOIC–Tape and Reel
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Commercial, 0°C to 70 °C
Commercial, 0°C to 70 °C
Commercial, 0°C to 70 °C
Commercial, 0°C to 70 °C
CY2DL814ZXI
CY2DL814ZXIT
CY2DL814SXI
CY2DL814SXIT
CY2DL814ZXC
CY2DL814ZXCT
CY2DL814SXC
16-pin TSSOP
16-pin TSSOP–Tape and Reel
16-pin SOIC
16-pin SOIC–Tape and Reel
16-pin TSSOP
16-pin TSSOP–Tape and Reel
16-pin SOIC
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
Commercial, 0°C to 70 °C
Commercial, 0°C to 70 °C
Commercial, 0°C to 70 °C
Commercial, 0°C to 70 °C
CY2DL814SXCT
16-pin SOIC–Tape and Reel
Notes:
7. LVCMOS/LVTTL single ended input value. Ground either input: when on the B side then non-inversion takes place. If A side is grounded, the signal becomes
the complement of the input on B side. See Table 4.
8. LVPECL or LVDS differential input value.
Document #: 38-07057 Rev. *B
Page 6 of 8
ComLink™ Series
CY2DL814
Package Drawing and Dimensions
16 Lead (150 Mil) SOIC
16-Lead (150-Mil) SOIC S16.15
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.010[0.254]
0.016[0.406]
X 45°
0.386[9.804]
0.393[9.982]
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
51-85068-*B
16-lead TSSOP 4.40 mm Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05 gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
ComLink is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-07057 Rev. *B
Page 7 of 8
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
ComLink™ Series
CY2DL814
Document Title: ComLink™ Series CY2DL814 1:4 Clock Fanout Buffer
Document Number: 38-07057
Issue
Orig. of
REV.
**
*A
ECN NO.
115362
122744
384077
Date
Change
Description of Change
07/10/02
12/14/02
See ECN
EHX
RBI
RGL
New Data Sheet
Added power up requirements to maximum ratings information.
Added Lead-free devices
*B
Added typical values
Document #: 38-07057 Rev. *B
Page 8 of 8
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