CY2HH8110ACT [CYPRESS]
1.5V 1:10 HSTL Fanout Buffer; 1:10 1.5V HSTL扇出缓冲器
| 型号： | CY2HH8110ACT |
| 厂家： | 
CYPRESS |
| 描述： | 1.5V 1:10 HSTL Fanout Buffer |
| 文件： | 总7页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2HH8110
1.5V 1:10 HSTL Fanout Buffer
Features
Description
• DC to 150-MHz operation
• 1.5V power supply
The CY2HH8110 is a low-voltage HSTL fanout buffer
designed for data communications, clock management, and
specialty memory applications.
• One single-ended HSTL input
• Ten single-ended Class II HSTL outputs
• Less than 1.9% Duty Cycle distortion
• Balanced 16-mA output drive
• Output Enable/Disable
• Low output-output skew
• Operating temperature range: 0°C to +85°C
• 32-pin TQFP package
The class II HSTL outputs are balanced Push-Pull in design
capable of delivering 16 mA into 10 pF load. This class allows
both source series termination and symmetrically double
parallel termination.
The CY2HH8110 low-output duty cycle distortion makes it
suitable for Double Data Rate (DDR) applications.
Block Diagram
Pin Configuration
Q 1
Q 2
32 31 30 29 28 27 26 25
VDD
GND
GND
Q4
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
Q5
VDD
OE
IN
VDD
VDD
Q6
CY2HH8110
GND
IN
Q 9
Q 10
Q7
VDD
GND
GND
OE
9 10 11 12 13 14 15 16
Cypress Semiconductor Corporation
Document #: 38-07556 Rev **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 1, 2003
CY2HH8110
Pin Description[1]
Pin
Name
I/O
Type
HSTL
Description
6
IN
I
HSTL reference clock input
HSTL clock outputs
30, 27, 26, 23, 22, 19, 18, Q(1:10)
15, 14, 11
O
HSTL
4
OE
I, PD
LVCMOS
Output enable/disable input. When held
LOW, outputs are enabled. When set HIGH, all
outputs are disabled LOW.
1, 3, 7, 12, 13, 20, 21, 28, VDD
29
Supply
Supply
VDD
1.5V power supply[2]
2, 5, 8, 9, 10, 16, 17, 24, GND
25, 31, 32
Ground
Common ground
Notes:
1. PD = Internal pull down.
2. A 0.1-uF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the trace.
Document #: 38-07556 Rev **
Page 2 of 7
CY2HH8110
Absolute Maximum Conditions
Parameter
VDD
Description
DC Supply Voltage
Condition
Functional
Min.
–0.5
1.35
-0.5
Max.
Unit
V
2.5
1.65
VDD
DC Operating Voltage
DC Input Voltage
V
VIN
Relative to VSS, with or VDD
applied
VDD + 0.5
V
VOUT
VTT
LU
DC Output Voltage
Relative to VSS
–0.5
200
VDD + 0.5
V
V
Output termination Voltage
Latch Up Immunity
VDD ÷ 2
Functional
mA
mVp-p
°C
RPS
TS
Power Supply Ripple
Ripple Frequency < 100 kHz
Non-functional
Functional
150
Temperature, Storage
–65
0
+150
+85
+150
42
TA
Temperature, Operating Ambient
Temperature, Junction
°C
TJ
Functional
°C
ØJC
ØJA
ESDH
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Functional
°C/W
°C/W
V
Functional
105
ESD Protection (Human Body
Model)
1600
FIT
Failure in Time
Manufacturing test
10
ppm
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications (VDD = 1.5V ± 8%, TA = 0°C to +85°C)
Parameter
VIL
Description
Input Voltage, Low
Condition
Min.
Typ.
–
Max.
Unit
V
HSTL input, VREF = 0.75V
–0.30
0.65
VIH
Input Voltage, High
0.85
–
1.80
V
VIL
Input Voltage, Low
OE# input
-0.30
–
0.3 * VDD
V
VIH
Input Voltage, High
0.7 * VDD
–
VDD + 0.3
V
VOL
VOH
IIL
Output Voltage, Low[3]
Output Voltage, High[3]
Input Current, Low[4]
Input Current, High[4]
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Output Pin Capacitance
Output Impedance
IOL = 16 mA
-0.3
1.0
–
–
0.4
V
IOH = –16 mA
–
VDD + 0.3
V
VIL = VSS
–
–10
100
1
µA
µA
mA
mA
pF
pF
Ω
IIH
VIH = VDD
–
–
IDDQ
IDD
VIN = 0V, outputs disabled
Outputs loaded @ 62.5 MHz
–
–
–
215
–
250
6
CIN
–
COUT
ZOUT
–
4.5
25
6
–
–
AC Electrical Specifications (VDD = 1.5V ± 8%, TA = 0°C to +85°C) [5]
Parameter
Description
Input Frequency
Condition
Min.
–
Typ.
Max.
Unit
MHz
V
fin
–
–
–
–
–
–
150
VIL(AC)
VIH(AC)
tr , tf
AC Input HIGH Voltage
AC Input LOW Voltage
Output rise/fall time[6]
Output duty cycle
VREF =VDD/2,InternalVoltage
Reference
0.95
–
0.55
1.5
52
V
20% to 80%
0.3
48
ns
DC
Fout < 100 MHz
Fout > 100 MHz
%
45
55
Notes:
3. Driving 50Ω series terminated or symmetrically double parallel terminated transmission line to a termination voltage of VTT
.
4. Inputs have pull-down resistors that affect the input current.
5. AC characteristics apply for series or parallel output termination to VTT. Parameters are guaranteed by characterization and are not 100% tested.
6. tr/tf times are faster with parallel terminated loads.
Document #: 38-07556 Rev **
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CY2HH8110
AC Electrical Specifications (VDD = 1.5V ± 8%, TA = 0°C to +85°C) (continued)[5]
Parameter
tjit_DCD
Description
Condition
Min.
Typ.
Max.
Unit
Output Duty Cycle Distortion
Measure Jitter delay between
input and output at VDD/2 @
fREF = 62.5 MHz
–
–
|300|
ps
DCD @ fREF = 62.5 MHz
–
–
–
–
–
–
–
–
–
–
|1.9|
200
2
%
ps
ns
ns
ns
ns
ns
ps
tsk(O)
tsk(pp)
tPLH
Output-to-Output Skew
Part-to-Part Skew
–
Propagation Delay, Low to High
Propagation Delay, High to Low
Output Disable Time
–
7
tPHL
–
7
tQoff
–
7
tQon
Output Enable Time
–
7
tJIT(CC)
Cycle-to-Cycle Jitter, Deterministic
jitter
10
50
Parameter Measurement Information
Output
tjit_D(cc)
Figure 1. Cycle-to-Cycle Jitter
80%
20%
Input
Output
80%
20%
tPLH & tPHL
Figure 2. Propagation Delay from Input Reference to Output n
O u tp u t n
O u tp u t m
tsk(0 )
Figure 3. Output to Output Skew
O E
Q n
tQ o n
tQ o ff
Figure 4. Output Enable/Disable Time
Document #: 38-07556 Rev **
Page 4 of 7
CY2HH8110
VTT = VDDQ / 2
RT = 50 ohm
RT
RT
50 ohm
Cload = 10pf
Figure 5. An Example HSTL Symmetrically Double Parallel Terminated Output Load |
and CLASS II HSTL AC Test Load [7,8]
Cload = 10pF
25 ohm
50 ohm
Figure 6. An Example HSTL Source Series Terminated Output Load[7,8]
Ordering Information
Part Number
CY2HH8110AC
Package Type
Product Flow
32-pin TQFP
32-pin TQFP – Tape and Reel
Commercial, 0°C to +85°C
CY2HH8110ACT
Notes:
7. HSTL to HSTL input.
8. Cload includes probe and test board capacitance.
Document #: 38-07556 Rev **
Page 5 of 7
CY2HH8110
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32
51-85063-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07556 Rev **
Page 6 of 7
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2HH8110
Document History Page
Document Title:CY2HH8110 1.5V 1:10 HSTL Fanout Buffer
Document Number: 38-07556
Orig. of
REV.
ECN No. Issue Date Change
Description of Change
**
128398
08/04/03
RGL
New Data Sheet
Document #: 38-07556 Rev **
Page 7 of 7
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