CY2PP326AI [CYPRESS]
2 x 2 Clock and Data Switch Buffer; 2×2的时钟和数据交换缓冲区
| 型号： | CY2PP326AI |
| 厂家： | 
CYPRESS |
| 描述： | 2 x 2 Clock and Data Switch Buffer |
| 文件： | 总9页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FastEdge™ Series
CY2PP326
2 x 2 Clock and Data Switch Buffer
Features
Functional Description
The CY2PP326 is a low-skew, low propagation delay 2 x 2
differential clock, data switch, and fanout buffer targeted to
meet the requirements of high-performance clock and data
distribution applications. The device is implemented on SiGe
technology and has a fully differential internal architecture that
is optimized to achieve low-signal skews at operating
frequencies of up to 1.5 GHz.
• Six ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 250 ps device-to-device skew
• 950 ps propagation delay (typical)
• 1.2 GHz Operation
• 2.8 ps RMS period jitter (max.)
• PECLmodesupplyrange:VEE=–2.5V±5%to–3.3V±5%
with VEE = 0V
• ECL mode supply range: VCC = 2.5V± 5% to 3.3V±5%
with VEE = 0V
• Industrial temperature range: –40°C to 85°C
• 32-pin 1.4mm TQFP package
The device features two differential input paths which are mul-
tiplexed internally to six outputs grouped in two banks. The
muxes are controlled by SEL(0:1) control inputs. The
CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and
as a clock/data repeater or multiplexer.
Since the CY2PP326 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems and for switching data signals
between different channels. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2PP326 delivers consistent, guaranteed
performance over differing platforms.
• Temperature compensation like 100K ECL
• Pin Compatible with MC100ES6254
Pin Configuration
Block Diagram
VCC
Bank A
Bank B
QA0
QA0#
CLK0
0
CLK0#
QA1
QA1#
1
QA2
29
28
32 31
25
27 26
30
VEE
QA2#
VCC
VEE
SEL1
CLK1
CLK1#
OEB#
VEE
1
2
3
24
VCC
VEE
OEA#
CLK0
CLK0#
VCC
23
22
21
20
19
QB0
QB0#
CLK1
0
4
CLK1#
CY2PP326
QB1
5
6
7
8
QB1#
1
VEE
QB2
SEL0
VEE
VCC
QB2#
18
17
VCC
SEL0
SEL1
12
9
10
13
16
14 15
11
VEE
VEE
OEA#
OEB#
Sync
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07506 Rev.*D
Revised July 28, 2004
FastEdge™ Series
CY2PP326
Pin Definitions
Pin
Name
I/O[1]
Type[2]
Description
19,3
22,6
21,4
20,5
SEL0,SEL1
OEA#,OEB#
CLK(0:1)
I
LVCMOS Clock/Data Switch Select.
LVCMOS Output Enable.
ECL/PECL True Differential Inputs.
ECL/PECL Complement Differential Inputs.
ECL/PECL Differential Outputs – Bank A.
I
I,PD
I,PD/PU
O
CLK(0:1)#
31,28,25
QA(0:2)
32,29,26
QA(0:2)#
10,13,16
9,12,15
QB(0:2)
O
ECL/PECL Differential Outputs – Bank B.
QB(0:2)#
2,7,18,23,
1,8,11,14,17,24,27,30
VEE
VCC
–PWR
+PWR
GND
Negative Power Supply.
POWER Positive Power Supply.
Table 1. Function Table
Control
OAE#
Default
0
0
1
QA(0–2), QX(0–2)# are active. Deassertion of OE# QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can
can be asynchronous to the reference clock without be asynchronous to the reference clock without
generation of output runt pulses.
generation of output runt pulses.
OEB#
0
QA(0–2), QX(0–2)are active. Deassertion of OE# QA(0–2)= L, QX(0–2)# = H. Assertion of OE# can
can be asynchronous to the reference clock without be asynchronous to the reference clock without
generation of output runt pulses.
generation of output runt pulses.
SEL0,SEL1 00
See Table 2
Table 2. Clock Select Control
SEL0
SEL1
CLK0 Routed to
QA(0:2) and QB(0:2)
CLK1 Routed to
Application Mode
1:6 fanout of CLK0
1:6 fanout of CLK1
Dual 1:3 buffer
0
0
1
1
0
1
0
1
–
QA(0:2) and QB(0:2)
QB(0:2)
–
QA(0:2)
QB(0:2)
QA(0:2)
Dual 1:3 buffer crossed
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP326. The agency name and relevant specification is
listed below in Table 3.
Table 3.
Agency Name
JEDEC
Specification
JESD 020B (MSL)
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–B (skew,jitter)
Mil-Spec
883E Method 1012.1 (Thermal Theta JC)
Notes:
1. In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-Down, PU for Pull-Up, and PWR for Power
2. In ECL mode (negative power supply mode), V is either –3.3V or –2.5V and V is connected to GND (0V). In PECL mode (positive power supply mode),
EE
CC
V
is connected to GND (0V) and V is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
)
EE
CC
CC
and are between V and V
.
EE
CC
Document #: 38-07506 Rev.*D
Page 2 of 9
FastEdge™ Series
CY2PP326
Absolute Maximum Ratings
Parameter
VCC
VEE
TS
TJ
ESDh
MSL
Description
Condition
Non-Functional
Non-Functional
Non-Functional
Non-Functional
Human Body Model
Min.
–0.3
-4.6
–65
Max.
4.6
0.3
+150
150
Unit
V
V
°C
°C
V
N.A.
gates
Positive Supply Voltage
Negative Supply Voltage
Temperature, Storage
Temperature, Junction
ESD Protection
2000
3
50
Moisture Sensitivity Level
Gate Count Total Number of Used Gates
Assembled Die
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Operating Conditions
Parameter
LUI
TA
ØJc
ØJa
IEE
CIN
LIN
VIN
VTT
VOUT
IIN
Description
Latch Up Immunity
Condition
Functional, typical
Functional
Functional
Functional
Min.
Max.
Unit
mA
°C
°C/W
°C/W
mA
pF
nH
V
V
100
Temperature, Operating Ambient
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Maximum Quiescent Supply Current
Input pin capacitance
–40
+85
29[3]
75[3]
VEE pin
130 [4]
3
1
Pin Inductance
[5]
Input Voltage
Relative to VCC
Relative to VCC
Relative to VCC
–0.3
–0.3
VCC + 0.3
VCC – 2
VCC + 0.3
[5]
Output Termination Voltage
Output Voltage
[5]
V
uA
Input Current[6]
VIN = VIL, or VIN = VIH
l150l
PECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VCC
Operating Voltage
2.5V ± 5%, VEE = 0.0V
2.375
2.625
V
3.3V ± 5%, VEE = 0.0V
3.135
3.465
V
VCMR
VOH
VOL
Differential Cross Point Voltage[7]
Output High Voltage
Differential operation
IOH = –30 mA[8]
1.2
VCC – 1.25
VCC
VCC – 0.7
V
V
Output Low Voltage
I
OL = –5 mA[8]
V
CC = 3.3V ± 5%
VCC – 1.995
VCC –1.995
V
CC – 1.5
V
V
V
V
VCC = 2.5V ± 5%
Input Voltage, High
Input Voltage, Low
VCC – 1.3
VCC – 0.880 [9]
VCC – 1.625
VIH
VIL
Single-ended operation
Single-ended operation
VCC – 1.165
VCC – 1.945 [9]
Notes:
3. Theta JA EIA JEDEC 51 test board conditions (typical value); Theta JC 883E Method 1012.1
4. Power Calculation: V * I +0.5 (I + I ) (V – V ) (number of differential outputs used); I does not include current going off chip.
CC
EE
OH
OL
OH
OL
EE
5. where V is 3.3V±5% or 2.5V±5%
CC
6. Inputs have internal pull-up/pull-down or biasing resistors which affect the input current.
7. Refer to Figure 1
8. Equivalent to a termination of 50Ω to VTT. I
=(V
-V )/50; I
=(V
-V )/50; I
=(V
-V )/50; I
=(V
-V )/50;
OLMAX TT
OHMIN
OHMIN TT
OHMAX
OHMAX TT
OLMIN
OLMIN TT
OLMAX
9. V will operate down to V ; V will operate up to V
CC
IL
EE
IH
Document #: 38-07506 Rev.*D
Page 3 of 9
FastEdge™ Series
CY2PP326
ECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VEE
Negative Power Supply
–2.5V ± 5%, VCC = 0.0V
–2.625
–2.375
V
–3.3V ± 5%, VCC = 0.0V
–3.465
–3.135
VCMR
VOH
VOL
Differential cross point voltage[7]
Output High Voltage
Differential operation
IOH = –30 mA[8]
VEE + 1.2
–1.25
0V
–0.7
V
V
Output Low Voltage
I
OL = –5 mA[8]
V
EE = –3.3V ± 5%
–1.995
–1.995
–1.5
–1.3
V
V
EE = –2.5V ± 5%
VIH
VIL
Input Voltage, High
Input Voltage, Low
Single-ended operation
Single-ended operation
–1.165
–0.880 [9]
–1.625
V
V
–1.945 [9]
AC Electrical Specifications
Parameter
VPP
FCLK
TPD
Description
Condition
Differential operation
50% duty cycle Standard load
< 1 GHz [10]
Min.
0.1
–
Max.
1.3
1.5
Unit
V
GHz
ps
Differential Input Voltage[7]
Input Frequency
Propagation Delay CLKA or CLKB to
–
1200
Output pair
Vo
Output Voltage (peak-to-peak; see Fig- < 1 GHz
ure 2)
0.375
–
V
VCMRO
tsk(0)
tsk(PP)
TPER
Output Common Voltage Range (typ.)
VCC – 1.425
V
Output-to-output Skew
Part-to-Part Output Skew
Output Period Jitter (rms)[11]
Output Pulse Skew[12]
660 MHz [10], See Figure 3
–
–
–
–
50
250
2.8
75
ps
ps
ps
ps
660 MHz [10]
660 MHz [10]
tsk(P)
660 MHz [10], See Figure 3
TR,TF
Output Rise/Fall Time (see Figure 2)
660 MHz 50% duty cycle
Differential 20% to 80%
0.08
0.3
ns
tPDL
tPLD
Output disable time
Output enable time
T = CLK period
T = CLK period
2.5T + TPD
3.0T + TPD
3.5T + TPD
4.0T + TPD
ns
ns
S p litte r O p tio n s
R o u te r O p tio n s
S E L 0 /1
S E L 0 /1
C L K 0 /0 #
B a n k
B a n k
A
B
C L K 0 /0 #
B a n k
B a n k
A
C L K 1 /1 #
C L K 1 /1 #
B
S p litte r A
S w itc h
C L K 0 /0 #
C L K 1 /1 #
B a n k
B a n k
A
B
B a n k
A
B
C L K 0 /0 #
C L K 1 /1 #
B a n k
R e p e a te r
S p litte r B
S E L 0 /1
S E L 0 /1
Figure 1. Channel Cross Point Switch/Mux Configurations
Notes:
10. 50% duty cycle; standard load; differential operation
11. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
12. Output pulse skew is the absolute difference of the propagation delay times: | t
– t
|.
PHL
PLH
Document #: 38-07506 Rev.*D
Page 4 of 9
FastEdge™ Series
CY2PP326
Timing Definitions
VCC
VIH
VCMR Max = VCC
VPP range
0.1V - 1.3V
VPP
VCMR
VIL
VCMR Min = VEE + 1.2
VEE
Figure 2. PECL/ECL Input Waveform Definitions
tr, tf,
VO
20-80%
Figure 3. ECL/LVPECL Output
I n p u t
C l o c k
V P P
T P L H ,
T P D
T P H L
O
u t p u t
C l o c k
V O
t S K ( O
)
A n o t h e r
O
u t p u t
C l o c k
Figure4. PropagationDelay(TPD), outputpulseskew(|tPLH-tPHL|), andoutput-to-outputskew(tSK(O)
)
for both CLKA or CLKB to Output Pair, PECL/ECL to PECL/ECL
Document #: 38-07506 Rev.*D
Page 5 of 9
FastEdge™ Series
CY2PP326
CLKX
CLKX
2
3
2
3
1
1
50%
OEX
tPDL(OE[X] to Q[X}
tPLD(OE[X] to Q[X}
Q[X]
Q[X]#
Figure 5.
Test Configuration
Standard test load using a differential pulse generator and
differential measurement instrument.
V T T
V T T
R T = 50 ohm
R T = 50 ohm
5 "
P ulse
G enerator
Z o = 50 ohm
Z o = 50 ohm
Z = 50 ohm
5 "
D U T
R T = 50 ohm
C Y 2P P 326
R T = 50 ohm
V T T
V T T
Figure 6. CY2PP326 AC Test Reference
Applications Information
Termination Examples
V T T
C Y 2 P P 3 2 6
V C C
R T = 5 0 o h m
5 "
Z o = 50 o hm
5 "
R T = 5 0 o h m
V T T
V E E
Figure 7. Standard LVPECL – PECL Output Termination
Document #: 38-07506 Rev.*D
Page 6 of 9
FastEdge™ Series
CY2PP326
V T T
C Y 2 P P 3 2 6
R T = 5 0 o h m
V C C
5 "
Z o = 5 0 o h m
5 "
V T T
R T = 5 0 o h m
V B B (3 .3 V )
V E E
Figure 8. Driving a PECL/ECL Single-ended Input
3 .3 V
C Y 2 P P 3 2 6
V C C = 3 .3 V
1 2 0 o h m
L V D S
5 "
3 3 o h m
Z o = 5 0 o h m
(2 p la c e s )
5 "
1 2 0 o h m
5 1 o h m
(2 p la c e s )
3 .3 V
L V P E C L to
L V D S
V E E = 0 V
Figure 9. Low-voltage Positive Emitter-coupled Logic (LVPECL) to a Low-voltage Differential Signaling (LVDS) Inter-
face
VDD-2
X
VCC
Y
Z
One output is shown for clarity
Figure 10. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms,
and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other
signalling standards and supplies.
Ordering Information
Part Number
Package Type
Product Flow
Industrial, –40° to 85°C
Industrial, –40° to 85°C
CY2PP326AI
32-pin TQFP
CY2PP326AIT
32-pin TQFP – Tape and Reel
Document #: 38-07506 Rev.*D
Page 7 of 9
FastEdge™Series
CY2PP326
Package Drawing and Dimensions
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
Dimensions in mm.
51-85088-*B
FastEdge is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
Document #: 38-07506 Rev.*D
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
FastEdge™ Series
CY2PP326
Document History Page
Document Title: CY2PP326 FastEdge™ Series 2 x 2 Clock and Data Switch Buffer
Document Number: 38-07506
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
122361
02/12/03
RGL
New Data Sheet
*A
129269
09/09/03
RGL
Changed ComLink to FastEdge
Added tPLDg and tPDLf specs in the AC specs table
Added the Output disable/enabling timing diagram
Deleted the output reference voltage in the absolute max. conditions
Fixed the AC/DC Electrical specs to match the EROS
*B
*C
*D
131346
237751
247620
11/20/03
See ECN
RGL
RGL
Posted to external web
Supplied data to all TBD’s to match the device.
See ECN RGL/GGK Changed VOH and VOL to match the Char Data
Document #: 38-07506 Rev.*D
Page 9 of 9
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