CY2X0147FLXIT_技术文档

CY2X014

CY2X0147

Low-Jitter LVPECL Crystal Oscillator

Features

Functional Description

■ Low-jitter crystal oscillator (XO)

The CY2X014/CY2X0147 device is a high-performance and

high-frequency XO. The device uses a Cypress proprietary

low-noise PLL to synthesize the frequency from an integrated

crystal.

■ Less than 1 ps typical root mean square (RMS) phase jitter

■ Low-voltage positive emitter coupled logic (LVPECL) output

■ Output frequency from 50 MHz to 690 MHz

■ Factory-configured or field-programmable

■ Integrated phase-locked loop (PLL)

The CY2X014/CY2X0147 device is available as

a

factory-configured device or as a field-programmable device.

Factory-configured devices are configured for general use or

they can be customer-specific. The same CY2X014/CY2X0147

can be configured as four different device types as mentioned in

the Logic Block Diagram.

■ Can be configured as four different devices

■ Supply voltage: 3.3 V or 2.5 V

For a complete list of related documentation, click here.

■ Pb-free chip carrier (LCC): 5.0 mm × 3.2 mm for CY2X014 and

7.0 mm × 5.0 mm for CY2X0147

■ Commercial and industrial temperature ranges

Cypress Semiconductor Corporation

Document Number: 001-88287 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 8, 2018

CY2X014

CY2X0147

Logic Block Diagram

4

CRYSTAL

LOW- NOISE

PLL

CLK

OSCILLATOR

Device Type 1: High-performance

LVPECL crystal oscillator with Output

Enable

OUTPUT

DIVIDER

5

CLK#

PROGRAMMABLE

CONFIGURATION

1

OE/PD#

6

3

V_DD

V_SS

4

CRYSTAL

OSCILLATOR

LOW-NOISE

PLL

CLK

Device Type 2: High-performance

LVPECL crystal oscillator with

frequency margining - I²C control

OUTPUT

DIVIDER

5

CLK#

PROGRAMMABLE

CONFIGURATION

1

I²C

SDA

2

INTERFACE

SCL

4

5

CLK

Device Type 3:

Crystal

Oscillator

Output

Divider

High-performance LVPECL

crystal oscillator with frequency

margining - Frequency Select

Low-Noise PLL

CLK#

FS1

1

2

Frequency Select

Decode

FS0

CRYSTAL

OSCILLATOR

LOW-NOISE

4

5

CLK

PLL

OUTPUT

DIVIDER

Device Type 4:

CLK#

High-performance LVPECL

voltage-controlled crystal

oscillator

1

2

VIN

PROGRAMMABLE

CONFIGURATION

OE/PD#

6

3

VDD

VSS

Document Number: 001-88287 Rev. *F

Page 2 of 21

CY2X014

CY2X0147

Contents

Pinout ................................................................................4

Pin Definitions ..................................................................4

Functional Overview ........................................................5

Device Type 1 .............................................................5

Device Type 2 .............................................................5

Device Type 3 .............................................................5

Device Type 4 .............................................................5

Programming Description ...............................................6

Field-Programmable CY2X014F/CY2X0147F .............6

Factory Configured CY2X014/CY2X0147 ...................6

Programming Variables ...................................................6

Output Frequency ........................................................6

Pin 1: Output Enable (OE) or Power-Down (PD#) ......6

Industrial versus Commercial Device Performance ....6

Absolute Pull Range ....................................................6

Memory Map ......................................................................7

Serial Interface Protocol and Timing ...........................7

Device Address ...........................................................8

Data Valid ....................................................................8

Data Frame .................................................................8

Acknowledge Pulse .....................................................9

Write Operations ...............................................................9

Writing Individual Bytes ...............................................9

Writing Multiple Bytes ..................................................9

Read Operations ...............................................................9

Current Address Read .................................................9

Random Read .............................................................9

Sequential Read ..........................................................9

Serial Programming Interface

Timing Specifications ....................................................10

Absolute Maximum Conditions .....................................11

Operating Conditions .....................................................11

DC Electrical Characteristics ........................................12

Termination Circuits .......................................................12

AC Electrical Characteristics ........................................13

Switching Waveforms ....................................................14

Typical Output Characteristics .....................................15

Ordering Information ......................................................16

Possible Configurations .............................................16

Ordering Code Definitions .........................................16

Package Diagrams ..........................................................17

Acronyms ........................................................................19

Document Conventions .................................................19

Units of Measure .......................................................19

Document History Page .................................................20

Sales, Solutions, and Legal Information ......................21

Worldwide Sales and Design Support .......................21

Products ....................................................................21

PSoC® Solutions ......................................................21

Cypress Developer Community .................................21

Technical Support .....................................................21

Document Number: 001-88287 Rev. *F

Page 3 of 21

CY2X014

CY2X0147

Pinout

Figure 1. 6-pin Ceramic LCC pinout

Device Type 4: High

Device Type 1: High

Device Type 3: High

Performance LVPECL

Crystal Oscillator with

Frequency Margining -

Frequency Select

Device Type 2: High

Performance LVPECL

Crystal Oscillator with

Frequency Margining - I²C

control

Performance LVPECL

Voltage Controlled Crystal

Oscillator

Performance LVPECL

CrystalOscillator withOutput

Enable:

VIN 1

OE/PD# 2

VSS 3

6 VDD

5 CLK#

4 CLK

SDA 1

6 V_DD

FS1 1

FS0 2

VSS 3

6 VDD

OE/PD# 1

DNU 2

6 V_DD

SCLK 2

5 CLK#

4 CLK

5 CLK#

4 CLK

5 CLK#

4 CLK

V_SS

3

V_SS

3

Pin Definitions

6-pin Ceramic LCC

Name

Device Type 1 Device Type 2 Device Type 3 Device Type 4 I/O Type

Description

OE/PD#

1

N/A

2

CMOS Output enable pin: Active HIGH. If

input

OE = 1, CLK is enabled.

Power-down pin: Active LOW. If

PD# = 0, the device is powered

down and the clock is disabled. The

functionality

of

this

is

programmable

CLK,

CLK#

4,5

2

4,5

LVPECL Differential output clock

output

DNU

N/A

–

Do not use: DNU pins are electrically

connected but perform no function

V_DD

V_SS

6

3

6

3

6

3

6

3

Power Supply voltage: 2.5 V or 3.3 V

Power Ground

FS1, FS0

N/A

1,2

N/A

CMOS Frequency Select

input

SDA

N/A

1

2

N/A

I/O

I²C Serial Data

SCLK

CMOS I²C Serial Clock

input

VIN

N/A

1

Analog VCXO control voltage, positive slope

input

Document Number: 001-88287 Rev. *F

Page 4 of 21

CY2X014

CY2X0147

Figure 2 shows how the frequency words are arranged and

selected.

Functional Overview

Device Type 1

Device Type 1 is a simple crystal oscillator with one output

frequency. Pin 1 can be programmed either as OE or PD#. The

OE function is used to enable or disable the CLK output whereas

the PD# function places the device in a low-power state.

Figure 2. Frequency Words

Register

Address

00

01

10

11

10h – 15h

16h – 1Bh

1Ch – 21h

22h – 27h

Frequency Word 0

Frequency Word 1

Frequency Word 2

Frequency Word 3

Device Type 2

Device Type 2 has an I²C bus serial interface ^[1], which is used

to change the output frequency.

Control

PLL

Sel

Bits [1:0]

The CY2X014/CY2X0147 device is configured for four

frequencies. At power-on, the four configurations are

transparently loaded into an internal volatile memory which, in

turn, controls the PLL. The user can switch between the four

frequencies through the I²C bus. The user can also configure the

CY2X014/CY2X0147 with new output frequencies by shifting

new data into the internal memory.

40h

Select Byte

Device Type 3

The FS0 and FS1 pins select between four different output

frequencies, as shown in Table 1. Frequency margining is a

common application for this feature. One frequency is used for

the standard operating mode of the device, while the other

frequencies are available for margin testing, either during

product development or in-system manufacturing test.

Frequency margining is a common application for this feature.

One frequency is used for the standard operating mode of the

device, while additional frequencies are available for margin

testing, either during product development or in-system

manufacturing test.

Table 1. Frequency Select

Note that all configuration changes made using I²C are

temporary and are lost when power is removed from the device.

At power-on, the device returns to its original state.

FS1

0

FS0

0

Output Frequency

Frequency 0

0

1

Frequency 1

Frequency 2

Frequency 3

The configuration for a particular frequency is stored in a 6-byte

block of memory, known as a word. The CY2X014/CY2X0147

device has four such words, labeled ‘Frequency Word 0’ through

‘Frequency Word 3’. An additional register byte contains a 2-bit

field, which selects one of the four frequency words. By writing

to this select byte, the user can switch back and forth between

the four programmed frequencies. The select byte can be

configured to select any of the four frequency words at power-on.

1

0

1

When changing the output frequency, the frequency transition is

not guaranteed to be smooth. There can be frequency

excursions beyond the start frequency and the new frequency.

Glitches and runt pulses are possible, and time must be allowed

for the PLL to relock.

When changing the output frequency, the frequency transition is

not guaranteed to be smooth. There can be frequency

excursions beyond the start frequency and the new

frequency.Glitches and runt pulses are possible, and time must

be allowed for the PLL to relock.

If more than four frequencies are needed, the I²C bus can be

used to change any of the four frequency words. When writing

frequency words through I²C, the users should not change the

currently selected word. Instead, write one of the three

unselected words before changing the select byte to select that

new word.

Device Type 4

Device Type 4 is a voltage-controlled crystal oscillator. It has a

control voltage pin, VIN, which is an analog input used to adjust

the output frequency. The nominal output frequency is defined

when VIN = VDD,NOM/2. Increasing the voltage on VIN

increases the output frequency, while decreasing the voltage on

VIN decreases the output frequency. Any voltage between VSS

and VDD is allowed on VIN. The voltage or frequency slope is

very linear over most of the control voltage range.

Note

2

1. The serial interface is I C Bus compliant with the following exceptions: SDA input leakage current, SDA input capacitance, SDA, and SCLK are clamped to V

,

DD

setup time, and output hold time.

Document Number: 001-88287 Rev. *F

Page 5 of 21

CY2X014

CY2X0147

Programming Description

Programming Variables

CY2X014/CY2X0147 is a programmable device. Prior to being

used in an application, it must be programmed with the output

frequency and other variables described in Programming

Variables. Two device types are available, each with its own

programming flow. They are described in the following sections.

Output Frequency

The CY2X014/CY2X0147 device can synthesize a frequency to

a resolution of one part per million (ppm) but the actual accuracy

of the output frequency is limited by the accuracy of the

integrated reference crystal.

Field-Programmable CY2X014F/CY2X0147F

The CY2X014/CY2X0147 has an output frequency range of

50 MHz to 690 MHz, but the range is not continuous. The

CY2X014/CY2X0147 cannot generate frequencies in the ranges

of 521 MHz to 529 MHz and 596 MHz to 617 MHz.

Field-programmable devices are shipped unprogrammed and

must be programmed before being installed on a PCB.

Customers use the CyClockWizard™ software to specify the

device configuration and generate a joint electron devices

engineering council (JEDEC - extension .jed) programming file.

Programming of samples and prototype quantities is available

using the CyClockWizard software along with

CY3675-CLKMAKER1 CyClockMaker Clock Programmer Kit

and CY3675-LCC6B socket adapter. Cypress’s value-added

Pin 1: Output Enable (OE) or Power-Down (PD#)

This function is only available in Device Type 1 and 4. Pin 1

(Device Type 1) or Pin 2 (Device type 2) is programmed as either

OE or PD#. The OE function is used to enable or disable the CLK

output quickly, but it does not reduce core power consumption.

The PD# function places the device in a low-power state, but the

wake-up takes longer because the PLL must reacquire the lock.

a

distribution

partners

also

provide

programming

services. Field-programmable devices are designated with an ‘F’

in the part number. They are intended for quick prototyping and

inventory reduction. You can generate JEDEC for these four

devices using CyClockWizard 1.0. However, while creating

JEDEC or programming different device types, select different

MPNs in the CyClockWizard 1.0 software (seeTable 2.

Industrial versus Commercial Device Performance

Industrial and commercial devices have different internal

crystals. They have

a potentially significant impact on

performance levels for applications requiring the lowest possible

phase noise. The CyClockWIzard 1.0 software allows the user

to select between, and view the expected performance of, both

options.

You can download the software and programmer kit hardware

from www.cypress.com by clicking the hyperlinks in the previous

paragraph.

Table 2. MPNs selection on CyClockWizard 1.0 Software

Absolute Pull Range

This is only applicable for Device Type 4. The pull range of the

VCXO, measured in parts per million (ppm) is programmable.

The configuration software allows the user to select one of seven

possible absolute pull ranges (APR), ranging up to

approximately ±200 ppm. APR is the net pull range of the device,

after subtracting frequency variability due to device variation,

and temperature, voltage, and aging effects.

Device Type

Device Type 1

Device Type 2

Device Type 3

MPN selection on CyClockWizard 1.0

CY2X014

CY2XF24

CY2XF34

Contact Local Cypress FAE

Table 3. Device Programming Variables

Factory Configured CY2X014/CY2X0147

For ready-to-use devices, the

CY2X014/CY2X0147 device is available for samples or orders,

or you can request for a custom configuration. All requests are

submitted to the local Cypress field application engineer (FAE)

or sales representative. After the request is processed, the user

receives a new part number, samples, and datasheet with the

programmed values. This part number is used for additional

Variable

Output frequency

Device Type

Device Type 1 and 4

Device Type 1

preconfigured

Pin 1 function (OE or PD#)

Temperature range

Device Type 1, 2, 3 and 4

(commercial or industrial)

Output frequency 0

Output frequency 1

Output frequency 2

Output frequency 3

Absolute pull range

Pin 2 function (OE or PD#)

Device Type 2 and 3

Device Type 4

sample

requests

and

production

orders.

The

CY2X014/CY2X0147 device is one-time programmable (OTP).

Device Type 4

Document Number: 001-88287 Rev. *F

Page 6 of 21

CY2X014

CY2X0147

Memory Map

Table 5. Register 40h: Select Byte

Default Value

Five fields can be written via the I²C bus. Four frequency words

define the output frequency. As shown in Table 4, each of these

words is a 6-byte field. When writing to a frequency word, all six

bytes should be written. They may be written either as individual

byte writes or as a block write. The currently selected frequency

word should not be written to. All four words are symmetrical,

meaning that a 6-byte value that is valid for one word is also valid

for any of the other words, and produces the same frequency.

Bits

Name

Description

(binary)

7:2 000000

Reserved

Reserved. Always write

this value.

1:0 User-defined Word select Selects the Frequency

Word to determine the

output frequency. 00

selectsWord0;01selects

Word 1; 10 selects Word

2; 11 selects Word 3.

The fifth field is the select byte, located at byte address 40h. The

value written into the two least significant bits determines the

active frequency word. The other bits of the byte are reserved

and must be written with the values indicated in the table. Users

should never write to any address other than the 25 bytes

described here.

Serial Interface Protocol and Timing

The CY2X014/CY2X0147 device uses the SDA and SCLK pins

for an I²C bus that operates up to 100 kbits/sec in read or write

mode. The CY2X014/CY2X0147 device is always a slave on this

bus, meaning that it never initiates a bus transaction. The basic

write protocol is as follows:

Table 4. Frequency Words

Frequency

Word

Word Select

(Select Byte 40h)

Byte Addresses (hex)

0

1

2

3

10h to 15h

16h to 1Bh

1Ch to 21h

22h to 27h

00

01

10

11

Start Bit: 7-bit Device Address (DA); R/W Bit; Slave Clock

Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit

Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in

MA+2; ACK; and so on, until STOP Bit. The basic serial format

is illustrated in Figure 3.

Figure 3. Data Frame Architecture

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

R/W = 0

SDA Write

Multiple

Contiguous

Registers

7-bit

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

Device

Address

Register Register Register

Address Data

Data

(XXH+1)

(XXH)

(XXH+2)

(FFH)

(00H)

Stop Signal

Start Signal

1 Bit

Slave

ACK

1 Bit

Slave

ACK

1 Bit

Master

NACK

1 Bit

R/W = 1

SDA Read

7-bit

Device

Address

Current

Address

Read

8-bit

Register

Data

Stop Signal

Start Signal

1 Bit

Slave

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Master

ACK

1 Bit

Slave

ACK

1 Bit

Master

NACK

1 Bit

R/W = 0

SDA Read

Multiple

Contiguous

Registers

7-bit

Device

Address

8-bit

7-bit

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

8-bit

Register

Data

Register Device

Address

(XXH)

Address

+R/W=1

(XXH)

(XXH+1)

(FFH)

(00H)

Stop Signal

Start Signal

Repeated

Start bit

Document Number: 001-88287 Rev. *F

Page 7 of 21

CY2X014

CY2X0147

Device Address

Data Valid

The device I²C address is a 7-bit value. The default I²C address,

which appears in CyClockWizard is 69H, which can be changed

to any other value while generating configuration using

CyClockWizard. Note that the default address of the

field-programmable (unprogrammed^[2]) devices is 69H.

Data is valid when the clock is HIGH and may only be

transitioned when the clock is LOW, as illustrated in Figure 4.

Figure 4. Data Valid and Data Transition Periods

Transition

to next Bit

Data Valid

SDAT

SCLK

t_SU:DAT

t_HD:DAT

t_HIGH

VIH

VIL

t_LOW

followed by the register address (eight bits) and register data

(eight bits).

Data Frame

Every new data frame is indicated by a start and stop sequence,

as illustrated in Figure 5.

STOP Sequence - Stop frame is indicated by SDA going HIGH

when SCLK is HIGH. A stop frame frees the bus for writing to

another part on the same bus or writing to another random

register address.

START Sequence - Start frame is indicated by SDA going LOW

when SCLK is HIGH. Every time a start signal is given, the next

8-bit data must be the device address (seven bits) and a R/W bit,

Figure 5. Start and Stop Frame

SDA

SCLK

Transition

to next Bit

START

STOP

Note

2. Field-programmable devices are shipped unprogrammed and must be programmed before being installed on a PCB. An unprogrammed device will output the crystal

frequency of the integrated crystal (25 MHz for commercial and 38.8 MHz for industrial).

Document Number: 001-88287 Rev. *F

Page 8 of 21

CY2X014

CY2X0147

cycle as illustrated in Figure 6 (N = the number of bytes

transmitted). After the data packet is sent during read mode, the

master generates the acknowledge.

Acknowledge Pulse

During write mode, the CY2X014/CY2X0147 device responds

with an Acknowledge (ACK) pulse after every eight bits. This is

accomplished by pulling the SDA line LOW during the N*9^thclock

Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data)

SDA

+

START

D7

D6

D1

D0

DA6

DA5 DA0

R/W

ACK

RA7

RA6 RA1

RA0

ACK

STOP

+

SCLK

bit set to a ‘1’, the CY2X014/CY2X0147 device issues an ACK

and transmits the 8-bit word. The master device does not

acknowledge the transfer, but does generate a STOP condition,

which causes the CY2X014/CY2X0147 device to stop trans-

mission.

Write Operations

Writing Individual Bytes

A valid write operation must have a full 8-bit register address

after the device address word from the master, which is followed

by an ACK bit from the slave (SDA = 0/LOW). The next eight bits

must contain the data word intended for storage. After the data

word is received, the slave responds with another ACK bit

(SDA = 0/LOW), and the master must end the write sequence

with a STOP condition.

Random Read

Through random read operations, the master may access any

memory location. To perform this type of read operation, first the

word address must be set. This is accomplished by sending the

address to the CY2X014/CY2X0147 device as part of a write

operation. After the word address is sent, the master generates

a START condition following the acknowledge. This terminates

the write operation before any data is stored in the address, but

not before the internal address pointer is set. Next, the master

reissues the control byte with the R/W byte set to ‘1’. The

CY2X014/CY2X0147 then issues an acknowledge and transmits

the 8-bit word. The master device does not acknowledge the

transfer but does generate a STOP condition which causes the

CY2X014/CY2X0147 device to stop transmission.

Writing Multiple Bytes

To write more than one byte at a time, the master does not end

the write sequence with a stop condition. Instead, the master can

send multiple contiguous bytes of data to be stored. After each

byte, the slave responds with an acknowledge bit, just like after

the first byte, and accepts data until the ACK bit is responded to

by the STOP condition. When receiving multiple bytes, the

CY2X014/CY2X0147 internally increments the register address.

Read Operations

Sequential Read

Sequential read operations follow the same process as random

reads except that the master issues an ACK instead of a STOP

condition after transmission of the first 8-bit data word. This

action results in an incrementing of the internal address pointer

and subsequently output of the next 8-bit data word. By

continuing to issue acknowledges instead of STOP conditions,

the master may serially read the entire contents of the slave

device memory. When the internal address pointer points to the

FFh register, after the next increment, the pointer will point to the

00h register.

Read operations are initiated the same way as write operations

except that the R/W bit of the slave address is set to ‘1’ (HIGH).

There are three basic read operations: current address read,

random read, and sequential read.

Current Address Read

The CY2X014/CY2X0147 has an onboard address counter that

retains 1 more than the address of the last word access. If the

last word written or read was word ‘n’, then a current address

read operation would return the value stored in location ‘n+1’.

When the CY2X0147 receives the slave address with the R/W

Document Number: 001-88287 Rev. *F

Page 9 of 21

CY2X014

CY2X0147

Serial Programming Interface Timing Specifications

Parameter

f_SCLK

Description

Min

–

Max

100

–

Unit

kHz

s

Frequency of SCLK

t_HD:STA

Hold time START condition

4.0

t_LOW

t_HIGH

t_SU:STA

t_HD:DAT

t_SU:DAT

t_R

Low period of the SCLK clock

High period of the SCLK clock

4.7

4.0

4.7

200

1000

–

s

ns

s

Setup time for a repeated START condition

Data hold time

–

Data setup time

–

Rise time

300

–

t_F

Fall time

–

t_SU:STO

t_BUF

Setup time for STOP condition

Bus-free time between STOP and START conditions

4.0

4.7

–

Figure 7. Definition for Timing on the Serial Bus

SDAT

t_f

t_LOW

t_r

t_SU;DAT

t_f

t_HD;STA

t_r

t_BUF

SCLK

t_HD;STA

t_SU;STA

t_SU;STO

t_HD;DAT

t_HIGH

P

S

Sr

Document Number: 001-88287 Rev. *F

Page 10 of 21

CY2X014

CY2X0147

Absolute Maximum Conditions

Parameter

Description

Supply voltage

Condition

Min

–0.5

–55

Max

Unit

V

4.4

DD

[3]

Input voltage, DC

Relative to V

V

+ 0.5

DD

V

IN

SS

T

Temperature, storage

Temperature, junction

Non operating

135

–

°C

V

S

J

–40

ESD

Electrostatic discharge (ESD)

protection human body model

(HBM)

JEDEC Std 22-A114-B

2000

HBM

[4]

JA



Thermal resistance, junction to 0 m/s airflow

ambient

64

°C /

W

Operating Conditions

Parameter

Description

Min

3.0

Typ

3.3

2.5

–

Max

3.6

Unit

V

3.3 V supply voltage range

2.5 V supply voltage range

DD

2.375

0.05

2.625

500

V

T

Power-up time for V to reach minimum specified voltage (power

ms

PU

DD

ramp is monotonic)

T

Ambient temperature (commercial)

Ambient temperature (industrial)

0

–

70

85

°C

A

–40

Notes

3. The voltage on any input or I/O pin cannot exceed the power pin during power-up.

4. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 × 114 × 1.6 mm and has 4 layers of copper (2/1/1/2 oz.). The internal layers

are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.

Document Number: 001-88287 Rev. *F

Page 11 of 21

CY2X014

CY2X0147

DC Electrical Characteristics

Parameter

Description

Condition

Min

Typ

Max

Unit

[5]

I

Operating supply current

V

= 3.6 V, CLK = 150 MHz, output

DD

–

150

mA

DD

terminated,

OE/PD#=V

DD

V

= 2.625 V, CLK = 150 MHz,

–

145

mA

DD

output terminated,

OE/PD#=V

DD

A

I

Standby supply current

PD# = V

–

200

SB

SS

V

LVPECL high output voltage

V

R

= 3.3 V or 2.5 V,

V

- 1.15

V

- 0.75

DD

OH

DD

= 50  to V - 2.0V

TERM

DD

V

LVPECL low output voltage

V

R

= 3.3 V or 2.5 V,

V

- 2.0

–

V

- 1.625

OL

DD

= 50  to V - 2.0V

TERM

DD

mV

V

LVPECL output voltage swing

V

R

= 3.3 V or 2.5 V,

600

1000

OD1

OD2

OCM

DD

(V – V

)

= 50  to V - 2.0V

OH

OL

TERM

DD

LVPECL output voltage swing

(V – V

V

R

= 2.5 V,

500

1.2

1000

–

DD

)

= 50  to V - 1.5V

OH

OL

TERM

DD

LVPECL output common mode

voltage (V + V )/2

V

R

= 2.5 V,

DD

= 50  to V - 1.5V

OH

OL

TERM

DD

A

V

I

LVPECL output leakage current PD#/OE = V

Input high voltage

–35

–

35

–

OZ

SS

V

0.7 × V

IH

DD

V

Input low voltage

–

0.3 × V

115

50

IL

DD

A

pF

I

Input high current

Input low current

Input capacitance

Input = V

–

IH

IL

DD

SS

–

C

15

–

IN

Termination Circuits

Figure 8. LVPECL Termination

V_DD– 2 V or V_DD- 1.5 V

(V_DD= 2.5 V)

V_DD– 2 V

(V_DD= 3.3 V)



CLK

CLK#

Note

5.

I

includes ~24 mA of current that is dissipated externally in the output termination resistors.

DD

Document Number: 001-88287 Rev. *F

Page 12 of 21

CY2X014

CY2X0147

AC Electrical Characteristics

[6]

The following table lists the AC electrical specifications for this device.

Parameter

Description

Condition

Min

50

–

Typ

–

Max

690

±35

Unit

MHz

ppm

[7]

F

Output frequency

OUT

FSC

FSI

AG

Frequency stability, commercial

V

= min to max,

T = 0 °C to 70 °C

–

DD

[8]

devices

A

Frequency stability, industrial

V

= min to max,

T = –40 °C to 85 °C

–

±55

ppm

DD

[8]

devices

A

Aging, 10 years

–

±15

55

ppm

%

T

Output duty cycle

F < 450 MHz,

45

50

DC

measured at zero crossing

F > 450 MHz,

40

50

60

%

measured at zero crossing

T , T

Output rise and fall time

Output disable time

20% and 80% of full output swing

0.2

–

0.4

–

1.0

ns

R

F

T

Time from falling edge on OE to

stopped outputs (asynchronous)

100

OHZ

T

Output enable time

Startup time

Time from rising edge on OE to

–

100

10

ns

OE

outputs at

a

valid frequency

(asynchronous)

T

Time for CLK to reach valid

frequency measured from the time

ms

LOCK

V

= V (min) or from PD# rising

DD

edge

Relock time

Time for CLK to reach valid

frequency from serial bus change to

select bits in register 40h, measured

–

1

–

ms

ps

LSER

2

from I C STOP (Device Type 2) or

Time for CLK to reach valid

frequency from FS0 or FS1 pin

change (Device Type 3)

T

RMS phase jitter (random)

F

= 106.25 MHz

OUT

Jitter()

(12 kHz to 20 MHz)

Notes

6. Not 100% tested, guaranteed by design and characterization.

7. This parameter is specified in the CyClockWizard 1.0 software.

8. Frequency stability is the maximum variation in frequency from F . It includes initial accuracy, and variation from temperature and supply voltage.

0

Document Number: 001-88287 Rev. *F

Page 13 of 21

CY2X014

CY2X0147

Switching Waveforms

Figure 9. Output Voltage Swing

V_A

V_B

CLK

V_OD

V_OCM= (V_A+ V_B)/2

CLK#

Figure 10. Duty Cycle Timing

CLK

T_PW

T_DC

=

T_PERIOD

CLK#

T_PW

T_PERIOD

Figure 11. Output Rise and Fall Time

CLK#

80% 80%

20%

CLK

T_R

T_F

Figure 12. Output Enable and Disable Timing

V_IH

OE

V_IL

T_OHZ

T_OE

CLK

High-Impedance

CLK#

Document Number: 001-88287 Rev. *F

Page 14 of 21

CY2X014

CY2X0147

Typical Output Characteristics

Figure 13. 2.5 V Supply and Termination to V_DD–1.5 V, Minimum V_DDand Maximum T_A

0.9

0.8

0.7

0.6

0.5

0.4

1.40

1.35

1.30

1.25

1.20

0

100

200

300

400

500

600

700

0

100

200

300

400

500

600

700

Frequency (MHz)

Figure 14. 2.5 V Supply and Termination to V_DD–2 V, Minimum V_DDand Maximum T_A

0.9

0.8

0.7

0.6

0.5

0.4

0.90

0.85

0.80

0.75

0.70

0

100

200

300

400

500

600

700

0

100

200

300

400

500

600

700

Frequency (MHz)

Figure 15. 3.3 V Supply and Termination to V_DD–2 V, Minimum V_DDand Maximum T_A

0.9

0.8

0.7

0.6

0.5

0.4

1.60

1.55

1.50

1.45

1.40

0

100

200

300

400

500

600

700

0

100

200

300

400

500

600

700

Frequency (MHz)

Document Number: 001-88287 Rev. *F

Page 15 of 21

CY2X014

CY2X0147

Ordering Information

Part Number

Pb-free

Configuration

Package Description

Product Flow

CY2X014FLXIT

CY2X0147FLXCT

CY2X0147FLXIT

Field-programmable

6-pin ceramic LCC SMD - Tape and Reel Industrial, –40 °C to 85 °C

6-pin ceramic LCC SMD - Tape and Reel Commercial, 0 °C to 70 °C

6-pin ceramic LCC SMD - Tape and Reel Industrial, –40 °C to 85 °C

Some product offerings are factory-programmed, customer-specific devices with customized part numbers. The Possible

Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales

representative for more information.

Possible Configurations

[9]

Part Number

Pb-free

Configuration

Package Description

6-pin ceramic LCC SMD

Product Flow

CY2X014LXCxxx

CY2X014LXCxxxT

CY2X014LXIxxx

Factory-configured

Commercial, 0 °C to 70 °C

6-pin ceramic LCC SMD - Tape and Reel Commercial, 0 °C to 70 °C

6-pin ceramic LCC SMD Industrial, –40 °C to 85 °C

6-pin ceramic LCC SMD - Tape and Reel Industrial, –40 °C to 85 °C

6-pin ceramic LCC SMD Commercial, 0 °C to 70 °C

6-pin ceramic LCC SMD - Tape and Reel Commercial, 0 °C to 70 °C

6-pin ceramic LCC SMD Industrial, –40 °C to 85 °C

6-pin ceramic LCC SMD - Tape and Reel Industrial, –40 °C to 85 °C

CY2X014LXIxxxT

CY2X0147LXCxxx

CY2X0147LXCxxxT

CY2X0147LXIxxx

CY2X0147LXIxxxT

Ordering Code Definitions

xxx

X

0147

X

L

CY 2X

X = blank or T

blank = Tube; T = Tape and Reel

Customer Part Configuration Code

Temperature Range: X = C or I

C = Commercial; I = Industrial

Pb-free

Package Type: L = 6-pin Ceramic LCC SMD

Configuration: X = F or blank

F = Field Programmable; blank = Factory Configured

Part Identifier

Family

Company ID: CY = Cypress

Note

9. “xxx” indicates factory-programmed parts based on customer-specific configurations. For more details, contact your local Cypress FAE or a sales representative.

Document Number: 001-88287 Rev. *F

Page 16 of 21

CY2X014

CY2X0147

Package Diagrams

Figure 16. 6-pin Ceramic LCC (5.0 × 3.2 × 1.30 mm) LZ06B Package Outline, 001-10044

001-10044 *C

Document Number: 001-88287 Rev. *F

Page 17 of 21

CY2X014

CY2X0147

Package Diagrams (continued)

Figure 17. 6-pin Ceramic LCC (5.0 × 7.0 × 1.80 mm) LZ06B Package Outline, 001-85862

001-85862 *A

Document Number: 001-88287 Rev. *F

Page 18 of 21

CY2X014

CY2X0147

Acronyms

Document Conventions

Units of Measure

Acronym

Description

Electrostatic discharge

Field application engineer

ESD

FAE

Symbol

°C

Unit of Measure

degree Celsius

megahertz

microampere

milliampere

millivolt

MHz

A

mA

mV

ms

ns

HBM

JEDEC

LCC

LVPECL

OE

Human Body Model

Joint Electron Devices Engineering Council

Leadless chip carrier

Low-voltage positive emitter coupled logic

Output Enable

millisecond

nanosecond

ohm

OTP

PCB

PLL

One-time programmable

Printed circuit board



ppm

pF

ps

parts per million

picofarad

picosecond

volt

Phase-locked loop

RMS

XO

Root mean square

Crystal oscillator

V

W

watt

Document Number: 001-88287 Rev. *F

Page 19 of 21

CY2X014

CY2X0147

Document History Page

Document Title: CY2X014/CY2X0147, Low-Jitter LVPECL Crystal Oscillator

Document Number: 001-88287

Orig. of

Change

Submission

Date

Rev.

ECN

Description of Change

**

3944886

4178261

4485619

4587303

CINM

SAMP

07/02/2013 New data sheet.

*A

*B

*C

10/30/2013 Changed status from Preliminary to Final.

08/27/2014 Replaced LVDS with LVPECL in all instances across the document.

12/05/2014 Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

Updated Memory Map:

Updated Serial Interface Protocol and Timing:

Updated Figure 3 (Changed the last ACK in SDA Read from “ACK” to “NACK”).

*D

4756544

XHT

05/06/2015 Updated Document Title to read as “CY2X014/CY2X0147, Low-Jitter LVPECL

Crystal Oscillator”.

Added CY2X014 related information in all instances across the document.

Updated Read Operations:

Removed figure “Data Transfer Sequence on the Serial Bus”.

Added Serial Programming Interface Timing Specifications.

Updated Ordering Information:

Updated part numbers.

Updated Possible Configurations:

Updated part numbers.

Updated Ordering Code Definitions.

Updated Package Diagrams:

Added spec 001-10044 Rev. *C.

Completing Sunset Review.

*E

*F

5435358

6063701

XHT

09/13/2016 Updated to new template.

Completing Sunset Review.

02/08/2018 Updated Ordering Information:

Updated part numbers.

Updated to new template.

Document Number: 001-88287 Rev. *F

Page 20 of 21

CY2X014

CY2X0147

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

®

Arm Cortex Microcontrollers

Automotive

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Memory

cypress.com/support

cypress.com/memory

cypress.com/mcu

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 001-88287 Rev. *F

Revised February 8, 2018

Page 21 of 21


型号：	CY2X0147FLXIT
厂家：	CYPRESS
描述：	LVPECL Output Clock Oscillator, 振荡器
文件：	总21页 (文件大小：400K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY2X0147FLXIT [CYPRESS]

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