CY2X014FLXCT [CYPRESS]
6-Pin Ceramic LCC SMD - Tape and Reel; 6引脚LCC陶瓷SMD - 磁带和卷轴
| 型号： | CY2X014FLXCT |
| 厂家： | 
CYPRESS |
| 描述： | 6-Pin Ceramic LCC SMD - Tape and Reel |
| 文件： | 总9页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2X014
Low Jitter LVPECL Crystal Oscillator
Features
Functional Description
■ Low Jitter Crystal Oscillator (XO)
The CY2X014 is a high performance and high frequency Crystal
Oscillator (XO). The device uses a Cypress proprietary low noise
PLL to synthesize the frequency from an embedded crystal.
■ Less than 1 ps Typical RMS Phase Jitter
■ Differential LVPECL Output
The CY2X014 is available as a factory configured device or as a
field programmable device.
■ Output Frequency from 50 MHz to 690 MHz
■ Factory Configured or Field Programmable
■ Integrated Phase-Locked Loop (PLL)
■ Output Enable or Power Down Function
■ Supply Voltage: 3.3V or 2.5V
■ Pb-Free Package: 5.0 x 3.2 mm LCC
■ Commercial and Industrial Temperature Ranges
Logic Block Diagram
4
CRYSTAL
OSCILLATOR
LOW-NOISE
CLK
PLL
OUTPUT
5
DIVIDER
CLK#
PROGRAMMABLE
CONFIGURATION
1
OE/PD#
6
3
VDD
VSS
Pinout
Figure 1. Pin Diagram - 6 Pin Ceramic LCC
OE/PD# 1
DNU 2
6 VDD
5 CLK#
4 CLK
VSS 3
Cypress Semiconductor Corporation
Document Number: 001-10179 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 12, 2009
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CY2X014
Table 1. Pin Definitions - 6 Pin Ceramic LCC
Pin
Name
OE/PD#
I/O Type
Description
1
CMOS Input
Output Enable Pin: Active HIGH. If OE = 1, CLK is enabled.
Power Down Pin: Active LOW. If PD# = 0, the device is powered down and the clock is
disabled. The functionality of this pin is programmable.
4, 5
2
CLK, CLK#
DNU
LVPECL Output Differential Output Clock
–
Do Not Use: DNU pins are electrically connected, but perform no function
6
VDD
Power
Power
Supply Voltage: 2.5V or 3.3V
Ground
3
VSS
Pin 1: Output Enable or Power Down (OE/PD#)
Programming Description
Pin 1 is programmed as either Output Enable (OE) or Power
Down (PD#). The OE function is used to enable or disable the
CLK output quickly, but it does not reduce core power
consumption. The PD# function puts the device into a low power
state, but the wake up takes longer because the PLL must
reacquire lock.
The CY2X014 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in a later section. Two
different device types are available, each with its own
programming flow. They are described in the following sections.
Field Programmable CY2X014F
Industrial vs. Commercial Device Performance
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyberClocks™ Online Software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using a Cypress programmer.
Third party vendors manufacture programmers for small to large
volume applications. Cypress’s value added distribution partners
also provide programming services. Field programmable
devices are designated with an “F” in the part number. They are
intended for quick prototyping and inventory reduction.
Industrial and Commercial devices have different internal
crystals. They have a potentially significant impact on perfor-
mance levels for applications requiring the lowest possible
phase noise. CyberClocks Online Software displays expected
performance for both options.
Phase Noise vs. Jitter Performance
In most cases, the device configuration for optimal phase noise
performance is different from the device configuration for optimal
cycle to cycle or period jitter. CyberClocks Online Software
includes algorithms to optimize performance for either
parameter.
The software is located at www.cyberclocksonline.com.
Table 2. Device Programming Variables
Factory Configured CY2X014
For ready-to-use devices, the CY2X014 is available with no field
programming required. All requests are submitted to the local
Cypress Field Application Engineer (FAE) or sales represen-
tative. After the request is processed, the user receives a new
part number, samples, and data sheet with the programmed
values. This part number is used for additional sample requests
and production orders. The CY2X014 is one time programmable
(OTP).
Variable
Output Frequency
Pin 1 Function (OE or PD#)
Optimization (Phase Noise or Jitter)
Temperature Range (Commercial or Industrial)
Programming Variables
Output Frequency
The CY2X014 can synthesize a frequency to a resolution of one
part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
The CY2X014 has an output frequency range of 50 MHz to 690
MHz, but the range is not continuous. The CY2X014 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz and
596 MHz to 617 MHz.
Document Number: 001-10179 Rev. *D
Page 2 of 9
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CY2X014
Absolute Maximum Conditions
Parameter
Description
Condition
Relative to VSS
Min
–0.5
–0.5
–55
Max
Unit
VDD
Supply Voltage
4.4
V
[1]
VIN
Input Voltage, DC
VDD+0.5
135
V
°C
TS
Temperature, Storage
Non operating
TJ
Temperature, Junction
–40
135
°C
ESDHBM
ESD Protection (Human Body Model)
Thermal Resistance, Junction to Ambient
JEDEC STD 22-A114-B
0 m/s airflow
2000
V
[2]
ΘJA
64
°C/W
Operating Conditions
Parameter
Description
Min
3.0
Typ
3.3
2.5
–
Max
3.6
Unit
V
VDD
3.3V Supply Voltage Range
2.5V Supply Voltage Range
2.375
0.05
2.625
500
V
TPU
TA
Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp
is Monotonic)
ms
Ambient Temperature (Commercial)
Ambient Temperature (Industrial)
0
–
–
70
85
°C
°C
–40
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
[3]
IDD
Operating Supply Current
VDD = 3.6V, CLK = 150 MHz, OE/PD# =
–
–
150
mA
VDD, output terminated
VDD=2.625V, CLK= 150MHz, OE/PD#
= VDD, output terminated
–
–
145
200
mA
ISB
Standby Supply Current
PD# = VSS
–
–
–
μA
VOH
LVPECL High Output Voltage
VDD = 3.3V or 2.5V, RTERM = 50Ω to
VDD – 1.15
VDD
–
V
VDD – 2.0V
0.75
VOL
LVPECL Low Output Voltage
LVPECL Output Voltage Swing
VDD = 3.3V or 2.5V, RTERM = 50Ω to
DD – 2.0V
VDD – 2.0
600
–
–
–
–
VDD
1.625
–
V
mV
mV
V
V
VOD1
VOD2
VOCM
VDD = 3.3V or 2.5V, RTERM = 50Ω to
DD – 2.0V
1000
1000
–
(VOH - VOL
LVPECL Output Voltage Swing
(VOH - VOL
)
V
VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V
500
)
LVPECL Output Common Mode
Voltage (VOH + VOL)/2
VDD = 2.5V, RTERM = 50Ω to VDD – 1.5V
1.2
IOZ
VIH
VIL
IIH
LVPECL Output Leakage Current PD#/OE = VSS
Input High Voltage
–35
–
–
35
μA
V
0.7*VDD
–
0.3*VDD
115
Input Low Voltage
–
–
–
–
–
V
Input High Current
Input Low Current
Input Capacitance
Input = VDD
Input = VSS
–
μA
μA
pF
IIL
–
50
CIN
15
–
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3.
I
includes ~24 mA of current that is dissipated externally in the output termination resistors.
DD
Document Number: 001-10179 Rev. *D
Page 3 of 9
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CY2X014
[4]
AC Electrical Characteristics
Parameter
FOUT
Description
Output Frequency[6]
Condition
Min
50
–
Typ
–
Max
690
±35
Unit
MHz
ppm
FSC
Frequency Stability, Commercial VDD = min to max, TA = 0°C to 70°C
Devices[5]
–
FSI
Frequency Stability, Industrial
Devices[5]
VDD = min to max, TA = –40° to 85°C
–
–
±55
ppm
AG
Aging, 10 Years
–
45
40
200
–
–
50
50
400
–
±15
55
ppm
%
TDC
Output Duty Cycle
F <= 450 MHz, measured at zero crossing
F > 450 MHz, measured at zero crossing
20% and 80% of full output swing
60
%
TR, TF
TOHZ
Output Rise and Fall Time
Output Disable Time
600
100
ps
Time from falling edge on OE to stopped
outputs (Asynchronous)
ns
TOE
Output Enable Time
Startup Time
Time from rising edge on OE to outputs at
a valid frequency (Asynchronous)
–
–
–
–
100
10
ns
TLOCK
Time for CLK to reach valid frequency
measured from the time
ms
VDD = VDD(min.) or from PD# rising edge
TJitter(φ)
RMS Phase Jitter (Random)
FOUT = 106.25 MHz (12 kHz to 20 MHz)
–
1
–
ps
Typical Output Characteristics
Figure 2. 2.5V Supply and Termination to VDD–1.5V, Minimum VDD and Maximum TA
0.9
0.8
0.7
0.6
0.5
0.4
1.40
1.35
1.30
1.25
1.20
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Frequency (MHz)
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. Frequency stability is the maximum variation in frequency from F . It includes initial accuracy, and variation from temperature and supply voltage.
0
6. This parameter is specified in CyberClocks Online software
Document Number: 001-10179 Rev. *D
Page 4 of 9
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CY2X014
Figure 3. 2.5V Supply and Termination to VDD–2V, Minimum VDD and Maximum TA
0.9
0.8
0.7
0.6
0.5
0.4
0.90
0.85
0.80
0.75
0.70
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Frequency (MHz)
Figure 4. 3.3V Supply and Termination to VDD–2V, Minimum VDD and Maximum TA
0.9
0.8
0.7
0.6
0.5
0.4
1.60
1.55
1.50
1.45
1.40
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Frequency (MHz)
Document Number: 001-10179 Rev. *D
Page 5 of 9
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CY2X014
Switching Waveforms
Figure 5. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 6. Duty Cycle Timing
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Figure 7. Output Rise and Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Figure 8. Output Enable and Disable Timing
VIH
OE
VIL
TOHZ
TOE
CLK
High Impedance
CLK#
Termination Circuits
Figure 9. LVPECL Termination
VDD - 2V
(VDD = 3.3V)
VDD - 2V or VDD - 1.5V
(VDD = 2.5V)
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
CLK
50Ω
50Ω
CLK
CLK#
CLK#
Document Number: 001-10179 Rev. *D
Page 6 of 9
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CY2X014
Ordering Information
Part Number[7]
Configuration
Package Description
Product Flow
Pb-Free
CY2X014FLXCT
CY2X014FLXIT
CY2X014LXCxxxT
CY2X014LXIxxxT
Field Programmable
Field Programmable
Factory Configured
Factory Configured
6-Pin Ceramic LCC SMD - Tape and Reel
6-Pin Ceramic LCC SMD - Tape and Reel
6-Pin Ceramic LCC SMD - Tape and Reel
6-Pin Ceramic LCC SMD - Tape and Reel
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Industrial, –40° to 85°C
Package Diagram
Figure 10. 6-Pin 3.2x5.0 mm Ceramic LCC LZ06A
2.54 TYP.
SIDE VIEW
0.64 TYP.
TYP.
0.10 R REF.
TYP.
0.20 R REF.
5.0
0.32 R
INDEX
4
5
6
7
10
9
8
1
3
2
0.45 REF.
TOP VIEW
BOTTOM VIEW
Dimensions in mm
General Tolerance: 0.15MM
001-10044-**
Kyocera dwg ref KD-VA6432-A
Package Weight ~ 0.12 grams
.
Note
7. “xxx” is a factory assigned code that identifies the programming option.
Document Number: 001-10179 Rev. *D
Page 7 of 9
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CY2X014
Document History Page
Document Title: CY2X014 Low Jitter LVPECL Crystal Oscillator
Document Number: 001-10179
Orig. of Submission
Rev. ECN No.
Description of Change
Change
Date
**
504478
RGL
See ECN New data sheet
*A
1428603 JWK/SFV
See ECM Removed pull up on pin 1 and related specifications, Added items to Programming
Variables section, Added CIN specification, Modified tJ2, IIH, IIL, IDD and ISB specifi-
cations, Changed to a single Frequency Stability specification, Removed
Peak-to-peak Period Jitter specification, Changed pin 2 from NC to DNU, Changed
max storage temperature, Title change, 2.5V supply tightened from ±10% to ±5%,
2.5V termination option changed from VDD-1.4V to VDD-1.5V, Added typical output
characteristic curves
*B
*C
2669117 KVM/AESA
2701663 KVM/PYRS
03/05/09 Revised frequency stability and aging specs and conditions, Max frequency changed
from 700 MHz to 690 MHz, Duty cycle changed from 45/55 to 40/60 for freq > 450
MHz, Removed reference to CY3672 programmer, Junction and storage tempera-
tures changed from 125 to 135°C, IIH changed from 20μA to 115μA, IIL changed from
20μA to 50μA, Rise and fall times changed from 350 ps to 500 ps, Removed MSL
spec, Changed Data Sheet Status to Final.
05/06/09 General clean up
Added explanation of gaps in the frequency range
Added URL for software
Removed frequency stability paragraph under Programming Variables
Added programming variables table
Added separate IDD spec for 2.5V supply
Changed the amount of load current in IDD footnote
Changed phase jitter parameter name
Removed supply voltage as a programming variable
Changed conditions for ESD spec
Changed rise & fall times from 500 ps to 400 ps typ, added min and max
*D
2718433 WWZ/HMT
06/12/09 No change. Submit to ECN for product launch.
Document Number: 001-10179 Rev. *D
Page 8 of 9
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CY2X014
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
psoc.cypress.com
clocks.cypress.com
wireless.cypress.com
memory.cypress.com
image.cypress.com
psoc.cypress.com/solutions
psoc.cypress.com/low-power
psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
psoc.cypress.com/usb
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-10179 Rev. *D
Revised June 12, 2009
Page 9 of 9
CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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