CY2X014LXI159T_12 [CYPRESS]
Low Jitter LVPECL Crystal Oscillator; 低抖动LVPECL晶体振荡器
| 型号： | CY2X014LXI159T_12 |
| 厂家： | 
CYPRESS |
| 描述： | Low Jitter LVPECL Crystal Oscillator |
| 文件： | 总15页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2X014
Low Jitter LVPECL Crystal Oscillator
Low Jitter LVPECL Crystal Oscillator
Features
Functional Description
■ Low jitter crystal oscillator (XO)
The CY2X014 is a high-performance and high-frequency XO.
The device uses a Cypress proprietary low-noise PLL to
synthesize the frequency from an embedded crystal.
■ Less than 1 ps typical root mean square (RMS) phase jitter
■ Differential low-voltage positive emitter coupled logic
(LVPECL) output
The CY2X014 is available as a factory-configured device or as
a field-programmable device. Factory-configured devices are
configured
for
general
use
(see
Standard
and
■ Output frequency from 50 MHz to 690 MHz
■ Factory-configured or field-programmable
■ Integrated phase-locked loop (PLL)
Application-Specific Factory Configurations) or they can be
customer specific.
■ Output enable or power-down function
■ Supply voltage: 3.3 V or 2.5 V
■ Pb-free package: 5.0 x 3.2 mm leadless chip carrier (LCC)
■ Commercial and industrial temperature ranges
Logic Block Diagram
4
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
CLK
OUTPUT
DIVIDER
5
CLK#
PROGRAMMABLE
CONFIGURATION
1
OE/PD#
6
3
VDD
VSS
Cypress Semiconductor Corporation
Document Number: 001-10179 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 5, 2012
CY2X014
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Standard and Application-Specific
Switching Waveforms ....................................................10
Termination Circuits .......................................................10
Ordering Information ......................................................11
Possible Configurations .............................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................13
Document Conventions .................................................13
Units of Measure .......................................................13
Document History Page .................................................14
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support .......................15
Products ....................................................................15
PSoC Solutions .........................................................15
Factory Configurations ....................................................4
Programming Description ...............................................5
Field-programmable CY2X014 ....................................5
Factory-configured CY2X014 ......................................5
Programming Variables ...................................................5
Output Frequency ........................................................5
Pin 1: Output Enable (OE) or Power Down (PD#) .......5
Industrial versus Commercial Device Performance ....5
Absolute Maximum Conditions .......................................6
Operating Conditions .......................................................6
DC Electrical Characteristics ..........................................7
AC Electrical Characteristics ..........................................8
Typical Output Characteristics .......................................9
Document Number: 001-10179 Rev. *H
Page 2 of 15
CY2X014
Pin Configurations
Figure 1. 6-pin Ceramic LCC pinout
OE/PD# 1
DNU 2
6 VDD
5 CLK#
4 CLK
VSS
3
Pin Definitions
Pin
Name
I/O Type
Description
1
OE/PD#
CMOS input Output enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power-down pin: Active LOW. If PD# = 0, the device is powered down and the clock
is disabled. The functionality of this pin is programmable.
4, 5
2
CLK, CLK# LVPECL output Differential output clock
DNU
VDD
VSS
–
Do not use: DNU pins are electrically connected, but perform no function
6
Power
Power
Supply voltage: 2.5 V or 3.3 V
3
Ground
Document Number: 001-10179 Rev. *H
Page 3 of 15
CY2X014
Standard and Application-Specific Factory Configurations
RMS Phase Jitter (Random)
Offset Range Jitter (Typical)
Part Number
Output Frequency
Pin 1 Function
CY2X014LXI106T
CY2X014LXI122T
CY2X014LXI125T
106.25 MHz
122.88 MHz
125.00 MHz
OE
OE
OE
637 kHz to 10 MHz
12 kHz to 20 MHz
0.54 ps
0.81 ps
1.875 MHz to 20 MHz
12 kHz to 20 MHz
0.34 ps
0.84 ps
CY2X014LXI132T
132.8125 MHz
OE
1.875 MHz to 20 MHz
637 kHz to 10 MHz
0.36 ps
0.52 ps
CY2X014LXI153T
CY2X014LXI155T
153.60 MHz
155.52 MHz
OE
OE
12 kHz to 20 MHz
0.78 ps
250 kHz to 5 MHz
12 kHz to 5 MHz
12 kHz to 20 MHz
0.46 ps
0.49 ps
0.52 ps
CY2X014LXI156T
CY2X014LXI159T
CY2X014LXI212T
156.25 MHz
159.375 MHz
212.50 MHz
OE
OE
OE
1.875 MHz to 20 MHz
1.875 MHz to 20 MHz
0.31 ps
0.31 ps
2.55 MHz to 20 MHz
637 kHz to 10 MHz
0.31 ps
0.47 ps
CY2X014LXI311T
CY2X014LXI312T
CY2X014LXI622T
311.04 MHz
312.50 MHz
622.08 MHz
OE
OE
OE
12 kHz to 20 MHz
0.45 ps
0.29 ps
1.875 MHz to 20 MHz
12 kHz to 20 MHz
20 kHz to 80 MHz
50 kHz to 80 MHz
4 MHz to 80 MHz
0.42 ps
0.44 ps
0.44 ps
0.19 ps
Document Number: 001-10179 Rev. *H
Page 4 of 15
CY2X014
Programming Description
Programming Variables
The CY2X014 is a programmable device. Prior to being used in
an application, it must be programmed with the output frequency
and other variables described in Programming Variables. Two
different device types are available, each with its own
programming flow. They are described in the following sections.
Output Frequency
The CY2X014 can synthesize a frequency to a resolution of one
part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
Field-programmable CY2X014
The CY2X014 has an output frequency range of 50 MHz to
690 MHz, but the range is not continuous. The CY2X014 cannot
generate frequencies in the ranges of 521 MHz to 529 MHz and
596 MHz to 617 MHz.
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyClockWizard™ software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using the CyClockWizard
software along with a CY3675-CLKMAKER1 CyClockMaker
Clock Programmer Kit with a CY3675-LCC6A socket adapter.
Cypress’s value-added distribution partners also provide
programming services. Field-programmable devices are
designated with an ‘F’ in the part number. They are intended for
quick prototyping and inventory reduction.
Pin 1: Output Enable (OE) or Power Down (PD#)
Pin 1 is programmed as either OE or PD#. The OE function is
used to enable or disable the CLK output quickly, but it does not
reduce core power consumption. The PD# function puts the
device into a low power state, but the wake-up takes longer
because the PLL must reacquire the lock.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
The software and programmer kit hardware can be downloaded
from www.cypress.com by clicking the hyperlinks in the previous
paragraph.
crystals. They have
a potentially significant impact on
performance levels for applications requiring the lowest-possible
phase noise. CyClockWIzard software allows the user to select
between and view the expected performance of both options.
Factory-configured CY2X014
For ready-to-use devices, the CY2X014 is available with no field
programming required. Pre-configured devices (see Standard
and Application-Specific Factory Configurations) are available
for samples or orders, or a request for a custom configuration
can be made. All requests are submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. After
the request is processed, the user receives a new part number,
samples, and datasheet with the programmed values. This part
number is used for additional sample requests and production
orders. The CY2X014 is one-time programmable (OTP).
Table 1. Device Programming Variables
Variable
Output frequency
Pin 1 function (OE or PD#)
Temperature range (commercial or industrial)
Document Number: 001-10179 Rev. *H
Page 5 of 15
CY2X014
Absolute Maximum Conditions
Parameter
VDD
Description
Supply voltage
Condition
Min
–0.5
–0.5
–55
Max
4.4
Unit
V
[1]
VIN
TS
TJ
Input voltage, DC
Relative to VSS
Non operating
VDD + 0.5
135
V
Temperature, storage
Temperature, junction
°C
°C
V
–40
135
ESDHBM
Electrostatic discharge (ESD)
protection human body model
(HBM)
JEDEC STD 22-A114-B
2000
–
[2]
JA
Thermal resistance, junction to 0 m/s airflow
ambient
64
°C/W
Operating Conditions
Parameter
Description
Min
3.0
Typ
3.3
2.5
–
Max
3.6
Unit
V
VDD
3.3-V supply voltage range
2.5-V supply voltage range
2.375
0.05
2.625
500
V
TPU
TA
Power-up time for VDD to reach minimum specified voltage (power
ramp is monotonic)
ms
Ambient temperature (commercial)
Ambient temperature (industrial)
0
–
–
70
85
°C
°C
–40
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document Number: 001-10179 Rev. *H
Page 6 of 15
CY2X014
DC Electrical Characteristics
Parameter
Description
Condition
Min
Typ
Max
Unit
[3]
IDD
Operating supply current
VDD = 3.6 V, CLK = 150 MHz,
–
–
150
mA
OE/PD# = VDD
,
output terminated
VDD = 2.625 V, CLK = 150 MHz,
–
–
145
mA
OE/PD# = VDD
,
output terminated
ISB
Standby supply current
PD# = VSS
–
–
–
200
A
VOH
LVPECL high output voltage
VDD = 3.3 V or 2.5 V,
V
DD – 1.15
VDD – 0.75
V
RTERM = 50 to VDD – 2.0 V
VOL
LVPECL low output voltage
VDD = 3.3 V or 2.5 V,
R
VDD – 2.0
600
–
–
–
–
VDD – 1.625
V
mV
mV
V
TERM = 50 to VDD – 2.0 V
VDD = 3.3 V or 2.5 V,
TERM = 50 to VDD – 2.0 V
DD = 2.5 V,
RTERM = 50 to VDD – 1.5 V
LVPECL output common mode VDD = 2.5 V,
voltage (VOH + VOL)/2 TERM = 50 to VDD – 1.5 V
VOD1
VOD2
VOCM
LVPECL output voltage swing
1000
1000
–
(VOH – VOL
LVPECL output voltage swing
(VOH – VOL
)
R
V
500
)
1.2
R
IOZ
VIH
VIL
IIH
LVPECL output leakage current PD#/OE = VSS
Input high voltage
–35
–
–
35
A
V
0.7 × VDD
–
Input low voltage
–
–
–
–
–
0.3 × VDD
V
Input high current
Input low current
Input capacitance
Input = VDD
Input = VSS
–
115
50
–
A
A
pF
IIL
–
CIN
15
Note
3.
I
includes ~24 mA of current that is dissipated externally in the output termination resistors.
DD
Document Number: 001-10179 Rev. *H
Page 7 of 15
CY2X014
AC Electrical Characteristics
The following table lists the AC electrical specifications for this device.
Parameter [4]
FOUT
Description
Output frequency [5]
Condition
Min
50
–
Typ
–
Max
690
±35
Unit
MHz
ppm
FSC
Frequency stability, commercial VDD = min to max,
–
devices [6]
TA = 0 °C to 70 °C
FSI
Frequency stability, industrial
devices [6]
VDD = min to max,
TA = –40 °C to 85 °C
–
–
±55
ppm
AG
Aging, 10 years
–
–
±15
55
ppm
%
TDC
Output duty cycle
F < 450 MHz,
45
50
measured at zero crossing
F > 450 MHz,
measured at zero crossing
40
0.2
–
50
0.4
–
60
1.0
100
%
ns
ns
TR, TF
TOHZ
Output rise and fall time
Output disable time
20% and 80% of full output
swing
Time from falling edge on OE to
stopped outputs
(asynchronous)
TOE
Output enable time
Startup time
Time from rising edge on OE to
outputs at a valid frequency
(asynchronous)
–
–
–
–
100
10
ns
TLOCK
Time for CLK to reach valid
frequency measured from the
time VDD = VDD (min.) or from
PD# rising edge
ms
TJitter()
RMS phase jitter (random)
FOUT = 106.25 MHz
(12 kHz to 20 MHz)
–
1
–
ps
ps
Pre-defined factory
configurations[7]
See Note 7
Notes
4. Not 100% tested, guaranteed by design and characterization.
5. This parameter is specified in the CyClockWizard software
6. Frequency stability is the maximum variation in frequency from F . It includes initial accuracy, and variation from temperature and supply voltage.
0
7. Typical phase noise specs for factory programmed devices are listed in the Standard and Application-Specific Factory Configurations on page 4.
Document Number: 001-10179 Rev. *H
Page 8 of 15
CY2X014
Typical Output Characteristics
Figure 2. 2.5-V Supply and Termination to VDD–1.5 V, Minimum VDD and Maximum TA
0.9
0.8
0.7
0.6
0.5
0.4
1.40
1.35
1.30
1.25
1.20
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Frequency (MHz)
Figure 3. 2.5-V Supply and Termination to VDD–2 V, Minimum VDD and Maximum TA
0.9
0.8
0.7
0.6
0.5
0.4
0.90
0.85
0.80
0.75
0.70
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Frequency (MHz)
Figure 4. 3.3-V Supply and Termination to VDD–2 V, Minimum VDD and Maximum TA
0.9
0.8
0.7
0.6
0.5
0.4
1.60
1.55
1.50
1.45
1.40
0
100
200
300
400
500
600
700
0
100
200
300
400
500
600
700
Frequency (MHz)
Frequency (MHz)
Document Number: 001-10179 Rev. *H
Page 9 of 15
CY2X014
Switching Waveforms
Figure 5. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 6. Duty Cycle Timing
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Figure 7. Output Rise and Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Figure 8. Output Enable and Disable Timing
VIH
OE
V
IL
TOHZ
TOE
CLK
High-Impedance
CLK#
Termination Circuits
Figure 9. LVPECL Termination
VDD – 2 V or VDD - 1.5 V
(VDD = 2.5 V)
VDD – 2 V
(VDD = 3.3 V)
CLK
CLK
CLK#
CLK#
Document Number: 001-10179 Rev. *H
Page 10 of 15
CY2X014
Ordering Information
Part Number
Pb-free
Configuration
Package Description
Product Flow
CY2X014FLXCT
Field-programmable
6-pin ceramic LCC surface mount device (SMD) Commercial, 0 °C to 70 °C
- tape and reel
CY2X014FLXIT
Field-programmable
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
Factory-configured
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
Industrial, –40 °C to 85 °C
CY2X014LXI106T [8]
CY2X014LXI122T [8]
CY2X014LXI125T [8]
CY2X014LXI132T [8]
CY2X014LXI153T [8]
CY2X014LXI155T [8]
CY2X014LXI156T [8]
CY2X014LXI159T [8]
CY2X014LXI212T [8]
CY2X014LXI311T [8]
CY2X014LXI312T [8]
CY2X014LXI622T [8]
Some product offerings are factory-programmed customer-specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales
representative for more information.
Possible Configurations
Part Number [9]
CY2X014LXCxxxT
CY2X014LXIxxxT
Configuration
Factory-configured
Factory-configured
Package Description
6-pin ceramic LCC SMD - tape and reel
6-pin ceramic LCC SMD - tape and reel
Product Flow
Commercial, 0 °C to 70 °C
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2X014
X
-
L
X
X
XXX X
X = blank or T
blank = Tube; T = Tape and Reel
Custom part configuration code
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
L = 6-pin LCC package
X = F or blank
F = Field programmable device; blank = Factory configured device
Base part number
Company ID: CY = Cypress
Notes
8. Device configuration details are described in the Standard and Application-Specific Factory Configurations on page 4.
9. “xxx” indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or Sales Representative.
Document Number: 001-10179 Rev. *H
Page 11 of 15
CY2X014
Package Diagrams
Figure 10. 6-pin Ceramic LCC (5.0 × 3.2 × 1.3 mm) LZ06A Package Outline, 001-10044
001-10044 *B
Document Number: 001-10179 Rev. *H
Page 12 of 15
CY2X014
Acronyms
Document Conventions
Units of Measure
Acronym
Description
electrostatic discharge
field application engineer
ESD
Symbol
°C
Unit of Measure
FAE
degree Celsius
kilohertz
HBM
human body model
kHz
MHz
µA
mA
mm
ms
mV
ns
JEDEC
LCC
joint electron devices engineering council
leadless chip carrier
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
LVPECL
low-voltage positive-referenced emitter coupled
logic
OE
output enable
OTP
PCB
PLL
RMS
SMD
XO
one-time programmable
printed circuit board
phase-locked loop
root mean square
surface mount device
crystal oscillator
nanosecond
ohm
ppm
%
parts per million
percent
pF
picofarad
picosecond
volt
ps
V
W
watt
Document Number: 001-10179 Rev. *H
Page 13 of 15
CY2X014
Document History Page
Document Title: CY2X014, Low Jitter LVPECL Crystal Oscillator
Document Number: 001-10179
Orig. of
Change
Submission
Date
Rev.
ECN
Description of Change
**
504478
RGL
See ECN New datasheet
*A
1428603 JWK / SFV
See ECN Removed pull up on pin 1 and related specifications, Added items to
Programming Variables section, Added CIN specification, Modified tJ2, IIH, IIL,
I
DD and ISB specifications, Changed to a single Frequency Stability
specification, Removed Peak-to-peak Period Jitter specification, Changed pin
2 from NC to DNU, Changed max storage temperature, Title change, 2.5V
supply tightened from ±10% to ±5%, 2.5V termination option changed from
VDD-1.4V to VDD-1.5V, Added typical output characteristic curves
*B
*C
2669117
2701663
KVM /
AESA
03/05/09
05/06/09
Revised frequency stability and aging specs and conditions, Max frequency
changed from 700 MHz to 690 MHz, Duty cycle changed from 45/55 to 40/60
for freq > 450 MHz, Removed reference to CY3672 programmer, Junction and
storage temperatures changed from 125 to 135°C, IIH changed from 20 A to
115 A, IIL changed from 20 A to 50 A, Rise and fall times changed from
350 ps to 500 ps, Removed MSL spec, Changed Datasheet Status to Final.
KVM /
PYRS
General clean up
Added explanation of gaps in the frequency range
Added URL for software
Removed frequency stability paragraph under Programming Variables
Added programming variables table
Added separate IDD spec for 2.5V supply
Changed the amount of load current in IDD footnote
Changed phase jitter parameter name
Removed supply voltage as a programming variable
Changed conditions for ESD spec
Changed rise and fall times from 500 ps to 400 ps typ, added min and max
*D
2718433
WWZ /
HMT
06/12/09
No change. Submit to ECN for product launch.
*E
*F
2761943
2896548
KVM
KVM
09/10/09
03/19/10
Revised maximum output rise and fall times.
Moved parts with ‘xxx’ into new table, Possible Configurations
Updated package diagram
*G
2973338
CXQ
07/08/2010 Added Standard and Application-Specific Factory Configurations table on page
2.
Added phase jitter specs for pre-defined configurations in AC Electrical
Characteristics (note 7 refers users to the new table on page 2 for typical
specs).
Added all new factory programmed devices from the Standard and
Application-Specific Factory Configurations to Ordering Information. Added
note 8 to reference the configuration descriptions for each new device.
Changed all references to CyberClocksOnline software to CyClockWizard.
Removed section on phase noise vs jitter SW optimization.
*H
3767932
PURU
10/05/2012 Updated Package Diagrams (spec 001-10044 (Changed revision from *A to
*B)).
Added Units of Measure.
Updated in new template.
Document Number: 001-10179 Rev. *H
Page 14 of 15
CY2X014
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
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cypress.com/go/interface
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PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/psoc
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-10179 Rev. *H
Revised October 5, 2012
Page 15 of 15
CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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