CY2XP24 [CYPRESS]
Crystal to LVPECL Clock Generator One LVPECL Output Pair; 水晶LVPECL时钟发生器的一个LVPECL输出对
| 型号： | CY2XP24 |
| 厂家： | 
CYPRESS |
| 描述： | Crystal to LVPECL Clock Generator One LVPECL Output Pair |
| 文件： | 总12页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2XP24
Crystal to LVPECL Clock Generator
Features
Functional Description
■ One LVPECL Output Pair
The CY2XP24 is a PLL (phase locked loop) based high
performance clock generator. It is optimized to generate 10 Gb
Ethernet, Fibre Channel, and other high performance clock
frequencies. It produces an output frequency that is either 6.25
times or 7.5 times the crystal frequency. It uses Cypress’s low
noise VCO technology to achieve low phase jitter, that meets
both 10 Gb Ethernet, Fibre Channel, and SATA jitter
requirements. The CY2XP24 has a crystal oscillator interface
input and one LVPECL output pair.
■ Selectable output frequency: 156.25 MHz or 187.5 MHz
■ External crystal frequency: 25 MHz
■ Low root mean square (RMS) phase jitter at 156.25 MHz, using
25 MHz crystal (1.875 MHz to 20 MHz): 0.33 ps (typical)
■ Pb-free 8-Pin thin shrunk small outline package (TSSOP)
Package
■ Supply voltage: 3.3 V or 2.5 V
■ Commercial and industrial temperature ranges
Logic Block Diagram
XIN
CLK
External
Crystal
CRYSTAL
OSCILLATOR
PHASE
DETECTOR
VCO
/4
CLK#
XOUT
0 = /25
1 = /30
F_SEL
Cypress Semiconductor Corporation
Document #: 001-15705 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 7, 2011
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CY2XP24
Contents
Pinouts ..............................................................................3
Frequency Table ...............................................................4
Absolute Maximum Conditions .......................................4
Operating Conditions .......................................................4
DC Electrical Characteristics ..........................................4
AC Electrical Characteristics ...........................................5
Recommended Crystal Specifications ............................5
Parameter Measurements ................................................6
Application Information ...................................................7
Power Supply Filtering Techniques .............................7
Termination for LVPECL Output ..................................7
Crystal Input Interface .................................................7
Ordering Information ........................................................8
Ordering Code Definition .............................................8
Acronyms ........................................................................10
Document Conventions .................................................10
Units of Measure .......................................................10
Sales, Solutions, and Legal Information ......................12
Worldwide Sales and Design Support .......................12
Products ....................................................................12
PSoC Solutions .........................................................12
Document #: 001-15705 Rev. *G
Page 2 of 12
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CY2XP24
Pinouts
Figure 1. Pin Diagram - 8 Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
F_SEL
Table 1. Pin Definitions - 8 Pin TSSOP
Pin Name Type
VDD
VSS
Description
1, 8
2
Power
Power
3.3 V or 2.5 V power supply. All supply current flows through pin 1
Ground
3, 4
5
XOUT, XIN XTAL output and input Parallel resonant crystal interface
F_SEL
CMOS input
Frequency select. When HIGH, the output frequency is 7.5 times of the
crystal frequency. When LOW, the output frequency is 6.25 times of the
crystal frequency
6,7
CLK#, CLK LVPECL output
Differential clock output
Document #: 001-15705 Rev. *G
Page 3 of 12
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CY2XP24
Frequency Table
Inputs
PLL Multiplier Value
Output Frequency (MHz)
Crystal Frequency (MHz)
F_SEL
25
25
1
0
7.5
187.5
6.25
156.25
Absolute Maximum Conditions
Parameter
Description
Supply voltage
Condition
Min
–0.5
–0.5
–65
–
Max
Unit
V
VDD
–
4.4
VDD + 0.5
150
[1]
VIN
Input voltage, DC
Relative to VSS
V
TS
Temperature, vtorage
Temperature, junction
ESD protection (human body model)
Flammability rating
Non operating
C
C
V
TJ
135
ESDHBM
JEDEC STD 22-A114-B
At 1/8 in.
2000
–
UL–94
V–0
[2]
JA
Thermal resistance, junction to ambient 0 m/s airflow
100
91
C / W
1 m/s airflow
2.5 m/s airflow
87
Operating Conditions
Parameter
Description
Min
3.135
2.375
0
Max
3.465
2.625
70
Unit
V
VDD
TA
3.3 V supply voltage
2.5 V supply voltage
V
Ambient temperature, commercial
Ambient temperature, industrial
C
C
ms
-40
85
TPU
Power-up time for all VDD to reach minimum specified voltage (ensure power ramps
are monotonic)
0.05
500
DC Electrical Characteristics
Parameter
IDD
Description
Test Conditions
Min
Typ
Max
Unit
Power supply current with output VDD = 3.465 V, FOUT = 187.5 MHz,
unterminated
–
–
125
V
output unterminated
VDD = 2.625 V, FOUT = 187.5 MHz,
output unterminated
–
–
–
–
–
–
–
–
–
120
150
145
V
V
IDDT
Power supply current with output VDD = 3.465 V, FOUT = 187.5 MHz,
terminated
output terminated
VDD = 2.625V, FOUT = 187.5 MHz,
output terminated
V
VOH
VOL
LVPECL output high voltage
LVPECL output low voltage
VDD = 3.3 V or 2.5 V, RTERM = 50 to VDD –1.15
DD – 2.0 V
VDD –0.75
VDD –1.625
1000
V
V
VDD = 3.3 V or 2.5 V, RTERM = 50 to VDD –2.0
DD – 2.0 V
V
V
VOD1
LVPECL Peak-to-peak output
voltage swing
VDD = 3.3 V or 2.5 V, RTERM = 50 to
DD – 2.0 V
600
mV
V
Note
1. The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document #: 001-15705 Rev. *G
Page 4 of 12
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CY2XP24
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VOD2
LVPECL output voltage swing
V
DD = 2.5 V, RTERM = 50 to
500
–
1000
mV
(VOH - VOL
)
VDD – 1.5 V
VOCM
LVPECL output common mode VDD = 2.5 V, RTERM = 50 to
1.2
–
–
V
voltage (VOH + VOL)/2
VDD – 1.5 V
VIH
VIL
IIH
Input high voltage
0.7 x VDD
–
–
VDD + 0.3
V
Input low voltage
–0.3
–
0.3 x VDD
V
Input high current
F_SEL = VDD
F_SEL = VSS
–
115
–
µA
µA
pF
pF
IIL
Input low current
–50
–
–
[3]
CIN
Input capacitance, F_SEL
Pin capacitance, XIN & XOUT
15
4.5
–
[3]
CINX
–
–
AC Electrical Characteristics[4]
Parameter
Description
Output frequency
Conditions
Min
Typ
Max
187.5
1.0
–
Unit
FOUT
156.25
–
0.5
0.33
0.6
–
MHz
ns
[5]
TR, TF
Output rise/fall time
20 % to 80 % of full swing
–
–
[6]
TJitter()
RMS phase jitter (random)
156.25 MHz, (1.875 – 20 MHz), 3.3 V
156.25 MHz, (12 kHz – 20 MHz), 3.3 V
Measured at zero crossing point
ps
–
–
ps
[7]
TDC
Duty cycle
45
–
55
%
TLOCK
Startup time
Time for CLK to reach valid frequency
measured from the time
–
5
ms
VDD = VDD(min.)
TLFS
Re-lock time
Time for CLK to reach valid frequency
from F_SEL pin change
–
–
1
ms
Recommended Crystal Specifications[7]
Parameter
Description
Min
Max
Unit
Mode
F
Mode of oscillation
Frequency
Fundamental
25
–
25
50
7
MHz
ESR
C0
Equivalent series resistance
Shunt capacitance
–
pF
Notes
3. Not 100% tested, guaranteed by design and characterization.
4. Characterized using an 18 pF parallel resonant crystal.
5. Refer to Figure 7 on page 7.
6. Refer to Figure 4 on page 4.
7. Refer to Figure 7 on page 7.
Document #: 001-15705 Rev. *G
Page 5 of 12
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CY2XP24
Parameter Measurements
Figure 2. 3.3 V Output Load AC Test Circuit
2V
SCOPE
Z = 50
Z = 50
VDD
LVPECL
CLK
50
50
CLK#
VSS
-1.3V +/- 0.165V
Figure 3. 2.5 V Output Load AC Test Circuit
2V
SCOPE
Z = 50
Z = 50
VDD
LVPECL
CLK
50
50
CLK#
VSS
-0.5V +/- 0.125V
Figure 4. Output DC Parameters
VA
CLK
VOD
VOCM = (VA + VB)/2
CLK#
VB
Figure 5. Output Rise and Fall Time
CLK#
80% 80%
20%
20%
CLK
TR
TF
Figure 6. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
Area Under the Masked Phase Noise Plot
RMS Jitter =
Document #: 001-15705 Rev. *G
Page 6 of 12
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CY2XP24
Figure 7. Output Duty Cycle
CLK
TPW
TDC
=
TPERIOD
CLK#
TPW
TPERIOD
Figure 9. LVPECL Output Termination
Application Information
3.3V
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins can degrade performance. To achieve optimum jitter
performance, use good power supply isolation practices.
Figure 8 illustrates a typical filtering scheme. Because all current
flows through pin 1, the resistance and inductance between this
pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A 1 to 10 µF ceramic or
tantalum capacitor is located in the general vicinity of this device
and may be shared with other devices.
125
125
Z0 = 50
Z0 = 50
CLK
IN
CLK#
84
84
Figure 8. Power Supply Filtering
Crystal Input Interface
The CY2XP24 is characterized with 18 pF parallel resonant
crystals. The capacitor values shown in Figure 10 are
determined using a 25 MHz 18 pF parallel resonant crystal and
are chosen to minimize the ppm error. Note that the optimal
values for C1 and C2 depend on the parasitic trace capacitance
and are therefore layout dependent.
V
DD
(Pin 8)
3.3V
10µ
V
DD
(Pin 1)
F
0.01 µF
F
Figure 10. Crystal Input Interface
XIN
C1
30 pF
Termination for LVPECL Output
X1
Device
18 pF Parallel
The CY2XP24 implements its LVPECL driver with a current
steering design. For proper operation, it requires a 50 ohm dc
termination on each of the two output signals. For 3.3 V
operation, this data sheet specifies output levels for termination
Crystal
XOUT
C2
27 pF
to V –2.0 V. This termination voltage can also be used for V
DD
DD
= 2.5 V operation, or it can be terminated to V -1.5 V. Note that
DD
it is also possible to terminate with 50 ohms to ground (V ), but
SS
the high and low signal levels differ from the data sheet values.
Termination resistors are best located close to the destination
device. To avoid reflections, trace characteristic impedance (Z )
0
should match the termination impedance. Figure 9 shows a
standard termination scheme.
Document #: 001-15705 Rev. *G
Page 7 of 12
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CY2XP24
Ordering Information
Part Number
CY2XP24ZXC
Package Type
Product Flow
8-Pin TSSOP
Commercial, 0 C to 70 C
Commercial, 0 C to 70 C
Industrial, -40 C to 85 C
Industrial, -40 C to 85 C
CY2XP24ZXCT
CY2XP24ZXI
8-Pin TSSOP–Tape and Reel
8-Pin TSSOP
CY2XP24ZXIT
8-Pin TSSOP–Tape and Reel
Ordering Code Definition
CY xx xxxx
C/I
Z X
T
T = Tape and Reel
Temperature Range: C = Commercial, I = Industrial
Pb-free
Package Type
Part Identifier
Family
Company ID: CY = Cypress
Document #: 001-15705 Rev. *G
Page 8 of 12
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CY2XP24
Package Drawing and Dimensions
Figure 11. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
51-85093 *C
Document #: 001-15705 Rev. *G
Page 9 of 12
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CY2XP24
Acronyms
Acronym
CLKOUT
CMOS
DPM
Description
Clock output
Complementary metal oxide semiconductor
Die pick map
EPROM
LVDS
LVPECL
NTSC
OE
Erasable programmable read only memory
Low-voltage differential signaling
Low voltage positive emitter coupled logic
National television system committee
Output enable
PAL
Phase alternate line
PD
Power down
PLL
Phase locked loop
PPM
Parts per million
TTL
Transistor transistor logic
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
kilohertz
kHz
k
kilohms
MHz
M
µA
megahertz
megaohms
microamperes
microseconds
microvolts
µs
µV
µVrms
mA
mm
ms
mV
nA
microvolts root-mean-square
milliamperes
millimeters
milliseconds
millivolts
nanoamperes
nanoseconds
nanovolts
ns
nV
ohms
Document #: 001-15705 Rev. *G
Page 10 of 12
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CY2XP24
Document History Page
Document Title: CY2XP24 Crystal to LVPECL Clock Generator
Document Number: 001-15705
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
1285703
See ECN
WWZ/KVM/ New data sheet
ARI
*A
*B
1451704
2669117
See ECN
WWZ/AESA Added I-temp devices
03/05/2009
KVM/AESA Changed crystal frequency and output frequencies
Updated phase jitter value
Rise & fall times changed from 350 ps to 500 ps (typ.)
Junction temperature changed from 125C to 135C
Changed IIL and IIH values
Entered value for IDD
Removed MSL spec
Changed Data Sheet Status to Final
*C
2700242
04/30/2009
KVM/PYRS Typos: changed VCC to VDD, changed ps to MHz
Changed footnote about external power dissipation
Reformatted AC and DC tables
Changed LVPECL parameters from VPP to VOD and VOCM
Added CINX spec
Added IDD for 2.5V
Added TLOCK timing
Revised text in Application Information section
Changed recommended crystal load capacitor values
*D
*E
2718433
2767308
06/12/2009
09/22/2009
WWZ/HMT No change. Submit to ECN for product launch.
KVM
Add phase jitter spec for 12 kHz - 20 MHz integration range
Add I spec for unterminated outputs
DD
Change parameter name for I (terminated outputs) from I to I
DD
DD
DDT
Remove I footnote about externally dissipated current
DD
Add footnote reference to C and C :not 100% tested
IN
INX
Add max limit for T , T : 1.0 ns
R
F
Change T
max from 10 ms to 5 ms
LOCK
Split out parameter T
from T
LFS
LOCK
*F
2896121
3218841
03/19/2010
03/07/2011
KVM
Updated Package Diagram (Figure 11)
*G
BASH
Updated as per template
Added Acronyms and Units of Measure table
Added Ordering Code Definition details
Updated package diagram 51-85093 from *B to *C
Document #: 001-15705 Rev. *G
Page 11 of 12
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CY2XP24
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15705 Rev. *G
Revised April 7, 2011
Page 12 of 12
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