CY3LV002-10JI [CYPRESS]
Configuration Memory, 2MX1, Serial, CMOS, PQCC20, PLASTIC, MS-018AA, LCC-20;
| 型号： | CY3LV002-10JI |
| 厂家： | 
CYPRESS |
| 描述： | Configuration Memory, 2MX1, Serial, CMOS, PQCC20, PLASTIC, MS-018AA, LCC-20 时钟 PC 内存集成电路 |
| 文件： | 总9页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CY3LV002
2-Mbit CPLD Boot EEPROM
• Cascadable read-back to support higher-density
CPLDs
Features
• EE Reprogrammable 2,097,152 x 1 bit serial memory
designed to store configuration data for complex
programmable logic devices (CPLDs)
• In-System Programmable via two-wire bus using
Cypress’s CYDH2200E programming kits
• Low-power CMOS EEPROM process
• Available in PLCC package (pin compatible across
product family)
• Operates at 3.3V VCC
• System-friendly READY pin
• Low-power standby mode
• Simple interface to SRAM-based CPLDs
• CompatiblewithCypressDelta39K™&Quantum38K™
CPLDs
Block Diagram
CEO (A2)
Delta39K and Quantum38K are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03044 Rev. **
Revised October 16, 2001
PRELIMINARY
CY3LV002
Functional Description
Controlling the CY3LV CPLD Boot EEPROMs
During Configuration
The CY3LV002 (high-density CY3LV series) CPLD boot
EEPROM provides an easy-to-use, cost-effective configura-
tion memory for complex programmable logic devices. The
CY3LV series is packaged in the popular 20-pin PLCC. These
devices support a system-friendly READY pin, which signifies
a “good” power level to the CPLD and can be used to ensure
reliable system power-up.
Most connections between the CPLD device and the CY3LV
boot EEPROM are simple and self-explanatory. Figure 1
shows the five-signal interface required between the
Delta39K/Quantum38K CPLD and the CY3LV boot EEPROM
device.
• TheDATAoutputofthebootEEPROMdrivestheDATAinput
of the CPLD.
• The master CPLD CCLK output drives the CLK input of the
boot EEPROM.
• The CPLD CCE pin drives the CE input of the boot
EEPROM.
The CY3LV series boot EEPROMs can be programmed with
industry-standard programmers or Cypress’s CYDH2200E
CPLD boot EEPROM programming kit. Please refer to the
data sheet “CYDH2200E CPLD Boot PROM Programming Kit”
for details.
• The RESET/OE input of the boot EEPROM is driven by the
CPLD RESET pin.
CPLD Master Serial Mode Summary
• The READY pin of the boot EEPROM is connected to the
The I/O and logic functions of the CPLD and their associated
interconnections are established by loading configuration data
(bitstream) into the CPLD. This configuration data is loaded
either automatically upon power-up, or upon issuing a JTAG-
command. The configuration data is stored in the internal
Flash memory (Self-Boot packages only) or in the external
CPLD boot EEPROM memory. This data is loaded from the
appropriate memory depending on the state of the CPLD
mode select pin (MSEL).
RECONFIG pin of the CPLD.
The READY pin is available as an open-collector indicator of
the device’s RESET status; it is driven LOW while the device
is in its POWER-ON RESET cycle and released (three-stated)
when the cycle is complete. The rising edge of the READY
(RECONFIG) signal causes the CPLD to start configuring.
The CONFIG_DONE, CCE, and RESET outputs of the CPLD
are set LOW, CCLK is activated, and CPLD starts receiving
configuration dataon the DATA pin. After theconfigurationdata
is shifted in, the CPLD device deactivates the CCLK and sets
CCE, RESET and CONFIG_DONE HIGH.
In Master Serial mode (when MSEL = 1), the CPLD automat-
ically loads the configuration program from an external mem-
ory, i.e., CY3LV CPLD boot EEPROM. These EEPROMs have
been designed for compatibility with the Master Serial Mode.
This document discusses the interface between Cypress’s
SRAM-based CPLDs (Quantum38K and Delta39K) and
CY3LV EEPROMs.
A HIGH level on the RESET/OE input during CPLD reset
clears the boot EEPROM’s internal address pointer and sub-
sequent reconfiguration starts at the beginning.
The CEO output of any CY3LV drives the CE input of the next
CY3LV in a cascade chain of EEPROMs.
For details on other modes of configuration for these CPLDs,
please refer to the application note titled “Configuring
Delta39K/Quantum38K.”
SER_EN must be connected to VCC, except during In-System
Programming of the EEPROM.
For details on the hardware set-up and system programming
of the CPLD and Boot EEPROM, please refer to the applica-
tion note titled “Configuring Delta39K/Quantum38K.”
3.3 V
3.3 V
VCCCNFG
VCCPRG
SER_EN
DATA
DATA
Reset
Vcc
Reset/OE
CE
CCE
Delta39K
0.1µF
CCLK
MSEL
CLK
GND
READY
CY3LV002
Reconfig
Reconfig
Config_Done
GND
1µF
All resistors are 4.7 k
Ω
Figure 1. Interface between Delta39K/Quantum38K CPLD and CY3LV Boot EEPROM
Document #: 38-03044 Rev. **
Page 2 of 9
PRELIMINARY
CY3LV002
dard programmers or Cypress’s CYDH2200E boot PROM pro-
gramming kit.
Cascading CY3LV CPLD Boot EEPROMs
For future CPLDs that require larger configuration memories,
cascaded CPLD boot EEPROMs provide additional memory.
Note: Every time the boot EEPROM is reprogrammed, care
should be taken to select the RESET polarity to HIGH in the
programmer software.
As the last bit from the first boot EEPROM is read, the clock
signal to the boot EEPROM asserts its CEO output LOW and
disables its DATA line driver. The second boot EEPROM
recognizes the LOW level on its CEinput and enables its DATA
output.
Programming Mode
The programming mode is entered by bringing SER_EN LOW.
In this mode the chip can be programmed by the two-wire
serial bus. The programming is done with a VCC (3.3V nomi-
nal) supply only. The CY3LV parts are Read/Write at 3.3V
nominal.
After configuration is complete, the address counters of all
cascaded boot EEPROMs are reset if the RESET/OE on each
boot EEPROM is driven to its active (HIGH) level.
CY3LV Series RESET Polarity
Standby Mode
The CY3LV series CPLD boot EEPROMs allow the user to
program the RESET polarity as either RESET/OE or
RESET/OE. Cypress’s SRAM-based CPLDs (Delta39K and
Quantum38K) require the RESET pin to be programmed ac-
tive HIGH, i.e., as RESET/OE. CY3LV boot EEPROMs are
shipped from the factory with the reset polarity programmed
active HIGH. This polarity can be verified using industry-stan-
The CY3LV enters a low-power standby mode whenever CE is
asserted HIGH. In this mode, the boot EEPROM consumes
less than 100 µA of current at 3.3V with CMOS level inputs.
The output remains in a high-impedance state regardless of
the state of the OE input.
Document #: 38-03044 Rev. **
Page 3 of 9
PRELIMINARY
CY3LV002
.
Table 1. Pin Configurations
20-pin
PLCC
Name
I/O
Description
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bidirectional pin for
programming.
4
5
CLK
I
I
Clock input. Increments the internal address and bit counter for reading and programming.
WP1
WRITE PROTECT (1). Protects portions of memory during programming. Disabled by default
due to internal pull-down resistor. This input pin is not used during CPLD loading operations.
6
RESET /
OE
I
RESET/Output Enable Input (when SER_EN is HIGH). A LOW level on both the CE and
RESET/OE inputs enables the data output driver. A HIGH level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. Delta39K/Quantum38K CPLDs require this pin to be programmed as
RESET/OE, so this document describes the pin as RESET/OE.
7
8
WP2
CE
I
I
WRITE PROTECT (2). Protects portions of memory during programming. Disabled by default
due to internal pull-down resistor. This input pin is not used during CPLD loading operations.
Chip Enable Input. Used for device selection. A LOW level on both CE and OE enables the
data output driver. A HIGH level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will not enable/disable the device
in two-wire Serial Programming Mode (i.e., when SER_EN is LOW).
10
14
GND
CEO
Ground pin. A 0.1-µF decoupling capacitor between VCC and GND is recommended.
O
Chip Enable Output. Asserted LOW on the clock cycle following the last bit read from the
memory. It will stay LOW as long as CE and OE are both LOW. It will then follow CE until OE
goes HIGH. Thereafter, CEO will stay HIGH until the entire EEPROM is read again.
A2
I
O
I
Device Selection Input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is LOW).
15
17
20
READY
SER_EN
VCC
Open collector reset state indicator. Driven LOW during power-up reset, released when
power-up is complete (recommend a 4.7-kΩ pull-up on this pin, if used).
Serial enable must be held HIGH during CPLD loading operations. Bringing SER_EN LOW
enables two-wire Serial Programming Mode.
+3.3V power supply pin.
Pin Configurations
CLK
WP1
4
5
6
7
8
18 NC
17 SER_EN
16 NC
RESET/OE
WP2
15 READY
14 CEO (A2)
CE
Document #: 38-03044 Rev. **
Page 4 of 9
PRELIMINARY
CY3LV002
Voltage on Any Pin
Maximum Ratings
with Respect to Ground......................... –0.1V to VCC + 0.5V
Supply Voltage (VCC) .....................................–0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16in.) ...........260°C
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Temperature...............................–55°C to +125°C
Storage Temperature .................................–65°C to +150°C
Operating Range
Range
Ambient Temperature
Junction Temperature
CY3LV002 (VCC)
Min
Max
3.5 V
3.5 V
3.5 V
Commercial
0°C to + 70°C
–40°C to + 85°C
–55°C to + 125°C
0°C to + 90°C
–40°C to + 125°C
–55°C to + 130°C
3.0 V
3.0 V
3.0 V
Industrial
Military
3.3V Device Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Min.
2.0
0
Max.
VCC
0.8
Unit
High-level input voltage
Low-level input voltage
V
V
VIL
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level output voltage (IOH = –2.5 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = –2 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = –2 mA)
Low-level output voltage (IOL = +2.5 mA)
Supply current, active mode
Commercial
Industrial
Military
2.4
V
0.4
0.4
V
2.4
2.4
V
V
V
0.4
5
V
mA
µA
µA
µA
Input or output leakage current (VIN = VCC or GND)
Supply current, standby mode
–10
10
ICCS
Commercial
100
100
Industrial/Military
Document #: 38-03044 Rev. **
Page 5 of 9
PRELIMINARY
CY3LV002
.
Switching Characteristics for CY3LV002 (3.3V) Over the Operating Range
Commercial
Industrial
Parameter
Description
Min.
Max.
50
Min.
Max.
Unit
ns
[1]
tOE
OE to Data Delay
CE to Data Delay
CLK to Data Delay
55
60
60
[1]
tCE
55
ns
[1]
tCAC
55
ns
tOH
Data Hold From CE, OE, or CLK
CE or OE to Data Float Delay
0
0
ns
[2]
tDF
50
50
ns
tLC
CLK Low Time
25
25
30
0
25
25
35
0
ns
tHC
CLK High Time
ns
tSCE
tHCE
tHOE
CE Set-up Time to CLK (to guarantee proper counting)
CE Hold Time from CLK (to guarantee proper counting)
OE High Time (guarantees counter is reset)
Max. Input Clock Frequency
ns
ns
25
15
25
10
ns
FMAX
MHz
Switching Characteristics for CY3LV002 (3.3V) when Cascading Over the Operating Range
Commercial
Min. Max.
Industrial
Parameter
Description
CLK to Data Float Delay
Min.
Max.
Unit
ns
[2]
tCDF
50
50
35
35
50
55
40
35
[1]
tOCK
CLK to CEO Delay
ns
[1]
tOCE
CE to CEO Delay
ns
[1]
tOOE
RESET/OE to CEO Delay
MAX Input Clock Frequency
ns
FMAX
12.5
10
MHz
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ±200 mV from steady state active levels.
AC Characteristics
Document #: 38-03044 Rev. **
Page 6 of 9
PRELIMINARY
CY3LV002
AC Characteristics when Cascading
3.3V Ordering Information
Package
Name
Operating
Range
Memory Size
Ordering Code
Package Type
2M
CY3LV002-10JC
CY3LV002-10JI
20J
20J
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
Commercial
Industrial
Document #: 38-03044 Rev. **
Page 7 of 9
PRELIMINARY
CY3LV002
Package Diagrams: 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC Standard MS-018AA
Document #: 38-03044 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY3LV002
Document Title: CY3LV002 2-Mbit CPLD BOOT EEPROM DATASHEET
Document Number: 38-03044
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
109139
TBD
RN
New Data Sheet
Document #: 38-03044 Rev. **
Page 9 of 9
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